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GET /api/patches/1882156/?format=api
{ "id": 1882156, "url": "http://patchwork.ozlabs.org/api/patches/1882156/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20240103173349.398526-34-alex.bennee@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20240103173349.398526-34-alex.bennee@linaro.org>", "list_archive_url": null, "date": "2024-01-03T17:33:39", "name": "[v2,33/43] gdbstub: Infer number of core registers from XML", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c7a72b29be71a81b2f75b3927c9f1542b57976c7", "submitter": { "id": 39532, "url": "http://patchwork.ozlabs.org/api/people/39532/?format=api", "name": "Alex Bennée", "email": "alex.bennee@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20240103173349.398526-34-alex.bennee@linaro.org/mbox/", "series": [ { "id": 388742, "url": "http://patchwork.ozlabs.org/api/series/388742/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=388742", "date": "2024-01-03T17:33:08", "name": "testing and plugin updates for 9.0 (pre-PR)", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/388742/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1882156/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1882156/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=X9Pc2cDX;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Iglesias\" <edgar.iglesias@gmail.com>,\n Eduardo Habkost <eduardo@habkost.net>,\n Pierrick Bouvier <pierrick.bouvier@linaro.org>, qemu-riscv@nongnu.org,\n Alistair Francis <alistair.francis@wdc.com>,\n Akihiko Odaki <akihiko.odaki@daynix.com>", "Subject": "[PATCH v2 33/43] gdbstub: Infer number of core registers from XML", "Date": "Wed, 3 Jan 2024 17:33:39 +0000", "Message-Id": "<20240103173349.398526-34-alex.bennee@linaro.org>", "X-Mailer": "git-send-email 2.39.2", "In-Reply-To": "<20240103173349.398526-1-alex.bennee@linaro.org>", "References": "<20240103173349.398526-1-alex.bennee@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::333;\n envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x333.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001,\n T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Akihiko Odaki <akihiko.odaki@daynix.com>\n\nGDBFeature has the num_regs member so use it where applicable to\nremove magic numbers.\n\nSigned-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>\nMessage-Id: <20231213-gdb-v17-8-777047380591@daynix.com>\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\n---\n include/hw/core/cpu.h | 3 ++-\n target/s390x/cpu.h | 2 --\n gdbstub/gdbstub.c | 5 ++++-\n target/arm/cpu.c | 1 -\n target/arm/cpu64.c | 1 -\n target/avr/cpu.c | 1 -\n target/hexagon/cpu.c | 1 -\n target/i386/cpu.c | 2 --\n target/loongarch/cpu.c | 2 --\n target/m68k/cpu.c | 1 -\n target/microblaze/cpu.c | 1 -\n target/riscv/cpu.c | 1 -\n target/rx/cpu.c | 1 -\n target/s390x/cpu.c | 1 -\n 14 files changed, 6 insertions(+), 17 deletions(-)", "diff": "diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h\nindex c0c8320413e..a6214610603 100644\n--- a/include/hw/core/cpu.h\n+++ b/include/hw/core/cpu.h\n@@ -127,7 +127,8 @@ struct SysemuCPUOps;\n * @gdb_adjust_breakpoint: Callback for adjusting the address of a\n * breakpoint. Used by AVR to handle a gdb mis-feature with\n * its Harvard architecture split code and data.\n- * @gdb_num_core_regs: Number of core registers accessible to GDB.\n+ * @gdb_num_core_regs: Number of core registers accessible to GDB or 0 to infer\n+ * from @gdb_core_xml_file.\n * @gdb_core_xml_file: File name for core registers GDB XML description.\n * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop\n * before the insn which triggers a watchpoint rather than after it.\ndiff --git a/target/s390x/cpu.h b/target/s390x/cpu.h\nindex fa3aac4f973..2d81fbfea5c 100644\n--- a/target/s390x/cpu.h\n+++ b/target/s390x/cpu.h\n@@ -491,8 +491,6 @@ static inline void cpu_get_tb_cpu_state(CPUS390XState *env, vaddr *pc,\n #define S390_R13_REGNUM 15\n #define S390_R14_REGNUM 16\n #define S390_R15_REGNUM 17\n-/* Total Core Registers. */\n-#define S390_NUM_CORE_REGS 18\n \n static inline void setcc(S390CPU *cpu, uint64_t cc)\n {\ndiff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c\nindex 1d5c1da1b24..801eba9a0b0 100644\n--- a/gdbstub/gdbstub.c\n+++ b/gdbstub/gdbstub.c\n@@ -546,9 +546,12 @@ void gdb_init_cpu(CPUState *cpu)\n gdb_register_feature(cpu, 0,\n cc->gdb_read_register, cc->gdb_write_register,\n feature);\n+ cpu->gdb_num_regs = cpu->gdb_num_g_regs = feature->num_regs;\n }\n \n- cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs;\n+ if (cc->gdb_num_core_regs) {\n+ cpu->gdb_num_regs = cpu->gdb_num_g_regs = cc->gdb_num_core_regs;\n+ }\n }\n \n void gdb_register_coprocessor(CPUState *cpu,\ndiff --git a/target/arm/cpu.c b/target/arm/cpu.c\nindex 650e09b29c5..0a02d16220b 100644\n--- a/target/arm/cpu.c\n+++ b/target/arm/cpu.c\n@@ -2498,7 +2498,6 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data)\n #ifndef CONFIG_USER_ONLY\n cc->sysemu_ops = &arm_sysemu_ops;\n #endif\n- cc->gdb_num_core_regs = 26;\n cc->gdb_arch_name = arm_gdb_arch_name;\n cc->gdb_get_dynamic_xml = arm_gdb_get_dynamic_xml;\n cc->gdb_stop_before_watchpoint = true;\ndiff --git a/target/arm/cpu64.c b/target/arm/cpu64.c\nindex 8e30a7993ea..869d8dd24ee 100644\n--- a/target/arm/cpu64.c\n+++ b/target/arm/cpu64.c\n@@ -793,7 +793,6 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void *data)\n \n cc->gdb_read_register = aarch64_cpu_gdb_read_register;\n cc->gdb_write_register = aarch64_cpu_gdb_write_register;\n- cc->gdb_num_core_regs = 34;\n cc->gdb_core_xml_file = \"aarch64-core.xml\";\n cc->gdb_arch_name = aarch64_gdb_arch_name;\n \ndiff --git a/target/avr/cpu.c b/target/avr/cpu.c\nindex 999c010dedb..4bab9e22728 100644\n--- a/target/avr/cpu.c\n+++ b/target/avr/cpu.c\n@@ -251,7 +251,6 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)\n cc->gdb_read_register = avr_cpu_gdb_read_register;\n cc->gdb_write_register = avr_cpu_gdb_write_register;\n cc->gdb_adjust_breakpoint = avr_cpu_gdb_adjust_breakpoint;\n- cc->gdb_num_core_regs = 35;\n cc->gdb_core_xml_file = \"avr-cpu.xml\";\n cc->tcg_ops = &avr_tcg_ops;\n }\ndiff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c\nindex 65ac9c75ad0..71678ef9c67 100644\n--- a/target/hexagon/cpu.c\n+++ b/target/hexagon/cpu.c\n@@ -384,7 +384,6 @@ static void hexagon_cpu_class_init(ObjectClass *c, void *data)\n cc->get_pc = hexagon_cpu_get_pc;\n cc->gdb_read_register = hexagon_gdb_read_register;\n cc->gdb_write_register = hexagon_gdb_write_register;\n- cc->gdb_num_core_regs = TOTAL_PER_THREAD_REGS;\n cc->gdb_stop_before_watchpoint = true;\n cc->gdb_core_xml_file = \"hexagon-core.xml\";\n cc->disas_set_info = hexagon_cpu_disas_set_info;\ndiff --git a/target/i386/cpu.c b/target/i386/cpu.c\nindex 95d5f16cd5e..b14c97169cd 100644\n--- a/target/i386/cpu.c\n+++ b/target/i386/cpu.c\n@@ -7969,10 +7969,8 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data)\n cc->gdb_arch_name = x86_gdb_arch_name;\n #ifdef TARGET_X86_64\n cc->gdb_core_xml_file = \"i386-64bit.xml\";\n- cc->gdb_num_core_regs = 66;\n #else\n cc->gdb_core_xml_file = \"i386-32bit.xml\";\n- cc->gdb_num_core_regs = 50;\n #endif\n cc->disas_set_info = x86_disas_set_info;\n \ndiff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c\nindex 07319d6fb97..dfac51a7f60 100644\n--- a/target/loongarch/cpu.c\n+++ b/target/loongarch/cpu.c\n@@ -851,7 +851,6 @@ static void loongarch32_cpu_class_init(ObjectClass *c, void *data)\n {\n CPUClass *cc = CPU_CLASS(c);\n \n- cc->gdb_num_core_regs = 35;\n cc->gdb_core_xml_file = \"loongarch-base32.xml\";\n cc->gdb_arch_name = loongarch32_gdb_arch_name;\n }\n@@ -865,7 +864,6 @@ static void loongarch64_cpu_class_init(ObjectClass *c, void *data)\n {\n CPUClass *cc = CPU_CLASS(c);\n \n- cc->gdb_num_core_regs = 35;\n cc->gdb_core_xml_file = \"loongarch-base64.xml\";\n cc->gdb_arch_name = loongarch64_gdb_arch_name;\n }\ndiff --git a/target/m68k/cpu.c b/target/m68k/cpu.c\nindex 11c7e0a7902..a27194b2a59 100644\n--- a/target/m68k/cpu.c\n+++ b/target/m68k/cpu.c\n@@ -564,7 +564,6 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)\n #endif\n cc->disas_set_info = m68k_cpu_disas_set_info;\n \n- cc->gdb_num_core_regs = 18;\n cc->tcg_ops = &m68k_tcg_ops;\n }\n \ndiff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c\nindex 1998f69828f..9d3fbfe1592 100644\n--- a/target/microblaze/cpu.c\n+++ b/target/microblaze/cpu.c\n@@ -428,7 +428,6 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)\n cc->sysemu_ops = &mb_sysemu_ops;\n #endif\n device_class_set_props(dc, mb_properties);\n- cc->gdb_num_core_regs = 32 + 25;\n cc->gdb_core_xml_file = \"microblaze-core.xml\";\n \n cc->disas_set_info = mb_disas_set_info;\ndiff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex 673e937a5d8..a3a98230ca8 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -1688,7 +1688,6 @@ static void riscv_cpu_common_class_init(ObjectClass *c, void *data)\n cc->get_pc = riscv_cpu_get_pc;\n cc->gdb_read_register = riscv_cpu_gdb_read_register;\n cc->gdb_write_register = riscv_cpu_gdb_write_register;\n- cc->gdb_num_core_regs = 33;\n cc->gdb_stop_before_watchpoint = true;\n cc->disas_set_info = riscv_cpu_disas_set_info;\n #ifndef CONFIG_USER_ONLY\ndiff --git a/target/rx/cpu.c b/target/rx/cpu.c\nindex 9cc9d9d15ec..cf11b189116 100644\n--- a/target/rx/cpu.c\n+++ b/target/rx/cpu.c\n@@ -231,7 +231,6 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data)\n cc->gdb_write_register = rx_cpu_gdb_write_register;\n cc->disas_set_info = rx_cpu_disas_set_info;\n \n- cc->gdb_num_core_regs = 26;\n cc->gdb_core_xml_file = \"rx-core.xml\";\n cc->tcg_ops = &rx_tcg_ops;\n }\ndiff --git a/target/s390x/cpu.c b/target/s390x/cpu.c\nindex 6acfa1c91b2..6fba9497295 100644\n--- a/target/s390x/cpu.c\n+++ b/target/s390x/cpu.c\n@@ -362,7 +362,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data)\n s390_cpu_class_init_sysemu(cc);\n #endif\n cc->disas_set_info = s390_cpu_disas_set_info;\n- cc->gdb_num_core_regs = S390_NUM_CORE_REGS;\n cc->gdb_core_xml_file = \"s390x-core64.xml\";\n cc->gdb_arch_name = s390_gdb_arch_name;\n \n", "prefixes": [ "v2", "33/43" ] }