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GET /api/patches/1882115/?format=api
{ "id": 1882115, "url": "http://patchwork.ozlabs.org/api/patches/1882115/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20240103173349.398526-27-alex.bennee@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20240103173349.398526-27-alex.bennee@linaro.org>", "list_archive_url": null, "date": "2024-01-03T17:33:32", "name": "[v2,26/43] target/arm: Use GDBFeature for dynamic XML", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f464b683dd402192118306be453f70b6adcd2410", "submitter": { "id": 39532, "url": "http://patchwork.ozlabs.org/api/people/39532/?format=api", "name": "Alex Bennée", "email": "alex.bennee@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20240103173349.398526-27-alex.bennee@linaro.org/mbox/", "series": [ { "id": 388742, "url": "http://patchwork.ozlabs.org/api/series/388742/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=388742", "date": "2024-01-03T17:33:08", "name": "testing and plugin updates for 9.0 (pre-PR)", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/388742/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1882115/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1882115/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=O2usBBJJ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Iglesias\" <edgar.iglesias@gmail.com>,\n Eduardo Habkost <eduardo@habkost.net>,\n Pierrick Bouvier <pierrick.bouvier@linaro.org>, qemu-riscv@nongnu.org,\n Alistair Francis <alistair.francis@wdc.com>,\n Akihiko Odaki <akihiko.odaki@daynix.com>", "Subject": "[PATCH v2 26/43] target/arm: Use GDBFeature for dynamic XML", "Date": "Wed, 3 Jan 2024 17:33:32 +0000", "Message-Id": "<20240103173349.398526-27-alex.bennee@linaro.org>", "X-Mailer": "git-send-email 2.39.2", "In-Reply-To": "<20240103173349.398526-1-alex.bennee@linaro.org>", "References": "<20240103173349.398526-1-alex.bennee@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::42c;\n envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x42c.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001,\n T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Akihiko Odaki <akihiko.odaki@daynix.com>\n\nIn preparation for a change to use GDBFeature as a parameter of\ngdb_register_coprocessor(), convert the internal representation of\ndynamic feature from plain XML to GDBFeature.\n\nSigned-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>\nAcked-by: Richard Henderson <richard.henderson@linaro.org>\nMessage-Id: <20231213-gdb-v17-1-777047380591@daynix.com>\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\n---\n target/arm/cpu.h | 21 +++---\n target/arm/internals.h | 2 +-\n target/arm/gdbstub.c | 142 ++++++++++++++++++++---------------------\n target/arm/gdbstub64.c | 95 +++++++++++++--------------\n 4 files changed, 123 insertions(+), 137 deletions(-)", "diff": "diff --git a/target/arm/cpu.h b/target/arm/cpu.h\nindex a0282e0d281..b2f8ac81f06 100644\n--- a/target/arm/cpu.h\n+++ b/target/arm/cpu.h\n@@ -25,6 +25,7 @@\n #include \"hw/registerfields.h\"\n #include \"cpu-qom.h\"\n #include \"exec/cpu-defs.h\"\n+#include \"exec/gdbstub.h\"\n #include \"qapi/qapi-types-common.h\"\n \n /* ARM processors have a weak memory model */\n@@ -136,23 +137,21 @@ enum {\n */\n \n /**\n- * DynamicGDBXMLInfo:\n- * @desc: Contains the XML descriptions.\n- * @num: Number of the registers in this XML seen by GDB.\n+ * DynamicGDBFeatureInfo:\n+ * @desc: Contains the feature descriptions.\n * @data: A union with data specific to the set of registers\n * @cpregs_keys: Array that contains the corresponding Key of\n * a given cpreg with the same order of the cpreg\n * in the XML description.\n */\n-typedef struct DynamicGDBXMLInfo {\n- char *desc;\n- int num;\n+typedef struct DynamicGDBFeatureInfo {\n+ GDBFeature desc;\n union {\n struct {\n uint32_t *keys;\n } cpregs;\n } data;\n-} DynamicGDBXMLInfo;\n+} DynamicGDBFeatureInfo;\n \n /* CPU state for each instance of a generic timer (in cp15 c14) */\n typedef struct ARMGenericTimer {\n@@ -878,10 +877,10 @@ struct ArchCPU {\n uint64_t *cpreg_vmstate_values;\n int32_t cpreg_vmstate_array_len;\n \n- DynamicGDBXMLInfo dyn_sysreg_xml;\n- DynamicGDBXMLInfo dyn_svereg_xml;\n- DynamicGDBXMLInfo dyn_m_systemreg_xml;\n- DynamicGDBXMLInfo dyn_m_secextreg_xml;\n+ DynamicGDBFeatureInfo dyn_sysreg_feature;\n+ DynamicGDBFeatureInfo dyn_svereg_feature;\n+ DynamicGDBFeatureInfo dyn_m_systemreg_feature;\n+ DynamicGDBFeatureInfo dyn_m_secextreg_feature;\n \n /* Timers used by the generic (architected) timer */\n QEMUTimer *gt_timer[NUM_GTIMERS];\ndiff --git a/target/arm/internals.h b/target/arm/internals.h\nindex 143d57c0fe4..1136710741f 100644\n--- a/target/arm/internals.h\n+++ b/target/arm/internals.h\n@@ -1446,7 +1446,7 @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)\n }\n \n #ifdef TARGET_AARCH64\n-int arm_gen_dynamic_svereg_xml(CPUState *cpu, int base_reg);\n+GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cpu, int base_reg);\n int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);\n int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);\n int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);\ndiff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c\nindex 28f546a5ff9..5949adfb31a 100644\n--- a/target/arm/gdbstub.c\n+++ b/target/arm/gdbstub.c\n@@ -26,11 +26,11 @@\n #include \"cpu-features.h\"\n #include \"cpregs.h\"\n \n-typedef struct RegisterSysregXmlParam {\n+typedef struct RegisterSysregFeatureParam {\n CPUState *cs;\n- GString *s;\n+ GDBFeatureBuilder builder;\n int n;\n-} RegisterSysregXmlParam;\n+} RegisterSysregFeatureParam;\n \n /* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect\n whatever the target description contains. Due to a historical mishap\n@@ -216,7 +216,7 @@ static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg)\n const ARMCPRegInfo *ri;\n uint32_t key;\n \n- key = cpu->dyn_sysreg_xml.data.cpregs.keys[reg];\n+ key = cpu->dyn_sysreg_feature.data.cpregs.keys[reg];\n ri = get_arm_cp_reginfo(cpu->cp_regs, key);\n if (ri) {\n if (cpreg_field_is_64bit(ri)) {\n@@ -233,34 +233,32 @@ static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg)\n return 0;\n }\n \n-static void arm_gen_one_xml_sysreg_tag(GString *s, DynamicGDBXMLInfo *dyn_xml,\n+static void arm_gen_one_feature_sysreg(GDBFeatureBuilder *builder,\n+ DynamicGDBFeatureInfo *dyn_feature,\n ARMCPRegInfo *ri, uint32_t ri_key,\n- int bitsize, int regnum)\n+ int bitsize, int n)\n {\n- g_string_append_printf(s, \"<reg name=\\\"%s\\\"\", ri->name);\n- g_string_append_printf(s, \" bitsize=\\\"%d\\\"\", bitsize);\n- g_string_append_printf(s, \" regnum=\\\"%d\\\"\", regnum);\n- g_string_append_printf(s, \" group=\\\"cp_regs\\\"/>\");\n- dyn_xml->data.cpregs.keys[dyn_xml->num] = ri_key;\n- dyn_xml->num++;\n+ gdb_feature_builder_append_reg(builder, ri->name, bitsize, n,\n+ \"int\", \"cp_regs\");\n+\n+ dyn_feature->data.cpregs.keys[n] = ri_key;\n }\n \n-static void arm_register_sysreg_for_xml(gpointer key, gpointer value,\n- gpointer p)\n+static void arm_register_sysreg_for_feature(gpointer key, gpointer value,\n+ gpointer p)\n {\n uint32_t ri_key = (uintptr_t)key;\n ARMCPRegInfo *ri = value;\n- RegisterSysregXmlParam *param = (RegisterSysregXmlParam *)p;\n- GString *s = param->s;\n+ RegisterSysregFeatureParam *param = p;\n ARMCPU *cpu = ARM_CPU(param->cs);\n CPUARMState *env = &cpu->env;\n- DynamicGDBXMLInfo *dyn_xml = &cpu->dyn_sysreg_xml;\n+ DynamicGDBFeatureInfo *dyn_feature = &cpu->dyn_sysreg_feature;\n \n if (!(ri->type & (ARM_CP_NO_RAW | ARM_CP_NO_GDB))) {\n if (arm_feature(env, ARM_FEATURE_AARCH64)) {\n if (ri->state == ARM_CP_STATE_AA64) {\n- arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64,\n- param->n++);\n+ arm_gen_one_feature_sysreg(¶m->builder, dyn_feature,\n+ ri, ri_key, 64, param->n++);\n }\n } else {\n if (ri->state == ARM_CP_STATE_AA32) {\n@@ -269,32 +267,32 @@ static void arm_register_sysreg_for_xml(gpointer key, gpointer value,\n return;\n }\n if (ri->type & ARM_CP_64BIT) {\n- arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 64,\n- param->n++);\n+ arm_gen_one_feature_sysreg(¶m->builder, dyn_feature,\n+ ri, ri_key, 64, param->n++);\n } else {\n- arm_gen_one_xml_sysreg_tag(s , dyn_xml, ri, ri_key, 32,\n- param->n++);\n+ arm_gen_one_feature_sysreg(¶m->builder, dyn_feature,\n+ ri, ri_key, 32, param->n++);\n }\n }\n }\n }\n }\n \n-static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg)\n+static GDBFeature *arm_gen_dynamic_sysreg_feature(CPUState *cs, int base_reg)\n {\n ARMCPU *cpu = ARM_CPU(cs);\n- GString *s = g_string_new(NULL);\n- RegisterSysregXmlParam param = {cs, s, base_reg};\n-\n- cpu->dyn_sysreg_xml.num = 0;\n- cpu->dyn_sysreg_xml.data.cpregs.keys = g_new(uint32_t, g_hash_table_size(cpu->cp_regs));\n- g_string_printf(s, \"<?xml version=\\\"1.0\\\"?>\");\n- g_string_append_printf(s, \"<!DOCTYPE target SYSTEM \\\"gdb-target.dtd\\\">\");\n- g_string_append_printf(s, \"<feature name=\\\"org.qemu.gdb.arm.sys.regs\\\">\");\n- g_hash_table_foreach(cpu->cp_regs, arm_register_sysreg_for_xml, ¶m);\n- g_string_append_printf(s, \"</feature>\");\n- cpu->dyn_sysreg_xml.desc = g_string_free(s, false);\n- return cpu->dyn_sysreg_xml.num;\n+ RegisterSysregFeatureParam param = {cs};\n+ gsize num_regs = g_hash_table_size(cpu->cp_regs);\n+\n+ gdb_feature_builder_init(¶m.builder,\n+ &cpu->dyn_sysreg_feature.desc,\n+ \"org.qemu.gdb.arm.sys.regs\",\n+ \"system-registers.xml\",\n+ base_reg);\n+ cpu->dyn_sysreg_feature.data.cpregs.keys = g_new(uint32_t, num_regs);\n+ g_hash_table_foreach(cpu->cp_regs, arm_register_sysreg_for_feature, ¶m);\n+ gdb_feature_builder_end(¶m.builder);\n+ return &cpu->dyn_sysreg_feature.desc;\n }\n \n #ifdef CONFIG_TCG\n@@ -386,31 +384,29 @@ static int arm_gdb_set_m_systemreg(CPUARMState *env, uint8_t *buf, int reg)\n return 0; /* TODO */\n }\n \n-static int arm_gen_dynamic_m_systemreg_xml(CPUState *cs, int orig_base_reg)\n+static GDBFeature *arm_gen_dynamic_m_systemreg_feature(CPUState *cs,\n+ int base_reg)\n {\n ARMCPU *cpu = ARM_CPU(cs);\n CPUARMState *env = &cpu->env;\n- GString *s = g_string_new(NULL);\n- int base_reg = orig_base_reg;\n+ GDBFeatureBuilder builder;\n+ int reg = 0;\n int i;\n \n- g_string_printf(s, \"<?xml version=\\\"1.0\\\"?>\");\n- g_string_append_printf(s, \"<!DOCTYPE target SYSTEM \\\"gdb-target.dtd\\\">\");\n- g_string_append_printf(s, \"<feature name=\\\"org.gnu.gdb.arm.m-system\\\">\\n\");\n+ gdb_feature_builder_init(&builder, &cpu->dyn_m_systemreg_feature.desc,\n+ \"org.gnu.gdb.arm.m-system\", \"arm-m-system.xml\",\n+ base_reg);\n \n for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) {\n if (arm_feature(env, m_sysreg_def[i].feature)) {\n- g_string_append_printf(s,\n- \"<reg name=\\\"%s\\\" bitsize=\\\"32\\\" regnum=\\\"%d\\\"/>\\n\",\n- m_sysreg_def[i].name, base_reg++);\n+ gdb_feature_builder_append_reg(&builder, m_sysreg_def[i].name, 32,\n+ reg++, \"int\", NULL);\n }\n }\n \n- g_string_append_printf(s, \"</feature>\");\n- cpu->dyn_m_systemreg_xml.desc = g_string_free(s, false);\n- cpu->dyn_m_systemreg_xml.num = base_reg - orig_base_reg;\n+ gdb_feature_builder_end(&builder);\n \n- return cpu->dyn_m_systemreg_xml.num;\n+ return &cpu->dyn_m_systemreg_feature.desc;\n }\n \n #ifndef CONFIG_USER_ONLY\n@@ -428,31 +424,31 @@ static int arm_gdb_set_m_secextreg(CPUARMState *env, uint8_t *buf, int reg)\n return 0; /* TODO */\n }\n \n-static int arm_gen_dynamic_m_secextreg_xml(CPUState *cs, int orig_base_reg)\n+static GDBFeature *arm_gen_dynamic_m_secextreg_feature(CPUState *cs,\n+ int base_reg)\n {\n ARMCPU *cpu = ARM_CPU(cs);\n- GString *s = g_string_new(NULL);\n- int base_reg = orig_base_reg;\n+ GDBFeatureBuilder builder;\n+ char *name;\n+ int reg = 0;\n int i;\n \n- g_string_printf(s, \"<?xml version=\\\"1.0\\\"?>\");\n- g_string_append_printf(s, \"<!DOCTYPE target SYSTEM \\\"gdb-target.dtd\\\">\");\n- g_string_append_printf(s, \"<feature name=\\\"org.gnu.gdb.arm.secext\\\">\\n\");\n+ gdb_feature_builder_init(&builder, &cpu->dyn_m_secextreg_feature.desc,\n+ \"org.gnu.gdb.arm.secext\", \"arm-m-secext.xml\",\n+ base_reg);\n \n for (i = 0; i < ARRAY_SIZE(m_sysreg_def); i++) {\n- g_string_append_printf(s,\n- \"<reg name=\\\"%s_ns\\\" bitsize=\\\"32\\\" regnum=\\\"%d\\\"/>\\n\",\n- m_sysreg_def[i].name, base_reg++);\n- g_string_append_printf(s,\n- \"<reg name=\\\"%s_s\\\" bitsize=\\\"32\\\" regnum=\\\"%d\\\"/>\\n\",\n- m_sysreg_def[i].name, base_reg++);\n+ name = g_strconcat(m_sysreg_def[i].name, \"_ns\", NULL);\n+ gdb_feature_builder_append_reg(&builder, name, 32, reg++,\n+ \"int\", NULL);\n+ name = g_strconcat(m_sysreg_def[i].name, \"_s\", NULL);\n+ gdb_feature_builder_append_reg(&builder, name, 32, reg++,\n+ \"int\", NULL);\n }\n \n- g_string_append_printf(s, \"</feature>\");\n- cpu->dyn_m_secextreg_xml.desc = g_string_free(s, false);\n- cpu->dyn_m_secextreg_xml.num = base_reg - orig_base_reg;\n+ gdb_feature_builder_end(&builder);\n \n- return cpu->dyn_m_secextreg_xml.num;\n+ return &cpu->dyn_m_secextreg_feature.desc;\n }\n #endif\n #endif /* CONFIG_TCG */\n@@ -462,14 +458,14 @@ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)\n ARMCPU *cpu = ARM_CPU(cs);\n \n if (strcmp(xmlname, \"system-registers.xml\") == 0) {\n- return cpu->dyn_sysreg_xml.desc;\n+ return cpu->dyn_sysreg_feature.desc.xml;\n } else if (strcmp(xmlname, \"sve-registers.xml\") == 0) {\n- return cpu->dyn_svereg_xml.desc;\n+ return cpu->dyn_svereg_feature.desc.xml;\n } else if (strcmp(xmlname, \"arm-m-system.xml\") == 0) {\n- return cpu->dyn_m_systemreg_xml.desc;\n+ return cpu->dyn_m_systemreg_feature.desc.xml;\n #ifndef CONFIG_USER_ONLY\n } else if (strcmp(xmlname, \"arm-m-secext.xml\") == 0) {\n- return cpu->dyn_m_secextreg_xml.desc;\n+ return cpu->dyn_m_secextreg_feature.desc.xml;\n #endif\n }\n return NULL;\n@@ -487,7 +483,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)\n */\n #ifdef TARGET_AARCH64\n if (isar_feature_aa64_sve(&cpu->isar)) {\n- int nreg = arm_gen_dynamic_svereg_xml(cs, cs->gdb_num_regs);\n+ int nreg = arm_gen_dynamic_svereg_feature(cs, cs->gdb_num_regs)->num_regs;\n gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg,\n aarch64_gdb_set_sve_reg, nreg,\n \"sve-registers.xml\", 0);\n@@ -533,20 +529,20 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)\n 1, \"arm-m-profile-mve.xml\", 0);\n }\n gdb_register_coprocessor(cs, arm_gdb_get_sysreg, arm_gdb_set_sysreg,\n- arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs),\n+ arm_gen_dynamic_sysreg_feature(cs, cs->gdb_num_regs)->num_regs,\n \"system-registers.xml\", 0);\n \n #ifdef CONFIG_TCG\n if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) {\n gdb_register_coprocessor(cs,\n arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg,\n- arm_gen_dynamic_m_systemreg_xml(cs, cs->gdb_num_regs),\n+ arm_gen_dynamic_m_systemreg_feature(cs, cs->gdb_num_regs)->num_regs,\n \"arm-m-system.xml\", 0);\n #ifndef CONFIG_USER_ONLY\n if (arm_feature(env, ARM_FEATURE_M_SECURITY)) {\n gdb_register_coprocessor(cs,\n arm_gdb_get_m_secextreg, arm_gdb_set_m_secextreg,\n- arm_gen_dynamic_m_secextreg_xml(cs, cs->gdb_num_regs),\n+ arm_gen_dynamic_m_secextreg_feature(cs, cs->gdb_num_regs)->num_regs,\n \"arm-m-secext.xml\", 0);\n }\n #endif\ndiff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c\nindex d7b79a6589b..5286d5c6043 100644\n--- a/target/arm/gdbstub64.c\n+++ b/target/arm/gdbstub64.c\n@@ -247,7 +247,7 @@ int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg)\n return 0;\n }\n \n-static void output_vector_union_type(GString *s, int reg_width,\n+static void output_vector_union_type(GDBFeatureBuilder *builder, int reg_width,\n const char *name)\n {\n struct TypeSize {\n@@ -282,10 +282,10 @@ static void output_vector_union_type(GString *s, int reg_width,\n \n /* First define types and totals in a whole VL */\n for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {\n- g_string_append_printf(s,\n- \"<vector id=\\\"%s%c%c\\\" type=\\\"%s\\\" count=\\\"%d\\\"/>\",\n- name, vec_lanes[i].sz, vec_lanes[i].suffix,\n- vec_lanes[i].gdb_type, reg_width / vec_lanes[i].size);\n+ gdb_feature_builder_append_tag(\n+ builder, \"<vector id=\\\"%s%c%c\\\" type=\\\"%s\\\" count=\\\"%d\\\"/>\",\n+ name, vec_lanes[i].sz, vec_lanes[i].suffix,\n+ vec_lanes[i].gdb_type, reg_width / vec_lanes[i].size);\n }\n \n /*\n@@ -296,86 +296,77 @@ static void output_vector_union_type(GString *s, int reg_width,\n for (i = 0; i < ARRAY_SIZE(suf); i++) {\n int bits = 8 << i;\n \n- g_string_append_printf(s, \"<union id=\\\"%sn%c\\\">\", name, suf[i]);\n+ gdb_feature_builder_append_tag(builder, \"<union id=\\\"%sn%c\\\">\",\n+ name, suf[i]);\n for (j = 0; j < ARRAY_SIZE(vec_lanes); j++) {\n if (vec_lanes[j].size == bits) {\n- g_string_append_printf(s, \"<field name=\\\"%c\\\" type=\\\"%s%c%c\\\"/>\",\n- vec_lanes[j].suffix, name,\n- vec_lanes[j].sz, vec_lanes[j].suffix);\n+ gdb_feature_builder_append_tag(\n+ builder, \"<field name=\\\"%c\\\" type=\\\"%s%c%c\\\"/>\",\n+ vec_lanes[j].suffix, name,\n+ vec_lanes[j].sz, vec_lanes[j].suffix);\n }\n }\n- g_string_append(s, \"</union>\");\n+ gdb_feature_builder_append_tag(builder, \"</union>\");\n }\n \n /* And now the final union of unions */\n- g_string_append_printf(s, \"<union id=\\\"%s\\\">\", name);\n+ gdb_feature_builder_append_tag(builder, \"<union id=\\\"%s\\\">\", name);\n for (i = ARRAY_SIZE(suf) - 1; i >= 0; i--) {\n- g_string_append_printf(s, \"<field name=\\\"%c\\\" type=\\\"%sn%c\\\"/>\",\n- suf[i], name, suf[i]);\n+ gdb_feature_builder_append_tag(builder,\n+ \"<field name=\\\"%c\\\" type=\\\"%sn%c\\\"/>\",\n+ suf[i], name, suf[i]);\n }\n- g_string_append(s, \"</union>\");\n+ gdb_feature_builder_append_tag(builder, \"</union>\");\n }\n \n-int arm_gen_dynamic_svereg_xml(CPUState *cs, int orig_base_reg)\n+GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cs, int base_reg)\n {\n ARMCPU *cpu = ARM_CPU(cs);\n- GString *s = g_string_new(NULL);\n- DynamicGDBXMLInfo *info = &cpu->dyn_svereg_xml;\n int reg_width = cpu->sve_max_vq * 128;\n int pred_width = cpu->sve_max_vq * 16;\n- int base_reg = orig_base_reg;\n+ GDBFeatureBuilder builder;\n+ char *name;\n+ int reg = 0;\n int i;\n \n- g_string_printf(s, \"<?xml version=\\\"1.0\\\"?>\");\n- g_string_append_printf(s, \"<!DOCTYPE target SYSTEM \\\"gdb-target.dtd\\\">\");\n- g_string_append_printf(s, \"<feature name=\\\"org.gnu.gdb.aarch64.sve\\\">\");\n+ gdb_feature_builder_init(&builder, &cpu->dyn_svereg_feature.desc,\n+ \"org.gnu.gdb.aarch64.sve\", \"sve-registers.xml\",\n+ base_reg);\n \n /* Create the vector union type. */\n- output_vector_union_type(s, reg_width, \"svev\");\n+ output_vector_union_type(&builder, reg_width, \"svev\");\n \n /* Create the predicate vector type. */\n- g_string_append_printf(s,\n- \"<vector id=\\\"svep\\\" type=\\\"uint8\\\" count=\\\"%d\\\"/>\",\n- pred_width / 8);\n+ gdb_feature_builder_append_tag(\n+ &builder, \"<vector id=\\\"svep\\\" type=\\\"uint8\\\" count=\\\"%d\\\"/>\",\n+ pred_width / 8);\n \n /* Define the vector registers. */\n for (i = 0; i < 32; i++) {\n- g_string_append_printf(s,\n- \"<reg name=\\\"z%d\\\" bitsize=\\\"%d\\\"\"\n- \" regnum=\\\"%d\\\" type=\\\"svev\\\"/>\",\n- i, reg_width, base_reg++);\n+ name = g_strdup_printf(\"z%d\", i);\n+ gdb_feature_builder_append_reg(&builder, name, reg_width, reg++,\n+ \"svev\", NULL);\n }\n \n /* fpscr & status registers */\n- g_string_append_printf(s, \"<reg name=\\\"fpsr\\\" bitsize=\\\"32\\\"\"\n- \" regnum=\\\"%d\\\" group=\\\"float\\\"\"\n- \" type=\\\"int\\\"/>\", base_reg++);\n- g_string_append_printf(s, \"<reg name=\\\"fpcr\\\" bitsize=\\\"32\\\"\"\n- \" regnum=\\\"%d\\\" group=\\\"float\\\"\"\n- \" type=\\\"int\\\"/>\", base_reg++);\n+ gdb_feature_builder_append_reg(&builder, \"fpsr\", 32, reg++,\n+ \"int\", \"float\");\n+ gdb_feature_builder_append_reg(&builder, \"fpcr\", 32, reg++,\n+ \"int\", \"float\");\n \n /* Define the predicate registers. */\n for (i = 0; i < 16; i++) {\n- g_string_append_printf(s,\n- \"<reg name=\\\"p%d\\\" bitsize=\\\"%d\\\"\"\n- \" regnum=\\\"%d\\\" type=\\\"svep\\\"/>\",\n- i, pred_width, base_reg++);\n+ name = g_strdup_printf(\"p%d\", i);\n+ gdb_feature_builder_append_reg(&builder, name, pred_width, reg++,\n+ \"svep\", NULL);\n }\n- g_string_append_printf(s,\n- \"<reg name=\\\"ffr\\\" bitsize=\\\"%d\\\"\"\n- \" regnum=\\\"%d\\\" group=\\\"vector\\\"\"\n- \" type=\\\"svep\\\"/>\",\n- pred_width, base_reg++);\n+ gdb_feature_builder_append_reg(&builder, \"ffr\", pred_width, reg++,\n+ \"svep\", \"vector\");\n \n /* Define the vector length pseudo-register. */\n- g_string_append_printf(s,\n- \"<reg name=\\\"vg\\\" bitsize=\\\"64\\\"\"\n- \" regnum=\\\"%d\\\" type=\\\"int\\\"/>\",\n- base_reg++);\n+ gdb_feature_builder_append_reg(&builder, \"vg\", 64, reg++, \"int\", NULL);\n \n- g_string_append_printf(s, \"</feature>\");\n+ gdb_feature_builder_end(&builder);\n \n- info->desc = g_string_free(s, false);\n- info->num = base_reg - orig_base_reg;\n- return info->num;\n+ return &cpu->dyn_svereg_feature.desc;\n }\n", "prefixes": [ "v2", "26/43" ] }