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GET /api/patches/1882077/?format=api
{ "id": 1882077, "url": "http://patchwork.ozlabs.org/api/patches/1882077/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20240103173349.398526-32-alex.bennee@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20240103173349.398526-32-alex.bennee@linaro.org>", "list_archive_url": null, "date": "2024-01-03T17:33:37", "name": "[v2,31/43] gdbstub: Change gdb_get_reg_cb and gdb_set_reg_cb", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e0c68f35ff0292221988aae6b748a6b4d729ba5b", "submitter": { "id": 39532, "url": "http://patchwork.ozlabs.org/api/people/39532/?format=api", "name": "Alex Bennée", "email": "alex.bennee@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20240103173349.398526-32-alex.bennee@linaro.org/mbox/", "series": [ { "id": 388742, "url": "http://patchwork.ozlabs.org/api/series/388742/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=388742", "date": "2024-01-03T17:33:08", "name": "testing and plugin updates for 9.0 (pre-PR)", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/388742/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1882077/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1882077/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=r0onP2tc;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Iglesias\" <edgar.iglesias@gmail.com>,\n Eduardo Habkost <eduardo@habkost.net>,\n Pierrick Bouvier <pierrick.bouvier@linaro.org>, qemu-riscv@nongnu.org,\n Alistair Francis <alistair.francis@wdc.com>,\n Akihiko Odaki <akihiko.odaki@daynix.com>", "Subject": "[PATCH v2 31/43] gdbstub: Change gdb_get_reg_cb and gdb_set_reg_cb", "Date": "Wed, 3 Jan 2024 17:33:37 +0000", "Message-Id": "<20240103173349.398526-32-alex.bennee@linaro.org>", "X-Mailer": "git-send-email 2.39.2", "In-Reply-To": "<20240103173349.398526-1-alex.bennee@linaro.org>", "References": "<20240103173349.398526-1-alex.bennee@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::32b;\n envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32b.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001,\n T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Akihiko Odaki <akihiko.odaki@daynix.com>\n\nAlign the parameters of gdb_get_reg_cb and gdb_set_reg_cb with the\ngdb_read_register and gdb_write_register members of CPUClass to allow\nto unify the logic to access registers of the core and coprocessors\nin the future.\n\nSigned-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>\nReviewed-by: Alex Bennée <alex.bennee@linaro.org>\nMessage-Id: <20231213-gdb-v17-6-777047380591@daynix.com>\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\n---\n include/exec/gdbstub.h | 4 +-\n target/arm/internals.h | 12 +++---\n target/hexagon/internal.h | 4 +-\n target/microblaze/cpu.h | 4 +-\n gdbstub/gdbstub.c | 6 +--\n target/arm/gdbstub.c | 51 ++++++++++++++++--------\n target/arm/gdbstub64.c | 27 +++++++++----\n target/hexagon/gdbstub.c | 10 ++++-\n target/loongarch/gdbstub.c | 11 ++++--\n target/m68k/helper.c | 20 ++++++++--\n target/microblaze/gdbstub.c | 9 ++++-\n target/ppc/gdbstub.c | 46 +++++++++++++++++-----\n target/riscv/gdbstub.c | 46 ++++++++++++++++------\n target/s390x/gdbstub.c | 77 ++++++++++++++++++++++++++++---------\n 14 files changed, 236 insertions(+), 91 deletions(-)", "diff": "diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h\nindex ac6fce99a64..bcaab1bc750 100644\n--- a/include/exec/gdbstub.h\n+++ b/include/exec/gdbstub.h\n@@ -24,8 +24,8 @@ typedef struct GDBFeatureBuilder {\n \n \n /* Get or set a register. Returns the size of the register. */\n-typedef int (*gdb_get_reg_cb)(CPUArchState *env, GByteArray *buf, int reg);\n-typedef int (*gdb_set_reg_cb)(CPUArchState *env, uint8_t *buf, int reg);\n+typedef int (*gdb_get_reg_cb)(CPUState *cpu, GByteArray *buf, int reg);\n+typedef int (*gdb_set_reg_cb)(CPUState *cpu, uint8_t *buf, int reg);\n \n /**\n * gdb_register_coprocessor() - register a supplemental set of registers\ndiff --git a/target/arm/internals.h b/target/arm/internals.h\nindex 1136710741f..a08f461f444 100644\n--- a/target/arm/internals.h\n+++ b/target/arm/internals.h\n@@ -1447,12 +1447,12 @@ static inline uint64_t pmu_counter_mask(CPUARMState *env)\n \n #ifdef TARGET_AARCH64\n GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cpu, int base_reg);\n-int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg);\n-int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg);\n-int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg);\n-int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg);\n-int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg);\n-int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg);\n+int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *buf, int reg);\n+int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg);\n+int aarch64_gdb_get_fpu_reg(CPUState *cs, GByteArray *buf, int reg);\n+int aarch64_gdb_set_fpu_reg(CPUState *cs, uint8_t *buf, int reg);\n+int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg);\n+int aarch64_gdb_set_pauth_reg(CPUState *cs, uint8_t *buf, int reg);\n void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp);\n void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp);\n void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp);\ndiff --git a/target/hexagon/internal.h b/target/hexagon/internal.h\nindex d732b6bb3c7..beb08cb7e38 100644\n--- a/target/hexagon/internal.h\n+++ b/target/hexagon/internal.h\n@@ -33,8 +33,8 @@\n \n int hexagon_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);\n int hexagon_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);\n-int hexagon_hvx_gdb_read_register(CPUHexagonState *env, GByteArray *mem_buf, int n);\n-int hexagon_hvx_gdb_write_register(CPUHexagonState *env, uint8_t *mem_buf, int n);\n+int hexagon_hvx_gdb_read_register(CPUState *env, GByteArray *mem_buf, int n);\n+int hexagon_hvx_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n);\n \n void hexagon_debug_vreg(CPUHexagonState *env, int regnum);\n void hexagon_debug_qreg(CPUHexagonState *env, int regnum);\ndiff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h\nindex b5374365f5f..1906d8f266a 100644\n--- a/target/microblaze/cpu.h\n+++ b/target/microblaze/cpu.h\n@@ -381,8 +381,8 @@ G_NORETURN void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr,\n void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags);\n int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);\n int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);\n-int mb_cpu_gdb_read_stack_protect(CPUArchState *cpu, GByteArray *buf, int reg);\n-int mb_cpu_gdb_write_stack_protect(CPUArchState *cpu, uint8_t *buf, int reg);\n+int mb_cpu_gdb_read_stack_protect(CPUState *cs, GByteArray *buf, int reg);\n+int mb_cpu_gdb_write_stack_protect(CPUState *cs, uint8_t *buf, int reg);\n \n static inline uint32_t mb_cpu_read_msr(const CPUMBState *env)\n {\ndiff --git a/gdbstub/gdbstub.c b/gdbstub/gdbstub.c\nindex a80729436b6..21fea7fffae 100644\n--- a/gdbstub/gdbstub.c\n+++ b/gdbstub/gdbstub.c\n@@ -502,7 +502,6 @@ const GDBFeature *gdb_find_static_feature(const char *xmlname)\n static int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)\n {\n CPUClass *cc = CPU_GET_CLASS(cpu);\n- CPUArchState *env = cpu_env(cpu);\n GDBRegisterState *r;\n \n if (reg < cc->gdb_num_core_regs) {\n@@ -513,7 +512,7 @@ static int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)\n for (guint i = 0; i < cpu->gdb_regs->len; i++) {\n r = &g_array_index(cpu->gdb_regs, GDBRegisterState, i);\n if (r->base_reg <= reg && reg < r->base_reg + r->feature->num_regs) {\n- return r->get_reg(env, buf, reg - r->base_reg);\n+ return r->get_reg(cpu, buf, reg - r->base_reg);\n }\n }\n }\n@@ -523,7 +522,6 @@ static int gdb_read_register(CPUState *cpu, GByteArray *buf, int reg)\n static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg)\n {\n CPUClass *cc = CPU_GET_CLASS(cpu);\n- CPUArchState *env = cpu_env(cpu);\n GDBRegisterState *r;\n \n if (reg < cc->gdb_num_core_regs) {\n@@ -534,7 +532,7 @@ static int gdb_write_register(CPUState *cpu, uint8_t *mem_buf, int reg)\n for (guint i = 0; i < cpu->gdb_regs->len; i++) {\n r = &g_array_index(cpu->gdb_regs, GDBRegisterState, i);\n if (r->base_reg <= reg && reg < r->base_reg + r->feature->num_regs) {\n- return r->set_reg(env, mem_buf, reg - r->base_reg);\n+ return r->set_reg(cpu, mem_buf, reg - r->base_reg);\n }\n }\n }\ndiff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c\nindex f2b201d3125..059d84f98e5 100644\n--- a/target/arm/gdbstub.c\n+++ b/target/arm/gdbstub.c\n@@ -106,9 +106,10 @@ int arm_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)\n return 0;\n }\n \n-static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)\n+static int vfp_gdb_get_reg(CPUState *cs, GByteArray *buf, int reg)\n {\n- ARMCPU *cpu = env_archcpu(env);\n+ ARMCPU *cpu = ARM_CPU(cs);\n+ CPUARMState *env = &cpu->env;\n int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;\n \n /* VFP data registers are always little-endian. */\n@@ -130,9 +131,10 @@ static int vfp_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)\n return 0;\n }\n \n-static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)\n+static int vfp_gdb_set_reg(CPUState *cs, uint8_t *buf, int reg)\n {\n- ARMCPU *cpu = env_archcpu(env);\n+ ARMCPU *cpu = ARM_CPU(cs);\n+ CPUARMState *env = &cpu->env;\n int nregs = cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16;\n \n if (reg < nregs) {\n@@ -156,8 +158,11 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)\n return 0;\n }\n \n-static int vfp_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg)\n+static int vfp_gdb_get_sysreg(CPUState *cs, GByteArray *buf, int reg)\n {\n+ ARMCPU *cpu = ARM_CPU(cs);\n+ CPUARMState *env = &cpu->env;\n+\n switch (reg) {\n case 0:\n return gdb_get_reg32(buf, env->vfp.xregs[ARM_VFP_FPSID]);\n@@ -167,8 +172,11 @@ static int vfp_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg)\n return 0;\n }\n \n-static int vfp_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg)\n+static int vfp_gdb_set_sysreg(CPUState *cs, uint8_t *buf, int reg)\n {\n+ ARMCPU *cpu = ARM_CPU(cs);\n+ CPUARMState *env = &cpu->env;\n+\n switch (reg) {\n case 0:\n env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf);\n@@ -180,8 +188,11 @@ static int vfp_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg)\n return 0;\n }\n \n-static int mve_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)\n+static int mve_gdb_get_reg(CPUState *cs, GByteArray *buf, int reg)\n {\n+ ARMCPU *cpu = ARM_CPU(cs);\n+ CPUARMState *env = &cpu->env;\n+\n switch (reg) {\n case 0:\n return gdb_get_reg32(buf, env->v7m.vpr);\n@@ -190,8 +201,11 @@ static int mve_gdb_get_reg(CPUARMState *env, GByteArray *buf, int reg)\n }\n }\n \n-static int mve_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)\n+static int mve_gdb_set_reg(CPUState *cs, uint8_t *buf, int reg)\n {\n+ ARMCPU *cpu = ARM_CPU(cs);\n+ CPUARMState *env = &cpu->env;\n+\n switch (reg) {\n case 0:\n env->v7m.vpr = ldl_p(buf);\n@@ -210,9 +224,10 @@ static int mve_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)\n * We return the number of bytes copied\n */\n \n-static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg)\n+static int arm_gdb_get_sysreg(CPUState *cs, GByteArray *buf, int reg)\n {\n- ARMCPU *cpu = env_archcpu(env);\n+ ARMCPU *cpu = ARM_CPU(cs);\n+ CPUARMState *env = &cpu->env;\n const ARMCPRegInfo *ri;\n uint32_t key;\n \n@@ -228,7 +243,7 @@ static int arm_gdb_get_sysreg(CPUARMState *env, GByteArray *buf, int reg)\n return 0;\n }\n \n-static int arm_gdb_set_sysreg(CPUARMState *env, uint8_t *buf, int reg)\n+static int arm_gdb_set_sysreg(CPUState *cs, uint8_t *buf, int reg)\n {\n return 0;\n }\n@@ -367,8 +382,11 @@ static int m_sysreg_get(CPUARMState *env, GByteArray *buf,\n return gdb_get_reg32(buf, *ptr);\n }\n \n-static int arm_gdb_get_m_systemreg(CPUARMState *env, GByteArray *buf, int reg)\n+static int arm_gdb_get_m_systemreg(CPUState *cs, GByteArray *buf, int reg)\n {\n+ ARMCPU *cpu = ARM_CPU(cs);\n+ CPUARMState *env = &cpu->env;\n+\n /*\n * Here, we emulate MRS instruction, where CONTROL has a mix of\n * banked and non-banked bits.\n@@ -379,7 +397,7 @@ static int arm_gdb_get_m_systemreg(CPUARMState *env, GByteArray *buf, int reg)\n return m_sysreg_get(env, buf, reg, env->v7m.secure);\n }\n \n-static int arm_gdb_set_m_systemreg(CPUARMState *env, uint8_t *buf, int reg)\n+static int arm_gdb_set_m_systemreg(CPUState *cs, uint8_t *buf, int reg)\n {\n return 0; /* TODO */\n }\n@@ -414,12 +432,15 @@ static GDBFeature *arm_gen_dynamic_m_systemreg_feature(CPUState *cs,\n * For user-only, we see the non-secure registers via m_systemreg above.\n * For secext, encode the non-secure view as even and secure view as odd.\n */\n-static int arm_gdb_get_m_secextreg(CPUARMState *env, GByteArray *buf, int reg)\n+static int arm_gdb_get_m_secextreg(CPUState *cs, GByteArray *buf, int reg)\n {\n+ ARMCPU *cpu = ARM_CPU(cs);\n+ CPUARMState *env = &cpu->env;\n+\n return m_sysreg_get(env, buf, reg >> 1, reg & 1);\n }\n \n-static int arm_gdb_set_m_secextreg(CPUARMState *env, uint8_t *buf, int reg)\n+static int arm_gdb_set_m_secextreg(CPUState *cs, uint8_t *buf, int reg)\n {\n return 0; /* TODO */\n }\ndiff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c\nindex 5286d5c6043..caa31ff3fa1 100644\n--- a/target/arm/gdbstub64.c\n+++ b/target/arm/gdbstub64.c\n@@ -72,8 +72,11 @@ int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)\n return 0;\n }\n \n-int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg)\n+int aarch64_gdb_get_fpu_reg(CPUState *cs, GByteArray *buf, int reg)\n {\n+ ARMCPU *cpu = ARM_CPU(cs);\n+ CPUARMState *env = &cpu->env;\n+\n switch (reg) {\n case 0 ... 31:\n {\n@@ -92,8 +95,11 @@ int aarch64_gdb_get_fpu_reg(CPUARMState *env, GByteArray *buf, int reg)\n }\n }\n \n-int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg)\n+int aarch64_gdb_set_fpu_reg(CPUState *cs, uint8_t *buf, int reg)\n {\n+ ARMCPU *cpu = ARM_CPU(cs);\n+ CPUARMState *env = &cpu->env;\n+\n switch (reg) {\n case 0 ... 31:\n /* 128 bit FP register */\n@@ -116,9 +122,10 @@ int aarch64_gdb_set_fpu_reg(CPUARMState *env, uint8_t *buf, int reg)\n }\n }\n \n-int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg)\n+int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *buf, int reg)\n {\n- ARMCPU *cpu = env_archcpu(env);\n+ ARMCPU *cpu = ARM_CPU(cs);\n+ CPUARMState *env = &cpu->env;\n \n switch (reg) {\n /* The first 32 registers are the zregs */\n@@ -164,9 +171,10 @@ int aarch64_gdb_get_sve_reg(CPUARMState *env, GByteArray *buf, int reg)\n return 0;\n }\n \n-int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)\n+int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg)\n {\n- ARMCPU *cpu = env_archcpu(env);\n+ ARMCPU *cpu = ARM_CPU(cs);\n+ CPUARMState *env = &cpu->env;\n \n /* The first 32 registers are the zregs */\n switch (reg) {\n@@ -210,8 +218,11 @@ int aarch64_gdb_set_sve_reg(CPUARMState *env, uint8_t *buf, int reg)\n return 0;\n }\n \n-int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg)\n+int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg)\n {\n+ ARMCPU *cpu = ARM_CPU(cs);\n+ CPUARMState *env = &cpu->env;\n+\n switch (reg) {\n case 0: /* pauth_dmask */\n case 1: /* pauth_cmask */\n@@ -241,7 +252,7 @@ int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg)\n }\n }\n \n-int aarch64_gdb_set_pauth_reg(CPUARMState *env, uint8_t *buf, int reg)\n+int aarch64_gdb_set_pauth_reg(CPUState *cs, uint8_t *buf, int reg)\n {\n /* All pseudo registers are read-only. */\n return 0;\ndiff --git a/target/hexagon/gdbstub.c b/target/hexagon/gdbstub.c\nindex 54d37e006e0..6007e6462b9 100644\n--- a/target/hexagon/gdbstub.c\n+++ b/target/hexagon/gdbstub.c\n@@ -81,8 +81,11 @@ static int gdb_get_qreg(CPUHexagonState *env, GByteArray *mem_buf, int n)\n return total;\n }\n \n-int hexagon_hvx_gdb_read_register(CPUHexagonState *env, GByteArray *mem_buf, int n)\n+int hexagon_hvx_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)\n {\n+ HexagonCPU *cpu = HEXAGON_CPU(cs);\n+ CPUHexagonState *env = &cpu->env;\n+\n if (n < NUM_VREGS) {\n return gdb_get_vreg(env, mem_buf, n);\n }\n@@ -115,8 +118,11 @@ static int gdb_put_qreg(CPUHexagonState *env, uint8_t *mem_buf, int n)\n return MAX_VEC_SIZE_BYTES / 8;\n }\n \n-int hexagon_hvx_gdb_write_register(CPUHexagonState *env, uint8_t *mem_buf, int n)\n+int hexagon_hvx_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)\n {\n+ HexagonCPU *cpu = HEXAGON_CPU(cs);\n+ CPUHexagonState *env = &cpu->env;\n+\n if (n < NUM_VREGS) {\n return gdb_put_vreg(env, mem_buf, n);\n }\ndiff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c\nindex 843a869450e..22c6889011e 100644\n--- a/target/loongarch/gdbstub.c\n+++ b/target/loongarch/gdbstub.c\n@@ -84,9 +84,11 @@ int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)\n return length;\n }\n \n-static int loongarch_gdb_get_fpu(CPULoongArchState *env,\n- GByteArray *mem_buf, int n)\n+static int loongarch_gdb_get_fpu(CPUState *cs, GByteArray *mem_buf, int n)\n {\n+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);\n+ CPULoongArchState *env = &cpu->env;\n+\n if (0 <= n && n < 32) {\n return gdb_get_reg64(mem_buf, env->fpr[n].vreg.D(0));\n } else if (32 <= n && n < 40) {\n@@ -97,9 +99,10 @@ static int loongarch_gdb_get_fpu(CPULoongArchState *env,\n return 0;\n }\n \n-static int loongarch_gdb_set_fpu(CPULoongArchState *env,\n- uint8_t *mem_buf, int n)\n+static int loongarch_gdb_set_fpu(CPUState *cs, uint8_t *mem_buf, int n)\n {\n+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);\n+ CPULoongArchState *env = &cpu->env;\n int length = 0;\n \n if (0 <= n && n < 32) {\ndiff --git a/target/m68k/helper.c b/target/m68k/helper.c\nindex 675f2dcd5ad..a5ee4d87e32 100644\n--- a/target/m68k/helper.c\n+++ b/target/m68k/helper.c\n@@ -69,8 +69,11 @@ void m68k_cpu_list(void)\n g_slist_free(list);\n }\n \n-static int cf_fpu_gdb_get_reg(CPUM68KState *env, GByteArray *mem_buf, int n)\n+static int cf_fpu_gdb_get_reg(CPUState *cs, GByteArray *mem_buf, int n)\n {\n+ M68kCPU *cpu = M68K_CPU(cs);\n+ CPUM68KState *env = &cpu->env;\n+\n if (n < 8) {\n float_status s;\n return gdb_get_reg64(mem_buf, floatx80_to_float64(env->fregs[n].d, &s));\n@@ -86,8 +89,11 @@ static int cf_fpu_gdb_get_reg(CPUM68KState *env, GByteArray *mem_buf, int n)\n return 0;\n }\n \n-static int cf_fpu_gdb_set_reg(CPUM68KState *env, uint8_t *mem_buf, int n)\n+static int cf_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n)\n {\n+ M68kCPU *cpu = M68K_CPU(cs);\n+ CPUM68KState *env = &cpu->env;\n+\n if (n < 8) {\n float_status s;\n env->fregs[n].d = float64_to_floatx80(ldq_p(mem_buf), &s);\n@@ -106,8 +112,11 @@ static int cf_fpu_gdb_set_reg(CPUM68KState *env, uint8_t *mem_buf, int n)\n return 0;\n }\n \n-static int m68k_fpu_gdb_get_reg(CPUM68KState *env, GByteArray *mem_buf, int n)\n+static int m68k_fpu_gdb_get_reg(CPUState *cs, GByteArray *mem_buf, int n)\n {\n+ M68kCPU *cpu = M68K_CPU(cs);\n+ CPUM68KState *env = &cpu->env;\n+\n if (n < 8) {\n int len = gdb_get_reg16(mem_buf, env->fregs[n].l.upper);\n len += gdb_get_reg16(mem_buf, 0);\n@@ -125,8 +134,11 @@ static int m68k_fpu_gdb_get_reg(CPUM68KState *env, GByteArray *mem_buf, int n)\n return 0;\n }\n \n-static int m68k_fpu_gdb_set_reg(CPUM68KState *env, uint8_t *mem_buf, int n)\n+static int m68k_fpu_gdb_set_reg(CPUState *cs, uint8_t *mem_buf, int n)\n {\n+ M68kCPU *cpu = M68K_CPU(cs);\n+ CPUM68KState *env = &cpu->env;\n+\n if (n < 8) {\n env->fregs[n].l.upper = lduw_be_p(mem_buf);\n env->fregs[n].l.lower = ldq_be_p(mem_buf + 4);\ndiff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c\nindex 29ac6e9c0f7..6ffc5ad0752 100644\n--- a/target/microblaze/gdbstub.c\n+++ b/target/microblaze/gdbstub.c\n@@ -94,8 +94,10 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)\n return gdb_get_reg32(mem_buf, val);\n }\n \n-int mb_cpu_gdb_read_stack_protect(CPUMBState *env, GByteArray *mem_buf, int n)\n+int mb_cpu_gdb_read_stack_protect(CPUState *cs, GByteArray *mem_buf, int n)\n {\n+ MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);\n+ CPUMBState *env = &cpu->env;\n uint32_t val;\n \n switch (n) {\n@@ -153,8 +155,11 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)\n return 4;\n }\n \n-int mb_cpu_gdb_write_stack_protect(CPUMBState *env, uint8_t *mem_buf, int n)\n+int mb_cpu_gdb_write_stack_protect(CPUState *cs, uint8_t *mem_buf, int n)\n {\n+ MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);\n+ CPUMBState *env = &cpu->env;\n+\n switch (n) {\n case GDB_SP_SHL:\n env->slr = ldl_p(mem_buf);\ndiff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c\nindex 09b852464f3..8ca37b6bf95 100644\n--- a/target/ppc/gdbstub.c\n+++ b/target/ppc/gdbstub.c\n@@ -369,8 +369,10 @@ static int gdb_find_spr_idx(CPUPPCState *env, int n)\n return -1;\n }\n \n-static int gdb_get_spr_reg(CPUPPCState *env, GByteArray *buf, int n)\n+static int gdb_get_spr_reg(CPUState *cs, GByteArray *buf, int n)\n {\n+ PowerPCCPU *cpu = POWERPC_CPU(cs);\n+ CPUPPCState *env = &cpu->env;\n int reg;\n int len;\n \n@@ -385,8 +387,10 @@ static int gdb_get_spr_reg(CPUPPCState *env, GByteArray *buf, int n)\n return len;\n }\n \n-static int gdb_set_spr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)\n+static int gdb_set_spr_reg(CPUState *cs, uint8_t *mem_buf, int n)\n {\n+ PowerPCCPU *cpu = POWERPC_CPU(cs);\n+ CPUPPCState *env = &cpu->env;\n int reg;\n int len;\n \n@@ -403,8 +407,10 @@ static int gdb_set_spr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)\n }\n #endif\n \n-static int gdb_get_float_reg(CPUPPCState *env, GByteArray *buf, int n)\n+static int gdb_get_float_reg(CPUState *cs, GByteArray *buf, int n)\n {\n+ PowerPCCPU *cpu = POWERPC_CPU(cs);\n+ CPUPPCState *env = &cpu->env;\n uint8_t *mem_buf;\n if (n < 32) {\n gdb_get_reg64(buf, *cpu_fpr_ptr(env, n));\n@@ -421,8 +427,11 @@ static int gdb_get_float_reg(CPUPPCState *env, GByteArray *buf, int n)\n return 0;\n }\n \n-static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)\n+static int gdb_set_float_reg(CPUState *cs, uint8_t *mem_buf, int n)\n {\n+ PowerPCCPU *cpu = POWERPC_CPU(cs);\n+ CPUPPCState *env = &cpu->env;\n+\n if (n < 32) {\n ppc_maybe_bswap_register(env, mem_buf, 8);\n *cpu_fpr_ptr(env, n) = ldq_p(mem_buf);\n@@ -436,8 +445,10 @@ static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)\n return 0;\n }\n \n-static int gdb_get_avr_reg(CPUPPCState *env, GByteArray *buf, int n)\n+static int gdb_get_avr_reg(CPUState *cs, GByteArray *buf, int n)\n {\n+ PowerPCCPU *cpu = POWERPC_CPU(cs);\n+ CPUPPCState *env = &cpu->env;\n uint8_t *mem_buf;\n \n if (n < 32) {\n@@ -462,8 +473,11 @@ static int gdb_get_avr_reg(CPUPPCState *env, GByteArray *buf, int n)\n return 0;\n }\n \n-static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)\n+static int gdb_set_avr_reg(CPUState *cs, uint8_t *mem_buf, int n)\n {\n+ PowerPCCPU *cpu = POWERPC_CPU(cs);\n+ CPUPPCState *env = &cpu->env;\n+\n if (n < 32) {\n ppc_avr_t *avr = cpu_avr_ptr(env, n);\n ppc_maybe_bswap_register(env, mem_buf, 16);\n@@ -484,8 +498,11 @@ static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)\n return 0;\n }\n \n-static int gdb_get_spe_reg(CPUPPCState *env, GByteArray *buf, int n)\n+static int gdb_get_spe_reg(CPUState *cs, GByteArray *buf, int n)\n {\n+ PowerPCCPU *cpu = POWERPC_CPU(cs);\n+ CPUPPCState *env = &cpu->env;\n+\n if (n < 32) {\n #if defined(TARGET_PPC64)\n gdb_get_reg32(buf, env->gpr[n] >> 32);\n@@ -508,8 +525,11 @@ static int gdb_get_spe_reg(CPUPPCState *env, GByteArray *buf, int n)\n return 0;\n }\n \n-static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)\n+static int gdb_set_spe_reg(CPUState *cs, uint8_t *mem_buf, int n)\n {\n+ PowerPCCPU *cpu = POWERPC_CPU(cs);\n+ CPUPPCState *env = &cpu->env;\n+\n if (n < 32) {\n #if defined(TARGET_PPC64)\n target_ulong lo = (uint32_t)env->gpr[n];\n@@ -537,8 +557,11 @@ static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)\n return 0;\n }\n \n-static int gdb_get_vsx_reg(CPUPPCState *env, GByteArray *buf, int n)\n+static int gdb_get_vsx_reg(CPUState *cs, GByteArray *buf, int n)\n {\n+ PowerPCCPU *cpu = POWERPC_CPU(cs);\n+ CPUPPCState *env = &cpu->env;\n+\n if (n < 32) {\n gdb_get_reg64(buf, *cpu_vsrl_ptr(env, n));\n ppc_maybe_bswap_register(env, gdb_get_reg_ptr(buf, 8), 8);\n@@ -547,8 +570,11 @@ static int gdb_get_vsx_reg(CPUPPCState *env, GByteArray *buf, int n)\n return 0;\n }\n \n-static int gdb_set_vsx_reg(CPUPPCState *env, uint8_t *mem_buf, int n)\n+static int gdb_set_vsx_reg(CPUState *cs, uint8_t *mem_buf, int n)\n {\n+ PowerPCCPU *cpu = POWERPC_CPU(cs);\n+ CPUPPCState *env = &cpu->env;\n+\n if (n < 32) {\n ppc_maybe_bswap_register(env, mem_buf, 8);\n *cpu_vsrl_ptr(env, n) = ldq_p(mem_buf);\ndiff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c\nindex a879869fa1a..68d0fdc1fd6 100644\n--- a/target/riscv/gdbstub.c\n+++ b/target/riscv/gdbstub.c\n@@ -108,8 +108,11 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)\n return length;\n }\n \n-static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)\n+static int riscv_gdb_get_fpu(CPUState *cs, GByteArray *buf, int n)\n {\n+ RISCVCPU *cpu = RISCV_CPU(cs);\n+ CPURISCVState *env = &cpu->env;\n+\n if (n < 32) {\n if (env->misa_ext & RVD) {\n return gdb_get_reg64(buf, env->fpr[n]);\n@@ -121,8 +124,11 @@ static int riscv_gdb_get_fpu(CPURISCVState *env, GByteArray *buf, int n)\n return 0;\n }\n \n-static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)\n+static int riscv_gdb_set_fpu(CPUState *cs, uint8_t *mem_buf, int n)\n {\n+ RISCVCPU *cpu = RISCV_CPU(cs);\n+ CPURISCVState *env = &cpu->env;\n+\n if (n < 32) {\n env->fpr[n] = ldq_p(mem_buf); /* always 64-bit */\n return sizeof(uint64_t);\n@@ -130,8 +136,10 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)\n return 0;\n }\n \n-static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)\n+static int riscv_gdb_get_vector(CPUState *cs, GByteArray *buf, int n)\n {\n+ RISCVCPU *cpu = RISCV_CPU(cs);\n+ CPURISCVState *env = &cpu->env;\n uint16_t vlenb = riscv_cpu_cfg(env)->vlen >> 3;\n if (n < 32) {\n int i;\n@@ -146,8 +154,10 @@ static int riscv_gdb_get_vector(CPURISCVState *env, GByteArray *buf, int n)\n return 0;\n }\n \n-static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n)\n+static int riscv_gdb_set_vector(CPUState *cs, uint8_t *mem_buf, int n)\n {\n+ RISCVCPU *cpu = RISCV_CPU(cs);\n+ CPURISCVState *env = &cpu->env;\n uint16_t vlenb = riscv_cpu_cfg(env)->vlen >> 3;\n if (n < 32) {\n int i;\n@@ -160,8 +170,11 @@ static int riscv_gdb_set_vector(CPURISCVState *env, uint8_t *mem_buf, int n)\n return 0;\n }\n \n-static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n)\n+static int riscv_gdb_get_csr(CPUState *cs, GByteArray *buf, int n)\n {\n+ RISCVCPU *cpu = RISCV_CPU(cs);\n+ CPURISCVState *env = &cpu->env;\n+\n if (n < CSR_TABLE_SIZE) {\n target_ulong val = 0;\n int result;\n@@ -174,8 +187,11 @@ static int riscv_gdb_get_csr(CPURISCVState *env, GByteArray *buf, int n)\n return 0;\n }\n \n-static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n)\n+static int riscv_gdb_set_csr(CPUState *cs, uint8_t *mem_buf, int n)\n {\n+ RISCVCPU *cpu = RISCV_CPU(cs);\n+ CPURISCVState *env = &cpu->env;\n+\n if (n < CSR_TABLE_SIZE) {\n target_ulong val = ldtul_p(mem_buf);\n int result;\n@@ -188,25 +204,31 @@ static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n)\n return 0;\n }\n \n-static int riscv_gdb_get_virtual(CPURISCVState *cs, GByteArray *buf, int n)\n+static int riscv_gdb_get_virtual(CPUState *cs, GByteArray *buf, int n)\n {\n if (n == 0) {\n #ifdef CONFIG_USER_ONLY\n return gdb_get_regl(buf, 0);\n #else\n- return gdb_get_regl(buf, cs->priv);\n+ RISCVCPU *cpu = RISCV_CPU(cs);\n+ CPURISCVState *env = &cpu->env;\n+\n+ return gdb_get_regl(buf, env->priv);\n #endif\n }\n return 0;\n }\n \n-static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n)\n+static int riscv_gdb_set_virtual(CPUState *cs, uint8_t *mem_buf, int n)\n {\n if (n == 0) {\n #ifndef CONFIG_USER_ONLY\n- cs->priv = ldtul_p(mem_buf) & 0x3;\n- if (cs->priv == PRV_RESERVED) {\n- cs->priv = PRV_S;\n+ RISCVCPU *cpu = RISCV_CPU(cs);\n+ CPURISCVState *env = &cpu->env;\n+\n+ env->priv = ldtul_p(mem_buf) & 0x3;\n+ if (env->priv == PRV_RESERVED) {\n+ env->priv = PRV_S;\n }\n #endif\n return sizeof(target_ulong);\ndiff --git a/target/s390x/gdbstub.c b/target/s390x/gdbstub.c\nindex 02c388dc323..c1e7c59b822 100644\n--- a/target/s390x/gdbstub.c\n+++ b/target/s390x/gdbstub.c\n@@ -70,8 +70,11 @@ int s390_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)\n #define S390_A0_REGNUM 0\n #define S390_A15_REGNUM 15\n \n-static int cpu_read_ac_reg(CPUS390XState *env, GByteArray *buf, int n)\n+static int cpu_read_ac_reg(CPUState *cs, GByteArray *buf, int n)\n {\n+ S390CPU *cpu = S390_CPU(cs);\n+ CPUS390XState *env = &cpu->env;\n+\n switch (n) {\n case S390_A0_REGNUM ... S390_A15_REGNUM:\n return gdb_get_reg32(buf, env->aregs[n]);\n@@ -80,8 +83,11 @@ static int cpu_read_ac_reg(CPUS390XState *env, GByteArray *buf, int n)\n }\n }\n \n-static int cpu_write_ac_reg(CPUS390XState *env, uint8_t *mem_buf, int n)\n+static int cpu_write_ac_reg(CPUState *cs, uint8_t *mem_buf, int n)\n {\n+ S390CPU *cpu = S390_CPU(cs);\n+ CPUS390XState *env = &cpu->env;\n+\n switch (n) {\n case S390_A0_REGNUM ... S390_A15_REGNUM:\n env->aregs[n] = ldl_p(mem_buf);\n@@ -97,8 +103,11 @@ static int cpu_write_ac_reg(CPUS390XState *env, uint8_t *mem_buf, int n)\n #define S390_F0_REGNUM 1\n #define S390_F15_REGNUM 16\n \n-static int cpu_read_fp_reg(CPUS390XState *env, GByteArray *buf, int n)\n+static int cpu_read_fp_reg(CPUState *cs, GByteArray *buf, int n)\n {\n+ S390CPU *cpu = S390_CPU(cs);\n+ CPUS390XState *env = &cpu->env;\n+\n switch (n) {\n case S390_FPC_REGNUM:\n return gdb_get_reg32(buf, env->fpc);\n@@ -109,8 +118,11 @@ static int cpu_read_fp_reg(CPUS390XState *env, GByteArray *buf, int n)\n }\n }\n \n-static int cpu_write_fp_reg(CPUS390XState *env, uint8_t *mem_buf, int n)\n+static int cpu_write_fp_reg(CPUState *cs, uint8_t *mem_buf, int n)\n {\n+ S390CPU *cpu = S390_CPU(cs);\n+ CPUS390XState *env = &cpu->env;\n+\n switch (n) {\n case S390_FPC_REGNUM:\n env->fpc = ldl_p(mem_buf);\n@@ -129,8 +141,10 @@ static int cpu_write_fp_reg(CPUS390XState *env, uint8_t *mem_buf, int n)\n #define S390_V16_REGNUM 16\n #define S390_V31_REGNUM 31\n \n-static int cpu_read_vreg(CPUS390XState *env, GByteArray *buf, int n)\n+static int cpu_read_vreg(CPUState *cs, GByteArray *buf, int n)\n {\n+ S390CPU *cpu = S390_CPU(cs);\n+ CPUS390XState *env = &cpu->env;\n int ret;\n \n switch (n) {\n@@ -148,8 +162,11 @@ static int cpu_read_vreg(CPUS390XState *env, GByteArray *buf, int n)\n return ret;\n }\n \n-static int cpu_write_vreg(CPUS390XState *env, uint8_t *mem_buf, int n)\n+static int cpu_write_vreg(CPUState *cs, uint8_t *mem_buf, int n)\n {\n+ S390CPU *cpu = S390_CPU(cs);\n+ CPUS390XState *env = &cpu->env;\n+\n switch (n) {\n case S390_V0L_REGNUM ... S390_V15L_REGNUM:\n env->vregs[n][1] = ldtul_p(mem_buf + 8);\n@@ -168,8 +185,11 @@ static int cpu_write_vreg(CPUS390XState *env, uint8_t *mem_buf, int n)\n #define S390_C15_REGNUM 15\n \n #ifndef CONFIG_USER_ONLY\n-static int cpu_read_c_reg(CPUS390XState *env, GByteArray *buf, int n)\n+static int cpu_read_c_reg(CPUState *cs, GByteArray *buf, int n)\n {\n+ S390CPU *cpu = S390_CPU(cs);\n+ CPUS390XState *env = &cpu->env;\n+\n switch (n) {\n case S390_C0_REGNUM ... S390_C15_REGNUM:\n return gdb_get_regl(buf, env->cregs[n]);\n@@ -178,8 +198,11 @@ static int cpu_read_c_reg(CPUS390XState *env, GByteArray *buf, int n)\n }\n }\n \n-static int cpu_write_c_reg(CPUS390XState *env, uint8_t *mem_buf, int n)\n+static int cpu_write_c_reg(CPUState *cs, uint8_t *mem_buf, int n)\n {\n+ S390CPU *cpu = S390_CPU(cs);\n+ CPUS390XState *env = &cpu->env;\n+\n switch (n) {\n case S390_C0_REGNUM ... S390_C15_REGNUM:\n env->cregs[n] = ldtul_p(mem_buf);\n@@ -199,8 +222,11 @@ static int cpu_write_c_reg(CPUS390XState *env, uint8_t *mem_buf, int n)\n #define S390_VIRT_BEA_REGNUM 2\n #define S390_VIRT_PREFIX_REGNUM 3\n \n-static int cpu_read_virt_reg(CPUS390XState *env, GByteArray *mem_buf, int n)\n+static int cpu_read_virt_reg(CPUState *cs, GByteArray *mem_buf, int n)\n {\n+ S390CPU *cpu = S390_CPU(cs);\n+ CPUS390XState *env = &cpu->env;\n+\n switch (n) {\n case S390_VIRT_CKC_REGNUM:\n return gdb_get_regl(mem_buf, env->ckc);\n@@ -215,24 +241,27 @@ static int cpu_read_virt_reg(CPUS390XState *env, GByteArray *mem_buf, int n)\n }\n }\n \n-static int cpu_write_virt_reg(CPUS390XState *env, uint8_t *mem_buf, int n)\n+static int cpu_write_virt_reg(CPUState *cs, uint8_t *mem_buf, int n)\n {\n+ S390CPU *cpu = S390_CPU(cs);\n+ CPUS390XState *env = &cpu->env;\n+\n switch (n) {\n case S390_VIRT_CKC_REGNUM:\n env->ckc = ldtul_p(mem_buf);\n- cpu_synchronize_post_init(env_cpu(env));\n+ cpu_synchronize_post_init(cs);\n return 8;\n case S390_VIRT_CPUTM_REGNUM:\n env->cputm = ldtul_p(mem_buf);\n- cpu_synchronize_post_init(env_cpu(env));\n+ cpu_synchronize_post_init(cs);\n return 8;\n case S390_VIRT_BEA_REGNUM:\n env->gbea = ldtul_p(mem_buf);\n- cpu_synchronize_post_init(env_cpu(env));\n+ cpu_synchronize_post_init(cs);\n return 8;\n case S390_VIRT_PREFIX_REGNUM:\n env->psa = ldtul_p(mem_buf);\n- cpu_synchronize_post_init(env_cpu(env));\n+ cpu_synchronize_post_init(cs);\n return 8;\n default:\n return 0;\n@@ -245,8 +274,11 @@ static int cpu_write_virt_reg(CPUS390XState *env, uint8_t *mem_buf, int n)\n #define S390_VIRT_KVM_PFS_REGNUM 2\n #define S390_VIRT_KVM_PFC_REGNUM 3\n \n-static int cpu_read_virt_kvm_reg(CPUS390XState *env, GByteArray *mem_buf, int n)\n+static int cpu_read_virt_kvm_reg(CPUState *cs, GByteArray *mem_buf, int n)\n {\n+ S390CPU *cpu = S390_CPU(cs);\n+ CPUS390XState *env = &cpu->env;\n+\n switch (n) {\n case S390_VIRT_KVM_PP_REGNUM:\n return gdb_get_regl(mem_buf, env->pp);\n@@ -261,8 +293,11 @@ static int cpu_read_virt_kvm_reg(CPUS390XState *env, GByteArray *mem_buf, int n)\n }\n }\n \n-static int cpu_write_virt_kvm_reg(CPUS390XState *env, uint8_t *mem_buf, int n)\n+static int cpu_write_virt_kvm_reg(CPUState *cs, uint8_t *mem_buf, int n)\n {\n+ S390CPU *cpu = S390_CPU(cs);\n+ CPUS390XState *env = &cpu->env;\n+\n switch (n) {\n case S390_VIRT_KVM_PP_REGNUM:\n env->pp = ldtul_p(mem_buf);\n@@ -292,13 +327,19 @@ static int cpu_write_virt_kvm_reg(CPUS390XState *env, uint8_t *mem_buf, int n)\n #define S390_GS_GSSM_REGNUM 2\n #define S390_GS_GSEPLA_REGNUM 3\n \n-static int cpu_read_gs_reg(CPUS390XState *env, GByteArray *buf, int n)\n+static int cpu_read_gs_reg(CPUState *cs, GByteArray *buf, int n)\n {\n+ S390CPU *cpu = S390_CPU(cs);\n+ CPUS390XState *env = &cpu->env;\n+\n return gdb_get_regl(buf, env->gscb[n]);\n }\n \n-static int cpu_write_gs_reg(CPUS390XState *env, uint8_t *mem_buf, int n)\n+static int cpu_write_gs_reg(CPUState *cs, uint8_t *mem_buf, int n)\n {\n+ S390CPU *cpu = S390_CPU(cs);\n+ CPUS390XState *env = &cpu->env;\n+\n env->gscb[n] = ldtul_p(mem_buf);\n cpu_synchronize_post_init(env_cpu(env));\n return 8;\n", "prefixes": [ "v2", "31/43" ] }