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GET /api/patches/1882067/?format=api
{ "id": 1882067, "url": "http://patchwork.ozlabs.org/api/patches/1882067/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20240103173349.398526-29-alex.bennee@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20240103173349.398526-29-alex.bennee@linaro.org>", "list_archive_url": null, "date": "2024-01-03T17:33:34", "name": "[v2,28/43] target/riscv: Use GDBFeature for dynamic XML", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "be82bb7ae681a02f02d04024e40271e92040dc12", "submitter": { "id": 39532, "url": "http://patchwork.ozlabs.org/api/people/39532/?format=api", "name": "Alex Bennée", "email": "alex.bennee@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20240103173349.398526-29-alex.bennee@linaro.org/mbox/", "series": [ { "id": 388742, "url": "http://patchwork.ozlabs.org/api/series/388742/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=388742", "date": "2024-01-03T17:33:08", "name": "testing and plugin updates for 9.0 (pre-PR)", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/388742/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1882067/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1882067/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=MFFXzJIf;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Iglesias\" <edgar.iglesias@gmail.com>,\n Eduardo Habkost <eduardo@habkost.net>,\n Pierrick Bouvier <pierrick.bouvier@linaro.org>, qemu-riscv@nongnu.org,\n Alistair Francis <alistair.francis@wdc.com>,\n Akihiko Odaki <akihiko.odaki@daynix.com>", "Subject": "[PATCH v2 28/43] target/riscv: Use GDBFeature for dynamic XML", "Date": "Wed, 3 Jan 2024 17:33:34 +0000", "Message-Id": "<20240103173349.398526-29-alex.bennee@linaro.org>", "X-Mailer": "git-send-email 2.39.2", "In-Reply-To": "<20240103173349.398526-1-alex.bennee@linaro.org>", "References": "<20240103173349.398526-1-alex.bennee@linaro.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::333;\n envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x333.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001,\n T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Akihiko Odaki <akihiko.odaki@daynix.com>\n\nIn preparation for a change to use GDBFeature as a parameter of\ngdb_register_coprocessor(), convert the internal representation of\ndynamic feature from plain XML to GDBFeature.\n\nSigned-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>\nMessage-Id: <20231213-gdb-v17-3-777047380591@daynix.com>\nSigned-off-by: Alex Bennée <alex.bennee@linaro.org>\n---\n target/riscv/cpu.h | 5 +--\n target/riscv/cpu.c | 4 +--\n target/riscv/gdbstub.c | 79 +++++++++++++++++++-----------------------\n 3 files changed, 40 insertions(+), 48 deletions(-)", "diff": "diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h\nindex 060b7f69a74..ad7236d7547 100644\n--- a/target/riscv/cpu.h\n+++ b/target/riscv/cpu.h\n@@ -24,6 +24,7 @@\n #include \"hw/registerfields.h\"\n #include \"hw/qdev-properties.h\"\n #include \"exec/cpu-defs.h\"\n+#include \"exec/gdbstub.h\"\n #include \"qemu/cpu-float.h\"\n #include \"qom/object.h\"\n #include \"qemu/int128.h\"\n@@ -424,8 +425,8 @@ struct ArchCPU {\n \n CPURISCVState env;\n \n- char *dyn_csr_xml;\n- char *dyn_vreg_xml;\n+ GDBFeature dyn_csr_feature;\n+ GDBFeature dyn_vreg_feature;\n \n /* Configuration Settings */\n RISCVCPUConfig cfg;\ndiff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex b799f133604..673e937a5d8 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -1534,9 +1534,9 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)\n RISCVCPU *cpu = RISCV_CPU(cs);\n \n if (strcmp(xmlname, \"riscv-csr.xml\") == 0) {\n- return cpu->dyn_csr_xml;\n+ return cpu->dyn_csr_feature.xml;\n } else if (strcmp(xmlname, \"riscv-vector.xml\") == 0) {\n- return cpu->dyn_vreg_xml;\n+ return cpu->dyn_vreg_feature.xml;\n }\n \n return NULL;\ndiff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c\nindex 365040228a1..76b72a95954 100644\n--- a/target/riscv/gdbstub.c\n+++ b/target/riscv/gdbstub.c\n@@ -214,13 +214,14 @@ static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n)\n return 0;\n }\n \n-static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)\n+static GDBFeature *riscv_gen_dynamic_csr_feature(CPUState *cs, int base_reg)\n {\n RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);\n RISCVCPU *cpu = RISCV_CPU(cs);\n CPURISCVState *env = &cpu->env;\n- GString *s = g_string_new(NULL);\n+ GDBFeatureBuilder builder;\n riscv_csr_predicate_fn predicate;\n+ const char *name;\n int bitsize = 16 << mcc->misa_mxl_max;\n int i;\n \n@@ -233,9 +234,9 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)\n bitsize = 64;\n }\n \n- g_string_printf(s, \"<?xml version=\\\"1.0\\\"?>\");\n- g_string_append_printf(s, \"<!DOCTYPE feature SYSTEM \\\"gdb-target.dtd\\\">\");\n- g_string_append_printf(s, \"<feature name=\\\"org.gnu.gdb.riscv.csr\\\">\");\n+ gdb_feature_builder_init(&builder, &cpu->dyn_csr_feature,\n+ \"org.gnu.gdb.riscv.csr\", \"riscv-csr.xml\",\n+ base_reg);\n \n for (i = 0; i < CSR_TABLE_SIZE; i++) {\n if (env->priv_ver < csr_ops[i].min_priv_ver) {\n@@ -243,72 +244,64 @@ static int riscv_gen_dynamic_csr_xml(CPUState *cs, int base_reg)\n }\n predicate = csr_ops[i].predicate;\n if (predicate && (predicate(env, i) == RISCV_EXCP_NONE)) {\n- if (csr_ops[i].name) {\n- g_string_append_printf(s, \"<reg name=\\\"%s\\\"\", csr_ops[i].name);\n- } else {\n- g_string_append_printf(s, \"<reg name=\\\"csr%03x\\\"\", i);\n+ g_autofree char *dynamic_name = NULL;\n+ name = csr_ops[i].name;\n+ if (!name) {\n+ dynamic_name = g_strdup_printf(\"csr%03x\", i);\n+ name = dynamic_name;\n }\n- g_string_append_printf(s, \" bitsize=\\\"%d\\\"\", bitsize);\n- g_string_append_printf(s, \" regnum=\\\"%d\\\"/>\", base_reg + i);\n+\n+ gdb_feature_builder_append_reg(&builder, name, bitsize, i,\n+ \"int\", NULL);\n }\n }\n \n- g_string_append_printf(s, \"</feature>\");\n-\n- cpu->dyn_csr_xml = g_string_free(s, false);\n+ gdb_feature_builder_end(&builder);\n \n #if !defined(CONFIG_USER_ONLY)\n env->debugger = false;\n #endif\n \n- return CSR_TABLE_SIZE;\n+ return &cpu->dyn_csr_feature;\n }\n \n-static int ricsv_gen_dynamic_vector_xml(CPUState *cs, int base_reg)\n+static GDBFeature *ricsv_gen_dynamic_vector_feature(CPUState *cs, int base_reg)\n {\n RISCVCPU *cpu = RISCV_CPU(cs);\n- GString *s = g_string_new(NULL);\n- g_autoptr(GString) ts = g_string_new(\"\");\n+ GDBFeatureBuilder builder;\n int reg_width = cpu->cfg.vlen;\n- int num_regs = 0;\n int i;\n \n- g_string_printf(s, \"<?xml version=\\\"1.0\\\"?>\");\n- g_string_append_printf(s, \"<!DOCTYPE target SYSTEM \\\"gdb-target.dtd\\\">\");\n- g_string_append_printf(s, \"<feature name=\\\"org.gnu.gdb.riscv.vector\\\">\");\n+ gdb_feature_builder_init(&builder, &cpu->dyn_vreg_feature,\n+ \"org.gnu.gdb.riscv.vector\", \"riscv-vector.xml\",\n+ base_reg);\n \n /* First define types and totals in a whole VL */\n for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {\n int count = reg_width / vec_lanes[i].size;\n- g_string_printf(ts, \"%s\", vec_lanes[i].id);\n- g_string_append_printf(s,\n- \"<vector id=\\\"%s\\\" type=\\\"%s\\\" count=\\\"%d\\\"/>\",\n- ts->str, vec_lanes[i].gdb_type, count);\n+ gdb_feature_builder_append_tag(\n+ &builder, \"<vector id=\\\"%s\\\" type=\\\"%s\\\" count=\\\"%d\\\"/>\",\n+ vec_lanes[i].id, vec_lanes[i].gdb_type, count);\n }\n \n /* Define unions */\n- g_string_append_printf(s, \"<union id=\\\"riscv_vector\\\">\");\n+ gdb_feature_builder_append_tag(&builder, \"<union id=\\\"riscv_vector\\\">\");\n for (i = 0; i < ARRAY_SIZE(vec_lanes); i++) {\n- g_string_append_printf(s, \"<field name=\\\"%c\\\" type=\\\"%s\\\"/>\",\n- vec_lanes[i].suffix,\n- vec_lanes[i].id);\n+ gdb_feature_builder_append_tag(&builder,\n+ \"<field name=\\\"%c\\\" type=\\\"%s\\\"/>\",\n+ vec_lanes[i].suffix, vec_lanes[i].id);\n }\n- g_string_append(s, \"</union>\");\n+ gdb_feature_builder_append_tag(&builder, \"</union>\");\n \n /* Define vector registers */\n for (i = 0; i < 32; i++) {\n- g_string_append_printf(s,\n- \"<reg name=\\\"v%d\\\" bitsize=\\\"%d\\\"\"\n- \" regnum=\\\"%d\\\" group=\\\"vector\\\"\"\n- \" type=\\\"riscv_vector\\\"/>\",\n- i, reg_width, base_reg++);\n- num_regs++;\n+ gdb_feature_builder_append_reg(&builder, g_strdup_printf(\"v%d\", i),\n+ reg_width, i, \"riscv_vector\", \"vector\");\n }\n \n- g_string_append_printf(s, \"</feature>\");\n+ gdb_feature_builder_end(&builder);\n \n- cpu->dyn_vreg_xml = g_string_free(s, false);\n- return num_regs;\n+ return &cpu->dyn_vreg_feature;\n }\n \n void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)\n@@ -324,10 +317,9 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)\n 32, \"riscv-32bit-fpu.xml\", 0);\n }\n if (env->misa_ext & RVV) {\n- int base_reg = cs->gdb_num_regs;\n gdb_register_coprocessor(cs, riscv_gdb_get_vector,\n riscv_gdb_set_vector,\n- ricsv_gen_dynamic_vector_xml(cs, base_reg),\n+ ricsv_gen_dynamic_vector_feature(cs, cs->gdb_num_regs)->num_regs,\n \"riscv-vector.xml\", 0);\n }\n switch (mcc->misa_mxl_max) {\n@@ -347,9 +339,8 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs)\n }\n \n if (cpu->cfg.ext_zicsr) {\n- int base_reg = cs->gdb_num_regs;\n gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr,\n- riscv_gen_dynamic_csr_xml(cs, base_reg),\n+ riscv_gen_dynamic_csr_feature(cs, cs->gdb_num_regs)->num_regs,\n \"riscv-csr.xml\", 0);\n }\n }\n", "prefixes": [ "v2", "28/43" ] }