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GET /api/patches/1839984/?format=api
{ "id": 1839984, "url": "http://patchwork.ozlabs.org/api/patches/1839984/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/patch-17722-tamar@arm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<patch-17722-tamar@arm.com>", "list_archive_url": null, "date": "2023-09-27T00:52:29", "name": "AArch64 Add special patterns for creating DI scalar and vector constant 1 << 63 [PR109154]", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "255e766c653d266d5dc7bafa13c740c1047f4c80", "submitter": { "id": 69689, "url": "http://patchwork.ozlabs.org/api/people/69689/?format=api", "name": "Tamar Christina", "email": "Tamar.Christina@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/patch-17722-tamar@arm.com/mbox/", "series": [ { "id": 375022, "url": "http://patchwork.ozlabs.org/api/series/375022/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=375022", "date": "2023-09-27T00:52:29", "name": "AArch64 Add special patterns for creating DI scalar and vector constant 1 << 63 [PR109154]", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/375022/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1839984/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1839984/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=armh.onmicrosoft.com header.i=@armh.onmicrosoft.com\n header.a=rsa-sha256 header.s=selector2-armh-onmicrosoft-com\n header.b=OhHeiKCV;\n\tdkim=pass (1024-bit key) header.d=armh.onmicrosoft.com\n header.i=@armh.onmicrosoft.com header.a=rsa-sha256\n header.s=selector2-armh-onmicrosoft-com header.b=OhHeiKCV;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:3:1:0:246e:9693:128c; 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Ip=[63.35.35.123];\n Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n AM7EUR03FT013.eop-EUR03.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-Spam-Status": "No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED,\n DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_LOTSOFHASH,\n KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE,\n TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6", "X-Spam-Checker-Version": "SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "Hi All,\n\nThis adds a way to generate special sequences for creation of constants for\nwhich we don't have single instructions sequences which would have normally\nlead to a GP -> FP transfer or a literal load.\n\nThe patch starts out by adding support for creating 1 << 63 using fneg (mov 0).\n\nBootstrapped Regtested on aarch64-none-linux-gnu and no issues.\n\nOk for master?\n\nThanks,\nTamar\n\ngcc/ChangeLog:\n\n\tPR tree-optimization/109154\n\t* config/aarch64/aarch64-protos.h (aarch64_simd_special_constant_p):\n\tNew.\n\t* config/aarch64/aarch64-simd.md (*aarch64_simd_mov<VQMOV:mode>): Add\n\tnew coden for special constants.\n\t* config/aarch64/aarch64.cc (aarch64_extract_vec_duplicate_wide_int):\n\tTake optional mode.\n\t(aarch64_simd_special_constant_p): New.\n\t* config/aarch64/aarch64.md (*movdi_aarch64): Add new codegen for\n\tspecial constants.\n\t* config/aarch64/constraints.md (Dx): new.\n\ngcc/testsuite/ChangeLog:\n\n\tPR tree-optimization/109154\n\t* gcc.target/aarch64/fneg-abs_1.c: Updated.\n\t* gcc.target/aarch64/fneg-abs_2.c: Updated.\n\t* gcc.target/aarch64/fneg-abs_4.c: Updated.\n\n--- inline copy of patch -- \ndiff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h\nindex 70303d6fd953e0c397b9138ede8858c2db2e53db..2af9f6a774c20268bf90756c17064bbff8f8ff87 100644\n\n\n\n\n--\ndiff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h\nindex 70303d6fd953e0c397b9138ede8858c2db2e53db..2af9f6a774c20268bf90756c17064bbff8f8ff87 100644\n--- a/gcc/config/aarch64/aarch64-protos.h\n+++ b/gcc/config/aarch64/aarch64-protos.h\n@@ -827,6 +827,7 @@ bool aarch64_sve_ptrue_svpattern_p (rtx, struct simd_immediate_info *);\n bool aarch64_simd_valid_immediate (rtx, struct simd_immediate_info *,\n \t\t\tenum simd_immediate_check w = AARCH64_CHECK_MOV);\n rtx aarch64_check_zero_based_sve_index_immediate (rtx);\n+bool aarch64_simd_special_constant_p (rtx, rtx, machine_mode);\n bool aarch64_sve_index_immediate_p (rtx);\n bool aarch64_sve_arith_immediate_p (machine_mode, rtx, bool);\n bool aarch64_sve_sqadd_sqsub_immediate_p (machine_mode, rtx, bool);\ndiff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md\nindex 7b4d5a37a9795fefda785aaacc246918826ed0a2..63c802d942a186b5a94c66d2e83828a82a88ffa8 100644\n--- a/gcc/config/aarch64/aarch64-simd.md\n+++ b/gcc/config/aarch64/aarch64-simd.md\n@@ -181,17 +181,28 @@ (define_insn_and_split \"*aarch64_simd_mov<VQMOV:mode>\"\n [?r , r ; multiple , * , 8] #\n [w , Dn; neon_move<q> , simd, 4] << aarch64_output_simd_mov_immediate (operands[1], 128);\n [w , Dz; fmov , * , 4] fmov\\t%d0, xzr\n+ [w , Dx; neon_move , simd, 8] #\n }\n \"&& reload_completed\n- && !(FP_REGNUM_P (REGNO (operands[0]))\n-\t&& FP_REGNUM_P (REGNO (operands[1])))\"\n+ && (!(FP_REGNUM_P (REGNO (operands[0]))\n+\t && FP_REGNUM_P (REGNO (operands[1])))\n+ || (aarch64_simd_special_constant_p (operands[1], NULL_RTX, <MODE>mode)\n+\t && FP_REGNUM_P (REGNO (operands[0]))))\"\n [(const_int 0)]\n {\n if (GP_REGNUM_P (REGNO (operands[0]))\n \t&& GP_REGNUM_P (REGNO (operands[1])))\n aarch64_simd_emit_reg_reg_move (operands, DImode, 2);\n else\n- aarch64_split_simd_move (operands[0], operands[1]);\n+ {\n+\tif (FP_REGNUM_P (REGNO (operands[0]))\n+\t && <MODE>mode == V2DImode\n+\t && aarch64_simd_special_constant_p (operands[1], operands[0],\n+\t\t\t\t\t\t<MODE>mode))\n+\t ;\n+\telse\n+\t aarch64_split_simd_move (operands[0], operands[1]);\n+ }\n DONE;\n }\n )\ndiff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc\nindex 3739a44bfd909b69a76529cc6b0ae2f01d6fb36e..6e7ee446f1b31ee8bcf121c97c1c6fa87725bf42 100644\n--- a/gcc/config/aarch64/aarch64.cc\n+++ b/gcc/config/aarch64/aarch64.cc\n@@ -11799,16 +11799,18 @@ aarch64_get_condition_code_1 (machine_mode mode, enum rtx_code comp_code)\n /* Return true if X is a CONST_INT, CONST_WIDE_INT or a constant vector\n duplicate of such constants. If so, store in RET_WI the wide_int\n representation of the constant paired with the inner mode of the vector mode\n- or TImode for scalar X constants. */\n+ or SMODE for scalar X constants. If SMODE is not provided then TImode is\n+ used. */\n \n static bool\n-aarch64_extract_vec_duplicate_wide_int (rtx x, wide_int *ret_wi)\n+aarch64_extract_vec_duplicate_wide_int (rtx x, wide_int *ret_wi,\n+\t\t\t\t\tscalar_mode mode = TImode)\n {\n rtx elt = unwrap_const_vec_duplicate (x);\n if (!CONST_SCALAR_INT_P (elt))\n return false;\n scalar_mode smode\n- = CONST_SCALAR_INT_P (x) ? TImode : GET_MODE_INNER (GET_MODE (x));\n+ = CONST_SCALAR_INT_P (x) ? mode : GET_MODE_INNER (GET_MODE (x));\n *ret_wi = rtx_mode_t (elt, smode);\n return true;\n }\n@@ -11857,6 +11859,43 @@ aarch64_const_vec_all_same_in_range_p (rtx x,\n \t && IN_RANGE (INTVAL (elt), minval, maxval));\n }\n \n+/* Some constants can't be made using normal mov instructions in Advanced SIMD\n+ but we can still create them in various ways. If the constant in VAL can be\n+ created using alternate methods then if TARGET then return true and set\n+ TARGET to the rtx for the sequence, otherwise return false if sequence is\n+ not possible. */\n+\n+bool\n+aarch64_simd_special_constant_p (rtx val, rtx target, machine_mode mode)\n+{\n+ wide_int wval;\n+ machine_mode tmode = GET_MODE (val);\n+ auto smode = GET_MODE_INNER (tmode != VOIDmode ? tmode : mode);\n+ if (!aarch64_extract_vec_duplicate_wide_int (val, &wval, smode))\n+ return false;\n+\n+ /* For Advanced SIMD we can create an integer with only the top bit set\n+ using fneg (0.0f). */\n+ if (TARGET_SIMD\n+ && !TARGET_SVE\n+ && smode == DImode\n+ && wi::only_sign_bit_p (wval))\n+ {\n+ if (!target)\n+\treturn true;\n+\n+ /* Use the same base type as aarch64_gen_shareable_zero. */\n+ rtx zero = CONST0_RTX (V4SImode);\n+ emit_move_insn (target, lowpart_subreg (mode, zero, V4SImode));\n+ rtx neg = lowpart_subreg (V2DFmode, target, mode);\n+ emit_insn (gen_negv2df2 (neg, lowpart_subreg (V2DFmode, target, mode)));\n+ emit_move_insn (target, lowpart_subreg (mode, neg, V2DFmode));\n+ return true;\n+ }\n+\n+ return false;\n+}\n+\n bool\n aarch64_const_vec_all_same_int_p (rtx x, HOST_WIDE_INT val)\n {\ndiff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md\nindex 634cfd33b41d0f945ca00d8efc9eff1ede490544..b51f979dba12b726bff0c1109b75c6d2c7ae41ab 100644\n--- a/gcc/config/aarch64/aarch64.md\n+++ b/gcc/config/aarch64/aarch64.md\n@@ -1340,13 +1340,21 @@ (define_insn_and_split \"*movdi_aarch64\"\n [r, w ; f_mrc , fp , 4] fmov\\t%x0, %d1\n [w, w ; fmov , fp , 4] fmov\\t%d0, %d1\n [w, Dd ; neon_move, simd, 4] << aarch64_output_scalar_simd_mov_immediate (operands[1], DImode);\n+ [w, Dx ; neon_move, simd, 8] #\n }\n- \"CONST_INT_P (operands[1]) && !aarch64_move_imm (INTVAL (operands[1]), DImode)\n- && REG_P (operands[0]) && GP_REGNUM_P (REGNO (operands[0]))\"\n+ \"CONST_INT_P (operands[1])\n+ && REG_P (operands[0])\n+ && ((!aarch64_move_imm (INTVAL (operands[1]), DImode)\n+\t&& GP_REGNUM_P (REGNO (operands[0])))\n+ || (aarch64_simd_special_constant_p (operands[1], NULL_RTX, DImode)\n+\t && FP_REGNUM_P (REGNO (operands[0]))))\"\n [(const_int 0)]\n {\n+ if (GP_REGNUM_P (REGNO (operands[0])))\n aarch64_expand_mov_immediate (operands[0], operands[1]);\n- DONE;\n+ else\n+ aarch64_simd_special_constant_p (operands[1], operands[0], DImode);\n+ DONE;\n }\n )\n \ndiff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md\nindex 371a00827d84d8ea4a06ba2b00a761d3b179ae90..11cf5a0d16b3364a7a4d0b2a2e5bb33063151479 100644\n--- a/gcc/config/aarch64/constraints.md\n+++ b/gcc/config/aarch64/constraints.md\n@@ -488,6 +488,14 @@ (define_constraint \"Dr\"\n (and (match_code \"const,const_vector\")\n (match_test \"aarch64_simd_shift_imm_p (op, GET_MODE (op),\n \t\t\t\t\t\t false)\")))\n+\n+(define_constraint \"Dx\"\n+ \"@internal\n+ A constraint that matches a vector of 64-bit immediates which we don't have a\n+ single instruction to create but that we can create in creative ways.\"\n+ (and (match_code \"const_int,const,const_vector\")\n+ (match_test \"aarch64_simd_special_constant_p (op, NULL_RTX, DImode)\")))\n+\n (define_constraint \"Dz\"\n \"@internal\n A constraint that matches a vector of immediate zero.\"\ndiff --git a/gcc/testsuite/gcc.target/aarch64/fneg-abs_1.c b/gcc/testsuite/gcc.target/aarch64/fneg-abs_1.c\nindex f823013c3ddf6b3a266c3abfcbf2642fc2a75fa6..43c37e21b50e13c09b8d6850686e88465cd8482a 100644\n--- a/gcc/testsuite/gcc.target/aarch64/fneg-abs_1.c\n+++ b/gcc/testsuite/gcc.target/aarch64/fneg-abs_1.c\n@@ -28,8 +28,8 @@ float32x4_t t2 (float32x4_t a)\n \n /*\n ** t3:\n-**\tadrp\tx0, .LC[0-9]+\n-**\tldr\tq[0-9]+, \\[x0, #:lo12:.LC0\\]\n+**\tmovi\tv[0-9]+.4s, 0\n+**\tfneg\tv[0-9]+.2d, v[0-9]+.2d\n **\torr\tv[0-9]+.16b, v[0-9]+.16b, v[0-9]+.16b\n **\tret\n */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c b/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c\nindex 141121176b309e4b2aa413dc55271a6e3c93d5e1..fb14ec3e2210e0feeff80f2410d777d3046a9f78 100644\n--- a/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c\n+++ b/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c\n@@ -20,8 +20,8 @@ float32_t f1 (float32_t a)\n \n /*\n ** f2:\n-**\tmov\tx0, -9223372036854775808\n-**\tfmov\td[0-9]+, x0\n+**\tfmov\td[0-9]+, xzr\n+**\tfneg\tv[0-9]+.2d, v[0-9]+.2d\n **\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n **\tret\n */\n@@ -29,3 +29,4 @@ float64_t f2 (float64_t a)\n {\n return -fabs (a);\n }\n+\ndiff --git a/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c b/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c\nindex 10879dea74462d34b26160eeb0bd54ead063166b..4ea0105f6c0a9756070bcc60d34f142f53d8242c 100644\n--- a/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c\n+++ b/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c\n@@ -8,8 +8,8 @@\n \n /*\n ** negabs:\n-**\tmov\tx0, -9223372036854775808\n-**\tfmov\td[0-9]+, x0\n+**\tfmov\td[0-9]+, xzr\n+**\tfneg\tv[0-9]+.2d, v[0-9]+.2d\n **\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n **\tret\n */", "diff": "--- a/gcc/config/aarch64/aarch64-protos.h\n+++ b/gcc/config/aarch64/aarch64-protos.h\n@@ -827,6 +827,7 @@ bool aarch64_sve_ptrue_svpattern_p (rtx, struct simd_immediate_info *);\n bool aarch64_simd_valid_immediate (rtx, struct simd_immediate_info *,\n \t\t\tenum simd_immediate_check w = AARCH64_CHECK_MOV);\n rtx aarch64_check_zero_based_sve_index_immediate (rtx);\n+bool aarch64_simd_special_constant_p (rtx, rtx, machine_mode);\n bool aarch64_sve_index_immediate_p (rtx);\n bool aarch64_sve_arith_immediate_p (machine_mode, rtx, bool);\n bool aarch64_sve_sqadd_sqsub_immediate_p (machine_mode, rtx, bool);\ndiff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md\nindex 7b4d5a37a9795fefda785aaacc246918826ed0a2..63c802d942a186b5a94c66d2e83828a82a88ffa8 100644\n--- a/gcc/config/aarch64/aarch64-simd.md\n+++ b/gcc/config/aarch64/aarch64-simd.md\n@@ -181,17 +181,28 @@ (define_insn_and_split \"*aarch64_simd_mov<VQMOV:mode>\"\n [?r , r ; multiple , * , 8] #\n [w , Dn; neon_move<q> , simd, 4] << aarch64_output_simd_mov_immediate (operands[1], 128);\n [w , Dz; fmov , * , 4] fmov\\t%d0, xzr\n+ [w , Dx; neon_move , simd, 8] #\n }\n \"&& reload_completed\n- && !(FP_REGNUM_P (REGNO (operands[0]))\n-\t&& FP_REGNUM_P (REGNO (operands[1])))\"\n+ && (!(FP_REGNUM_P (REGNO (operands[0]))\n+\t && FP_REGNUM_P (REGNO (operands[1])))\n+ || (aarch64_simd_special_constant_p (operands[1], NULL_RTX, <MODE>mode)\n+\t && FP_REGNUM_P (REGNO (operands[0]))))\"\n [(const_int 0)]\n {\n if (GP_REGNUM_P (REGNO (operands[0]))\n \t&& GP_REGNUM_P (REGNO (operands[1])))\n aarch64_simd_emit_reg_reg_move (operands, DImode, 2);\n else\n- aarch64_split_simd_move (operands[0], operands[1]);\n+ {\n+\tif (FP_REGNUM_P (REGNO (operands[0]))\n+\t && <MODE>mode == V2DImode\n+\t && aarch64_simd_special_constant_p (operands[1], operands[0],\n+\t\t\t\t\t\t<MODE>mode))\n+\t ;\n+\telse\n+\t aarch64_split_simd_move (operands[0], operands[1]);\n+ }\n DONE;\n }\n )\ndiff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc\nindex 3739a44bfd909b69a76529cc6b0ae2f01d6fb36e..6e7ee446f1b31ee8bcf121c97c1c6fa87725bf42 100644\n--- a/gcc/config/aarch64/aarch64.cc\n+++ b/gcc/config/aarch64/aarch64.cc\n@@ -11799,16 +11799,18 @@ aarch64_get_condition_code_1 (machine_mode mode, enum rtx_code comp_code)\n /* Return true if X is a CONST_INT, CONST_WIDE_INT or a constant vector\n duplicate of such constants. If so, store in RET_WI the wide_int\n representation of the constant paired with the inner mode of the vector mode\n- or TImode for scalar X constants. */\n+ or SMODE for scalar X constants. If SMODE is not provided then TImode is\n+ used. */\n \n static bool\n-aarch64_extract_vec_duplicate_wide_int (rtx x, wide_int *ret_wi)\n+aarch64_extract_vec_duplicate_wide_int (rtx x, wide_int *ret_wi,\n+\t\t\t\t\tscalar_mode mode = TImode)\n {\n rtx elt = unwrap_const_vec_duplicate (x);\n if (!CONST_SCALAR_INT_P (elt))\n return false;\n scalar_mode smode\n- = CONST_SCALAR_INT_P (x) ? TImode : GET_MODE_INNER (GET_MODE (x));\n+ = CONST_SCALAR_INT_P (x) ? mode : GET_MODE_INNER (GET_MODE (x));\n *ret_wi = rtx_mode_t (elt, smode);\n return true;\n }\n@@ -11857,6 +11859,43 @@ aarch64_const_vec_all_same_in_range_p (rtx x,\n \t && IN_RANGE (INTVAL (elt), minval, maxval));\n }\n \n+/* Some constants can't be made using normal mov instructions in Advanced SIMD\n+ but we can still create them in various ways. If the constant in VAL can be\n+ created using alternate methods then if TARGET then return true and set\n+ TARGET to the rtx for the sequence, otherwise return false if sequence is\n+ not possible. */\n+\n+bool\n+aarch64_simd_special_constant_p (rtx val, rtx target, machine_mode mode)\n+{\n+ wide_int wval;\n+ machine_mode tmode = GET_MODE (val);\n+ auto smode = GET_MODE_INNER (tmode != VOIDmode ? tmode : mode);\n+ if (!aarch64_extract_vec_duplicate_wide_int (val, &wval, smode))\n+ return false;\n+\n+ /* For Advanced SIMD we can create an integer with only the top bit set\n+ using fneg (0.0f). */\n+ if (TARGET_SIMD\n+ && !TARGET_SVE\n+ && smode == DImode\n+ && wi::only_sign_bit_p (wval))\n+ {\n+ if (!target)\n+\treturn true;\n+\n+ /* Use the same base type as aarch64_gen_shareable_zero. */\n+ rtx zero = CONST0_RTX (V4SImode);\n+ emit_move_insn (target, lowpart_subreg (mode, zero, V4SImode));\n+ rtx neg = lowpart_subreg (V2DFmode, target, mode);\n+ emit_insn (gen_negv2df2 (neg, lowpart_subreg (V2DFmode, target, mode)));\n+ emit_move_insn (target, lowpart_subreg (mode, neg, V2DFmode));\n+ return true;\n+ }\n+\n+ return false;\n+}\n+\n bool\n aarch64_const_vec_all_same_int_p (rtx x, HOST_WIDE_INT val)\n {\ndiff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md\nindex 634cfd33b41d0f945ca00d8efc9eff1ede490544..b51f979dba12b726bff0c1109b75c6d2c7ae41ab 100644\n--- a/gcc/config/aarch64/aarch64.md\n+++ b/gcc/config/aarch64/aarch64.md\n@@ -1340,13 +1340,21 @@ (define_insn_and_split \"*movdi_aarch64\"\n [r, w ; f_mrc , fp , 4] fmov\\t%x0, %d1\n [w, w ; fmov , fp , 4] fmov\\t%d0, %d1\n [w, Dd ; neon_move, simd, 4] << aarch64_output_scalar_simd_mov_immediate (operands[1], DImode);\n+ [w, Dx ; neon_move, simd, 8] #\n }\n- \"CONST_INT_P (operands[1]) && !aarch64_move_imm (INTVAL (operands[1]), DImode)\n- && REG_P (operands[0]) && GP_REGNUM_P (REGNO (operands[0]))\"\n+ \"CONST_INT_P (operands[1])\n+ && REG_P (operands[0])\n+ && ((!aarch64_move_imm (INTVAL (operands[1]), DImode)\n+\t&& GP_REGNUM_P (REGNO (operands[0])))\n+ || (aarch64_simd_special_constant_p (operands[1], NULL_RTX, DImode)\n+\t && FP_REGNUM_P (REGNO (operands[0]))))\"\n [(const_int 0)]\n {\n+ if (GP_REGNUM_P (REGNO (operands[0])))\n aarch64_expand_mov_immediate (operands[0], operands[1]);\n- DONE;\n+ else\n+ aarch64_simd_special_constant_p (operands[1], operands[0], DImode);\n+ DONE;\n }\n )\n \ndiff --git a/gcc/config/aarch64/constraints.md b/gcc/config/aarch64/constraints.md\nindex 371a00827d84d8ea4a06ba2b00a761d3b179ae90..11cf5a0d16b3364a7a4d0b2a2e5bb33063151479 100644\n--- a/gcc/config/aarch64/constraints.md\n+++ b/gcc/config/aarch64/constraints.md\n@@ -488,6 +488,14 @@ (define_constraint \"Dr\"\n (and (match_code \"const,const_vector\")\n (match_test \"aarch64_simd_shift_imm_p (op, GET_MODE (op),\n \t\t\t\t\t\t false)\")))\n+\n+(define_constraint \"Dx\"\n+ \"@internal\n+ A constraint that matches a vector of 64-bit immediates which we don't have a\n+ single instruction to create but that we can create in creative ways.\"\n+ (and (match_code \"const_int,const,const_vector\")\n+ (match_test \"aarch64_simd_special_constant_p (op, NULL_RTX, DImode)\")))\n+\n (define_constraint \"Dz\"\n \"@internal\n A constraint that matches a vector of immediate zero.\"\ndiff --git a/gcc/testsuite/gcc.target/aarch64/fneg-abs_1.c b/gcc/testsuite/gcc.target/aarch64/fneg-abs_1.c\nindex f823013c3ddf6b3a266c3abfcbf2642fc2a75fa6..43c37e21b50e13c09b8d6850686e88465cd8482a 100644\n--- a/gcc/testsuite/gcc.target/aarch64/fneg-abs_1.c\n+++ b/gcc/testsuite/gcc.target/aarch64/fneg-abs_1.c\n@@ -28,8 +28,8 @@ float32x4_t t2 (float32x4_t a)\n \n /*\n ** t3:\n-**\tadrp\tx0, .LC[0-9]+\n-**\tldr\tq[0-9]+, \\[x0, #:lo12:.LC0\\]\n+**\tmovi\tv[0-9]+.4s, 0\n+**\tfneg\tv[0-9]+.2d, v[0-9]+.2d\n **\torr\tv[0-9]+.16b, v[0-9]+.16b, v[0-9]+.16b\n **\tret\n */\ndiff --git a/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c b/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c\nindex 141121176b309e4b2aa413dc55271a6e3c93d5e1..fb14ec3e2210e0feeff80f2410d777d3046a9f78 100644\n--- a/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c\n+++ b/gcc/testsuite/gcc.target/aarch64/fneg-abs_2.c\n@@ -20,8 +20,8 @@ float32_t f1 (float32_t a)\n \n /*\n ** f2:\n-**\tmov\tx0, -9223372036854775808\n-**\tfmov\td[0-9]+, x0\n+**\tfmov\td[0-9]+, xzr\n+**\tfneg\tv[0-9]+.2d, v[0-9]+.2d\n **\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n **\tret\n */\n@@ -29,3 +29,4 @@ float64_t f2 (float64_t a)\n {\n return -fabs (a);\n }\n+\ndiff --git a/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c b/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c\nindex 10879dea74462d34b26160eeb0bd54ead063166b..4ea0105f6c0a9756070bcc60d34f142f53d8242c 100644\n--- a/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c\n+++ b/gcc/testsuite/gcc.target/aarch64/fneg-abs_4.c\n@@ -8,8 +8,8 @@\n \n /*\n ** negabs:\n-**\tmov\tx0, -9223372036854775808\n-**\tfmov\td[0-9]+, x0\n+**\tfmov\td[0-9]+, xzr\n+**\tfneg\tv[0-9]+.2d, v[0-9]+.2d\n **\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n **\tret\n */\n", "prefixes": [] }