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GET /api/patches/1839983/?format=api
{ "id": 1839983, "url": "http://patchwork.ozlabs.org/api/patches/1839983/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/patch-17724-tamar@arm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<patch-17724-tamar@arm.com>", "list_archive_url": null, "date": "2023-09-27T00:51:30", "name": "AArch64: Use SVE unpredicated LOGICAL expressions when Advanced SIMD inefficient [PR109154]", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b9564cbfdeaca02fe64b7997c1d0b87b7659632f", "submitter": { "id": 69689, "url": "http://patchwork.ozlabs.org/api/people/69689/?format=api", "name": "Tamar Christina", "email": "Tamar.Christina@arm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/patch-17724-tamar@arm.com/mbox/", "series": [ { "id": 375021, "url": "http://patchwork.ozlabs.org/api/series/375021/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=375021", "date": "2023-09-27T00:51:30", "name": "AArch64: Use SVE unpredicated LOGICAL expressions when Advanced SIMD inefficient [PR109154]", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/375021/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1839983/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1839983/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=armh.onmicrosoft.com header.i=@armh.onmicrosoft.com\n header.a=rsa-sha256 header.s=selector2-armh-onmicrosoft-com\n header.b=W9reBpQQ;\n\tdkim=pass (1024-bit key) header.d=armh.onmicrosoft.com\n header.i=@armh.onmicrosoft.com header.a=rsa-sha256\n header.s=selector2-armh-onmicrosoft-com header.b=W9reBpQQ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:3:1:0:246e:9693:128c; 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Ip=[63.35.35.123];\n Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n AM7EUR03FT033.eop-EUR03.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-Spam-Status": "No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED,\n DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_LOTSOFHASH,\n KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE,\n TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6", "X-Spam-Checker-Version": "SpamAssassin 3.4.6 (2021-04-09) on\n server2.sourceware.org", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces+incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "Hi All,\n\nSVE has much bigger immediate encoding range for bitmasks than Advanced SIMD has\nand so on a system that is SVE capable if we need an Advanced SIMD Inclusive-OR\nby immediate and would require a reload then an unpredicated SVE ORR instead.\n\nThis has both speed and size improvements.\n\nBootstrapped Regtested on aarch64-none-linux-gnu and no issues.\n\nOk for master?\n\nThanks,\nTamar\n\ngcc/ChangeLog:\n\n\tPR tree-optimization/109154\n\t* config/aarch64/aarch64.md (<optab><mode>3): Convert to new syntax and\n\tSVE split case.\n\t* config/aarch64/iterators.md (VCONV, vconv): New.\n\ngcc/testsuite/ChangeLog:\n\n\tPR tree-optimization/109154\n\t* gcc.target/aarch64/sve/fneg-abs_2.c: Updated.\n\t* gcc.target/aarch64/sve/fneg-abs_4.c: Updated.\n\n--- inline copy of patch -- \ndiff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md\nindex 60c92213c75a2a4c18a6b59ae52fe45d1e872718..377c5cafedd43d8d1320489a36267cc6e5f15239 100644\n\n\n\n\n--\ndiff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md\nindex 60c92213c75a2a4c18a6b59ae52fe45d1e872718..377c5cafedd43d8d1320489a36267cc6e5f15239 100644\n--- a/gcc/config/aarch64/aarch64.md\n+++ b/gcc/config/aarch64/aarch64.md\n@@ -4551,17 +4551,27 @@ (define_insn_and_split \"*aarch64_and<mode>_imm2\"\n }\n )\n \n-(define_insn \"<optab><mode>3\"\n- [(set (match_operand:GPI 0 \"register_operand\" \"=r,rk,w\")\n-\t(LOGICAL:GPI (match_operand:GPI 1 \"register_operand\" \"%r,r,w\")\n-\t\t (match_operand:GPI 2 \"aarch64_logical_operand\" \"r,<lconst>,w\")))]\n- \"\"\n- \"@\n- <logical>\\\\t%<w>0, %<w>1, %<w>2\n- <logical>\\\\t%<w>0, %<w>1, %2\n- <logical>\\\\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>\"\n- [(set_attr \"type\" \"logic_reg,logic_imm,neon_logic\")\n- (set_attr \"arch\" \"*,*,simd\")]\n+(define_insn_and_split \"<optab><mode>3\"\n+ [(set (match_operand:GPI 0 \"register_operand\")\n+\t(LOGICAL:GPI (match_operand:GPI 1 \"register_operand\")\n+\t\t (match_operand:GPI 2 \"aarch64_logical_operand\")))]\n+ \"\"\n+ {@ [cons: =0, 1, 2; attrs: type, arch]\n+ [r , %r, r ; logic_reg , * ] <logical>\\t%<w>0, %<w>1, %<w>2\n+ [rk, r , <lconst>; logic_imm , * ] <logical>\\t%<w>0, %<w>1, %2\n+ [w , 0 , <lconst>; * , sve ] #\n+ [w , w , w ; neon_logic, simd] <logical>\\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>\n+ }\n+ \"&& TARGET_SVE && rtx_equal_p (operands[0], operands[1])\n+ && satisfies_constraint_<lconst> (operands[2])\n+ && FP_REGNUM_P (REGNO (operands[0]))\"\n+ [(const_int 0)]\n+ {\n+ rtx op1 = lowpart_subreg (<VCONV>mode, operands[1], <MODE>mode);\n+ rtx op2 = gen_const_vec_duplicate (<VCONV>mode, operands[2]);\n+ emit_insn (gen_<optab><vconv>3 (op1, op1, op2));\n+ DONE;\n+ }\n )\n \n ;; zero_extend version of above\ndiff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md\nindex d17becc37e230684beaee3c69e2a0f0ce612eda5..568cd5d1a3a9e00475376177ad13de72609df3d8 100644\n--- a/gcc/config/aarch64/iterators.md\n+++ b/gcc/config/aarch64/iterators.md\n@@ -1432,6 +1432,11 @@ (define_mode_attr VCONQ [(V8QI \"V16QI\") (V16QI \"V16QI\")\n \t\t\t (HI \"V8HI\") (QI \"V16QI\")\n \t\t\t (SF \"V4SF\") (DF \"V2DF\")])\n \n+;; 128-bit container modes for the lower part of an SVE vector to the inner or\n+;; scalar source mode.\n+(define_mode_attr VCONV [(SI \"VNx4SI\") (DI \"VNx2DI\")])\n+(define_mode_attr vconv [(SI \"vnx4si\") (DI \"vnx2di\")])\n+\n ;; Half modes of all vector modes.\n (define_mode_attr VHALF [(V8QI \"V4QI\") (V16QI \"V8QI\")\n \t\t\t (V4HI \"V2HI\") (V8HI \"V4HI\")\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c\nindex a60cd31b9294af2dac69eed1c93f899bd5c78fca..fe9f27bf91b8fb18205a5891a5d5e847a5d88e4b 100644\n--- a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c\n@@ -7,8 +7,7 @@\n \n /*\n ** f1:\n-**\tmovi\tv[0-9]+.2s, 0x80, lsl 24\n-**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n+**\torr\tz0.s, z0.s, #0x80000000\n **\tret\n */\n float32_t f1 (float32_t a)\n@@ -18,9 +17,7 @@ float32_t f1 (float32_t a)\n \n /*\n ** f2:\n-**\tmov\tx0, -9223372036854775808\n-**\tfmov\td[0-9]+, x0\n-**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n+**\torr\tz0.d, z0.d, #0x8000000000000000\n **\tret\n */\n float64_t f2 (float64_t a)\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c\nindex 21f2a8da2a5d44e3d01f6604ca7be87e3744d494..707bcb0b6c53e212b55a255f500e9e548e9ccd80 100644\n--- a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c\n@@ -6,9 +6,7 @@\n \n /*\n ** negabs:\n-**\tmov\tx0, -9223372036854775808\n-**\tfmov\td[0-9]+, x0\n-**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n+**\torr\tz0.d, z0.d, #0x8000000000000000\n **\tret\n */\n double negabs (double x)\n@@ -22,8 +20,7 @@ double negabs (double x)\n \n /*\n ** negabsf:\n-**\tmovi\tv[0-9]+.2s, 0x80, lsl 24\n-**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n+**\torr\tz0.s, z0.s, #0x80000000\n **\tret\n */\n float negabsf (float x)", "diff": "--- a/gcc/config/aarch64/aarch64.md\n+++ b/gcc/config/aarch64/aarch64.md\n@@ -4551,17 +4551,27 @@ (define_insn_and_split \"*aarch64_and<mode>_imm2\"\n }\n )\n \n-(define_insn \"<optab><mode>3\"\n- [(set (match_operand:GPI 0 \"register_operand\" \"=r,rk,w\")\n-\t(LOGICAL:GPI (match_operand:GPI 1 \"register_operand\" \"%r,r,w\")\n-\t\t (match_operand:GPI 2 \"aarch64_logical_operand\" \"r,<lconst>,w\")))]\n- \"\"\n- \"@\n- <logical>\\\\t%<w>0, %<w>1, %<w>2\n- <logical>\\\\t%<w>0, %<w>1, %2\n- <logical>\\\\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>\"\n- [(set_attr \"type\" \"logic_reg,logic_imm,neon_logic\")\n- (set_attr \"arch\" \"*,*,simd\")]\n+(define_insn_and_split \"<optab><mode>3\"\n+ [(set (match_operand:GPI 0 \"register_operand\")\n+\t(LOGICAL:GPI (match_operand:GPI 1 \"register_operand\")\n+\t\t (match_operand:GPI 2 \"aarch64_logical_operand\")))]\n+ \"\"\n+ {@ [cons: =0, 1, 2; attrs: type, arch]\n+ [r , %r, r ; logic_reg , * ] <logical>\\t%<w>0, %<w>1, %<w>2\n+ [rk, r , <lconst>; logic_imm , * ] <logical>\\t%<w>0, %<w>1, %2\n+ [w , 0 , <lconst>; * , sve ] #\n+ [w , w , w ; neon_logic, simd] <logical>\\t%0.<Vbtype>, %1.<Vbtype>, %2.<Vbtype>\n+ }\n+ \"&& TARGET_SVE && rtx_equal_p (operands[0], operands[1])\n+ && satisfies_constraint_<lconst> (operands[2])\n+ && FP_REGNUM_P (REGNO (operands[0]))\"\n+ [(const_int 0)]\n+ {\n+ rtx op1 = lowpart_subreg (<VCONV>mode, operands[1], <MODE>mode);\n+ rtx op2 = gen_const_vec_duplicate (<VCONV>mode, operands[2]);\n+ emit_insn (gen_<optab><vconv>3 (op1, op1, op2));\n+ DONE;\n+ }\n )\n \n ;; zero_extend version of above\ndiff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md\nindex d17becc37e230684beaee3c69e2a0f0ce612eda5..568cd5d1a3a9e00475376177ad13de72609df3d8 100644\n--- a/gcc/config/aarch64/iterators.md\n+++ b/gcc/config/aarch64/iterators.md\n@@ -1432,6 +1432,11 @@ (define_mode_attr VCONQ [(V8QI \"V16QI\") (V16QI \"V16QI\")\n \t\t\t (HI \"V8HI\") (QI \"V16QI\")\n \t\t\t (SF \"V4SF\") (DF \"V2DF\")])\n \n+;; 128-bit container modes for the lower part of an SVE vector to the inner or\n+;; scalar source mode.\n+(define_mode_attr VCONV [(SI \"VNx4SI\") (DI \"VNx2DI\")])\n+(define_mode_attr vconv [(SI \"vnx4si\") (DI \"vnx2di\")])\n+\n ;; Half modes of all vector modes.\n (define_mode_attr VHALF [(V8QI \"V4QI\") (V16QI \"V8QI\")\n \t\t\t (V4HI \"V2HI\") (V8HI \"V4HI\")\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c\nindex a60cd31b9294af2dac69eed1c93f899bd5c78fca..fe9f27bf91b8fb18205a5891a5d5e847a5d88e4b 100644\n--- a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_2.c\n@@ -7,8 +7,7 @@\n \n /*\n ** f1:\n-**\tmovi\tv[0-9]+.2s, 0x80, lsl 24\n-**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n+**\torr\tz0.s, z0.s, #0x80000000\n **\tret\n */\n float32_t f1 (float32_t a)\n@@ -18,9 +17,7 @@ float32_t f1 (float32_t a)\n \n /*\n ** f2:\n-**\tmov\tx0, -9223372036854775808\n-**\tfmov\td[0-9]+, x0\n-**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n+**\torr\tz0.d, z0.d, #0x8000000000000000\n **\tret\n */\n float64_t f2 (float64_t a)\ndiff --git a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c\nindex 21f2a8da2a5d44e3d01f6604ca7be87e3744d494..707bcb0b6c53e212b55a255f500e9e548e9ccd80 100644\n--- a/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c\n+++ b/gcc/testsuite/gcc.target/aarch64/sve/fneg-abs_4.c\n@@ -6,9 +6,7 @@\n \n /*\n ** negabs:\n-**\tmov\tx0, -9223372036854775808\n-**\tfmov\td[0-9]+, x0\n-**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n+**\torr\tz0.d, z0.d, #0x8000000000000000\n **\tret\n */\n double negabs (double x)\n@@ -22,8 +20,7 @@ double negabs (double x)\n \n /*\n ** negabsf:\n-**\tmovi\tv[0-9]+.2s, 0x80, lsl 24\n-**\torr\tv[0-9]+.8b, v[0-9]+.8b, v[0-9]+.8b\n+**\torr\tz0.s, z0.s, #0x80000000\n **\tret\n */\n float negabsf (float x)\n", "prefixes": [] }