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GET /api/patches/1839930/?format=api
{ "id": 1839930, "url": "http://patchwork.ozlabs.org/api/patches/1839930/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20230926194951.183767-3-dbarboza@ventanamicro.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20230926194951.183767-3-dbarboza@ventanamicro.com>", "list_archive_url": null, "date": "2023-09-26T19:49:46", "name": "[2/6] target/riscv/cpu.c: add zihpm extension flag", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e6322c603b2a33177a3b3d6e1408ce8eb85f37ae", "submitter": { "id": 85468, "url": "http://patchwork.ozlabs.org/api/people/85468/?format=api", "name": "Daniel Henrique Barboza", "email": "dbarboza@ventanamicro.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20230926194951.183767-3-dbarboza@ventanamicro.com/mbox/", "series": [ { "id": 374996, "url": "http://patchwork.ozlabs.org/api/series/374996/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=374996", "date": "2023-09-26T19:49:50", "name": "riscv: RVA22U64 profile support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/374996/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1839930/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1839930/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com\n header.a=rsa-sha256 header.s=google header.b=WI5IjVsy;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4Rw9P06wHVz1ypD\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 27 Sep 2023 05:51:48 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1qlE4O-0003qv-Sj; Tue, 26 Sep 2023 15:50:08 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <dbarboza@ventanamicro.com>)\n id 1qlE4N-0003qa-DN\n for qemu-devel@nongnu.org; Tue, 26 Sep 2023 15:50:07 -0400", "from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <dbarboza@ventanamicro.com>)\n id 1qlE4L-0001WK-El\n for qemu-devel@nongnu.org; Tue, 26 Sep 2023 15:50:06 -0400", "by mail-pl1-x633.google.com with SMTP id\n d9443c01a7336-1c453379020so69944505ad.1\n for <qemu-devel@nongnu.org>; Tue, 26 Sep 2023 12:50:05 -0700 (PDT)", "from grind.. ([177.94.42.59]) by smtp.gmail.com with ESMTPSA id\n l6-20020a170902f68600b001c41e1e9ca7sm11386010plg.215.2023.09.26.12.50.01\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Tue, 26 Sep 2023 12:50:03 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=ventanamicro.com; s=google; t=1695757804; x=1696362604; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=VgBZ++vbfTGATiMDuFz0FQ5o0TY/lQmHz8hELrIqQ4E=;\n b=WI5IjVsyW3BmkYAO7wwK7daV3qVaMR+g8jxQinqWKNjOVxsOrt3e4phJKoGZXnvHlt\n /dgKR64TDgkIEYUoq9ayeuPzcK/uPFye+ORz40/PG2BihPpJuZaY4AreT7ghIgn0he8z\n ewTH4uiyCDczhOrDQfSyjQYS5J0EiB3aaEfI13rEy36bKpFIpmjMlR0rmF1ZV95VZ5wP\n UG81IeRv8dXWWLGmaV9U4YYkJcT3F2o2/NzPgvfbKlC9gQZemNQQ0ce4ZIWZo7xqTIAR\n O+sa0C3BBDTDcKmj98+J2X7phw83idL5Tt6JJxSzxNcDULFtkeCK60Nl9x2oPDJla8fr\n rhBA==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20230601; t=1695757804; x=1696362604;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc\n :subject:date:message-id:reply-to;\n bh=VgBZ++vbfTGATiMDuFz0FQ5o0TY/lQmHz8hELrIqQ4E=;\n b=Oh4sAOWscgg98Bq53euAvDVHzq5Chj2z+ZN5vWhctZccPfgr8yW3L92c3/pQNXW2yp\n jS+8gpbM/30ndoOTDSbd3xuE6Pz87xDtiFafwy+6Rv6Q/+aJ91v8boiUaRJmCvESRxkW\n foWyjFZe586rzMNBoWtD3Fq24l4IOIWnKqW/Gmk9wbB079TlGRVU0u/M6TAA7pvgFAG9\n 1QydKWbGmsJK3MmePWWzaTo7/V2Er/27raGd+KEsrJTKi/ST8FOO8W1cvvUkylsEZx4E\n kc7GKW2sbrZrbzWG5g8oi/3MGscAntO6ZjBYCb0F8/pbzLXYJa02X4kPmHHMOFsjq/YU\n mWbA==", "X-Gm-Message-State": "AOJu0YyYWQhTvFYHToiXpo7gCzuecwBiUhx7zxKLGFjMfx5blvaOoLnc\n TLJASUtgi2OijYzsvaEaE+vB42hxJ5EnlMiyhe8=", "X-Google-Smtp-Source": "\n AGHT+IFKzCZJlnU/ea7mSt6iZGI3hAb6+EnXRcHGHe3JntCJwCaQvnbyhrzo59Nan3qRwc4QEVWnEQ==", "X-Received": "by 2002:a17:903:2352:b0:1c3:e130:18f1 with SMTP id\n c18-20020a170903235200b001c3e13018f1mr9485531plh.20.1695757803743;\n Tue, 26 Sep 2023 12:50:03 -0700 (PDT)", "From": "Daniel Henrique Barboza <dbarboza@ventanamicro.com>", "To": "qemu-devel@nongnu.org", "Cc": "qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org,\n liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,\n Daniel Henrique Barboza <dbarboza@ventanamicro.com>", "Subject": "[PATCH 2/6] target/riscv/cpu.c: add zihpm extension flag", "Date": "Tue, 26 Sep 2023 16:49:46 -0300", "Message-ID": "<20230926194951.183767-3-dbarboza@ventanamicro.com>", "X-Mailer": "git-send-email 2.41.0", "In-Reply-To": "<20230926194951.183767-1-dbarboza@ventanamicro.com>", "References": "<20230926194951.183767-1-dbarboza@ventanamicro.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::633;\n envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x633.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "zihpm is the Hardware Performance Counters extension described in\nchapter 12 of the unprivileged spec. It describes support for 29\nunprivileged performance counters, hpmcounter3-hpmcounter21.\n\nAs with zicntr, QEMU already implements zihpm before it was even an\nextension. zihpm is also part of the RVA22 profile, so add it to QEMU\nto complement the future future profile implementation.\n\nDefault it to 'true' since it was always present in the code. Change the\nrealize() time validation to disable it in case 'icsr' isn't present and\nif there's no hardware counters (cpu->cfg.pmu_num is zero).\n\nSigned-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>\n---\n target/riscv/cpu.c | 4 +++-\n target/riscv/cpu_cfg.h | 1 +\n target/riscv/tcg/tcg-cpu.c | 4 ++++\n 3 files changed, 8 insertions(+), 1 deletion(-)", "diff": "diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex 8783a415b1..b3befccf89 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -84,6 +84,7 @@ const RISCVIsaExtData isa_edata_arr[] = {\n ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei),\n ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl),\n ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),\n+ ISA_EXT_DATA_ENTRY(zihpm, PRIV_VERSION_1_12_0, ext_ihpm),\n ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul),\n ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs),\n ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa),\n@@ -1267,10 +1268,11 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {\n MULTI_EXT_CFG_BOOL(\"svpbmt\", ext_svpbmt, false),\n \n /*\n- * Always default true - we'll disable it during\n+ * Always default true - we'll disable them during\n * realize() if needed.\n */\n MULTI_EXT_CFG_BOOL(\"zicntr\", ext_icntr, true),\n+ MULTI_EXT_CFG_BOOL(\"zihpm\", ext_ihpm, true),\n \n MULTI_EXT_CFG_BOOL(\"zba\", ext_zba, true),\n MULTI_EXT_CFG_BOOL(\"zbb\", ext_zbb, true),\ndiff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h\nindex 671b8c7cb8..cf228546da 100644\n--- a/target/riscv/cpu_cfg.h\n+++ b/target/riscv/cpu_cfg.h\n@@ -66,6 +66,7 @@ struct RISCVCPUConfig {\n bool ext_icsr;\n bool ext_icbom;\n bool ext_icboz;\n+ bool ext_ihpm;\n bool ext_zicond;\n bool ext_zihintntl;\n bool ext_zihintpause;\ndiff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c\nindex ce0fde0f5d..11e34782b9 100644\n--- a/target/riscv/tcg/tcg-cpu.c\n+++ b/target/riscv/tcg/tcg-cpu.c\n@@ -546,6 +546,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)\n cpu->cfg.ext_icntr = false;\n }\n \n+ if (cpu->cfg.ext_ihpm && (!cpu->cfg.ext_icsr || cpu->cfg.pmu_num == 0)) {\n+ cpu->cfg.ext_ihpm = false;\n+ }\n+\n /*\n * Disable isa extensions based on priv spec after we\n * validated and set everything we need.\n", "prefixes": [ "2/6" ] }