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GET /api/patches/1839929/?format=api
{ "id": 1839929, "url": "http://patchwork.ozlabs.org/api/patches/1839929/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20230926194951.183767-6-dbarboza@ventanamicro.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20230926194951.183767-6-dbarboza@ventanamicro.com>", "list_archive_url": null, "date": "2023-09-26T19:49:49", "name": "[5/6] target/riscv/tcg-cpu.c: enable profile support for vendor CPUs", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f32f671eb1db073d79a10919ba7974c10b1c27ad", "submitter": { "id": 85468, "url": "http://patchwork.ozlabs.org/api/people/85468/?format=api", "name": "Daniel Henrique Barboza", "email": "dbarboza@ventanamicro.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20230926194951.183767-6-dbarboza@ventanamicro.com/mbox/", "series": [ { "id": 374996, "url": "http://patchwork.ozlabs.org/api/series/374996/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=374996", "date": "2023-09-26T19:49:50", "name": "riscv: RVA22U64 profile support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/374996/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1839929/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1839929/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com\n header.a=rsa-sha256 header.s=google header.b=KDd+PHwJ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4Rw9NZ2vHKz1yqV\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 27 Sep 2023 05:51:26 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1qlE4m-0003wO-Mj; Tue, 26 Sep 2023 15:50:32 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <dbarboza@ventanamicro.com>)\n id 1qlE4Z-0003t8-2l\n for qemu-devel@nongnu.org; Tue, 26 Sep 2023 15:50:26 -0400", "from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <dbarboza@ventanamicro.com>)\n id 1qlE4W-0001Xl-TP\n for qemu-devel@nongnu.org; Tue, 26 Sep 2023 15:50:18 -0400", "by mail-pl1-x630.google.com with SMTP id\n d9443c01a7336-1c0ecb9a075so67773515ad.2\n for <qemu-devel@nongnu.org>; Tue, 26 Sep 2023 12:50:13 -0700 (PDT)", "from grind.. ([177.94.42.59]) by smtp.gmail.com with ESMTPSA id\n l6-20020a170902f68600b001c41e1e9ca7sm11386010plg.215.2023.09.26.12.50.09\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Tue, 26 Sep 2023 12:50:11 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=ventanamicro.com; s=google; t=1695757812; x=1696362612; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=sy9DWvnGfhIdovSiPtVQ7Y2mU8p0z4ZBY7chUUangFo=;\n b=KDd+PHwJlYtsGI2CAdcrRdRSqTCro0VefT4h7z59vQD59NYlgab9iDgtlupivPCaa5\n CLy7xIiTW+WcrxsPb9vBSTfIHS+Qf8QQGTWc74zqtMshXuUaD8ESNids1TFa3AS+Pd24\n 7QXBxRYZCg4ebIM8pCKtWgX+fvcyFRNTttw4vnQRUZL7dDOXK07ZS6u2AWjm6WQRdSIP\n TsMOKUgb//88Y8HAUlhiPwS6bCANPbke6NmES7Ix2EY2FurZMOHp2Gwnc4nWKKphqkqb\n ihE/48B2q0r7fbrM009Ql0AcDbZie5XBduih57AYOJsDbYehQPwajT26ZpwmYA1n3rE2\n mp1g==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20230601; t=1695757812; x=1696362612;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc\n :subject:date:message-id:reply-to;\n bh=sy9DWvnGfhIdovSiPtVQ7Y2mU8p0z4ZBY7chUUangFo=;\n b=UAwk0ZlibwGlboeK9ygllD2QFyXH0myJVGl3ihBjELfG0ubKtIgqXXeIYG89TosRhX\n oMB/99EAawBHz7aYBP63LVC+IJyy0k2BcYxmR2dfqss+a6l5RbGfsPTP5OaL9NYUWSNH\n P3E/2Ng+bgOBgS7qanzw+UCyJccwL7gwNTc1ahytEDovTy5EghuCo5bEsCbMQgs+xE74\n FTjH8MT2vjaYEkEP7GxB3helC1hIvlgnjnjtWGKwAUzDeEK55SUtdrdPejkr4wY3XcUt\n awdXOkyYXFErnZROE4QVJEEEcYaqmREDHpaSwm7TCpBfjtLurxBti291VgSRo2edcd10\n pB3w==", "X-Gm-Message-State": "AOJu0Yz5fFnUlzkXpnCTPs89J3rOBIdDUhYV2XZf1leJmA4mFRfX9NtG\n xwh7/3R1TPjNtMhReS8/U5seOFwaAS1Gu/mPzng=", "X-Google-Smtp-Source": "\n AGHT+IE3fdPSIpykoVG5dkti1SxHtMNh2Mb8Z2g5AD1xPqSbfXzVX9xnN3NWqyFgQZzatsAhWAZgvg==", "X-Received": "by 2002:a17:903:2452:b0:1c6:2780:3adc with SMTP id\n l18-20020a170903245200b001c627803adcmr4650431pls.24.1695757812140;\n Tue, 26 Sep 2023 12:50:12 -0700 (PDT)", "From": "Daniel Henrique Barboza <dbarboza@ventanamicro.com>", "To": "qemu-devel@nongnu.org", "Cc": "qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org,\n liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,\n Daniel Henrique Barboza <dbarboza@ventanamicro.com>", "Subject": "[PATCH 5/6] target/riscv/tcg-cpu.c: enable profile support for vendor\n CPUs", "Date": "Tue, 26 Sep 2023 16:49:49 -0300", "Message-ID": "<20230926194951.183767-6-dbarboza@ventanamicro.com>", "X-Mailer": "git-send-email 2.41.0", "In-Reply-To": "<20230926194951.183767-1-dbarboza@ventanamicro.com>", "References": "<20230926194951.183767-1-dbarboza@ventanamicro.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::630;\n envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x630.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Vendor CPUs can implement any profile they want as long as all required\nextensions are being set in their respective cpu_init().\n\nWe do not enable extensions for vendor CPUs and that will still be true\nwith profile support. The idea then is to enable the profile option for\nvendor CPUs and let users try to enable it. In case the vendor CPU\ndo not implement all mandatory extensions of the profile, error out.\nProceed as usual otherwise.\n\nHere's an example of what happens if we try to enable the rva22u64\nprofile with the veyron-v1 CPU:\n\n./qemu-system-riscv64 -M virt -cpu veyron-v1,rva22u64=true\n\nqemu-system-riscv64: can't apply global veyron-v1-riscv-cpu.rva22u64=true:\n Setting profile 'rva22u64' failed: CPU veyron-v1 does not support extension 'Zihintpause'\n\nSigned-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>\n---\n target/riscv/tcg/tcg-cpu.c | 43 ++++++++++++++++++++++++++++++++++----\n 1 file changed, 39 insertions(+), 4 deletions(-)", "diff": "diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c\nindex 03435521c9..c8f688292e 100644\n--- a/target/riscv/tcg/tcg-cpu.c\n+++ b/target/riscv/tcg/tcg-cpu.c\n@@ -99,6 +99,31 @@ static const struct TCGCPUOps riscv_tcg_ops = {\n #endif /* !CONFIG_USER_ONLY */\n };\n \n+static const char *cpu_get_multi_ext_cfg_name(uint32_t ext_offset)\n+{\n+ const RISCVCPUMultiExtConfig *prop;\n+\n+ for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {\n+ if (prop->offset == ext_offset) {\n+ return prop->name;\n+ }\n+ }\n+\n+ for (prop = riscv_cpu_experimental_exts; prop && prop->name; prop++) {\n+ if (prop->offset == ext_offset) {\n+ return prop->name;\n+ }\n+ }\n+\n+ for (prop = riscv_cpu_vendor_exts; prop && prop->name; prop++) {\n+ if (prop->offset == ext_offset) {\n+ return prop->name;\n+ }\n+ }\n+\n+ return NULL;\n+}\n+\n static int cpu_cfg_ext_get_min_version(uint32_t ext_offset)\n {\n const RISCVIsaExtData *edata;\n@@ -747,7 +772,7 @@ static void cpu_set_profile(Object *obj, Visitor *v, const char *name,\n RISCVCPU *cpu = RISCV_CPU(obj);\n CPURISCVState *env = &cpu->env;\n int i = 0;\n- bool value;\n+ bool value, generic_cpu;\n \n if (!visit_type_bool(v, name, &value, errp)) {\n return;\n@@ -758,16 +783,28 @@ static void cpu_set_profile(Object *obj, Visitor *v, const char *name,\n return;\n }\n \n+ generic_cpu = object_dynamic_cast(obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;\n+\n env->misa_ext |= profile->misa_ext;\n env->misa_ext_mask |= profile->misa_ext;\n \n for (i = 0;; i++) {\n int ext_offset = profile->ext_offsets[i];\n+ bool prev_val = isa_ext_is_enabled(cpu, ext_offset);\n \n if (ext_offset == RISCV_PROFILE_EXT_LIST_END) {\n break;\n }\n \n+ if (!prev_val && !generic_cpu) {\n+ const char *ext_name = cpu_get_multi_ext_cfg_name(ext_offset);\n+ const char *cpu_name = riscv_cpu_get_name(cpu);\n+\n+ error_setg(errp, \"Setting profile '%s' failed: CPU %s does not \"\n+ \"support extension '%s'\", name, cpu_name, ext_name);\n+ return;\n+ }\n+\n isa_ext_update_enabled(cpu, ext_offset, true);\n g_hash_table_insert(multi_ext_user_opts,\n GUINT_TO_POINTER(ext_offset),\n@@ -885,9 +922,7 @@ static void riscv_cpu_add_user_properties(Object *obj)\n riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts);\n riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts);\n \n- if (object_dynamic_cast(obj, TYPE_RISCV_DYNAMIC_CPU) != NULL) {\n- riscv_cpu_add_profile_prop(obj, &RVA22U64);\n- }\n+ riscv_cpu_add_profile_prop(obj, &RVA22U64);\n \n for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) {\n qdev_property_add_static(DEVICE(obj), prop);\n", "prefixes": [ "5/6" ] }