Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/1839928/?format=api
{ "id": 1839928, "url": "http://patchwork.ozlabs.org/api/patches/1839928/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20230926194951.183767-2-dbarboza@ventanamicro.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20230926194951.183767-2-dbarboza@ventanamicro.com>", "list_archive_url": null, "date": "2023-09-26T19:49:45", "name": "[1/6] target/riscv/cpu.c: add zicntr extension flag", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "1d05f7fcb106daf2405efc35f7f2e37006099614", "submitter": { "id": 85468, "url": "http://patchwork.ozlabs.org/api/people/85468/?format=api", "name": "Daniel Henrique Barboza", "email": "dbarboza@ventanamicro.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20230926194951.183767-2-dbarboza@ventanamicro.com/mbox/", "series": [ { "id": 374996, "url": "http://patchwork.ozlabs.org/api/series/374996/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=374996", "date": "2023-09-26T19:49:50", "name": "riscv: RVA22U64 profile support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/374996/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1839928/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1839928/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com\n header.a=rsa-sha256 header.s=google header.b=SALLpOS3;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4Rw9NS2G3zz1ypD\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 27 Sep 2023 05:51:20 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1qlE4M-0003pu-1v; Tue, 26 Sep 2023 15:50:06 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <dbarboza@ventanamicro.com>)\n id 1qlE4K-0003pW-LV\n for qemu-devel@nongnu.org; Tue, 26 Sep 2023 15:50:04 -0400", "from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <dbarboza@ventanamicro.com>)\n id 1qlE4I-0001Ip-TP\n for qemu-devel@nongnu.org; Tue, 26 Sep 2023 15:50:04 -0400", "by mail-pl1-x62c.google.com with SMTP id\n d9443c01a7336-1c724577e1fso14645ad.0\n for <qemu-devel@nongnu.org>; Tue, 26 Sep 2023 12:50:02 -0700 (PDT)", "from grind.. ([177.94.42.59]) by smtp.gmail.com with ESMTPSA id\n l6-20020a170902f68600b001c41e1e9ca7sm11386010plg.215.2023.09.26.12.49.58\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Tue, 26 Sep 2023 12:50:00 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=ventanamicro.com; s=google; t=1695757801; x=1696362601; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=uJTj/yG05+kNxL5qN2Z68Ih6ZRkTJzsbo+tX9aImP4Q=;\n b=SALLpOS3aCNOpKq52a5B2TPRCFIk7SNmZy/KG52tv1lVYqSA2tBL1IhoHPpL2lHyys\n mgzjmJPDOHkh9Tex+xFsSsA9OsdD5UdY9+yNu6NZbRmxBSdLBBiwiPHC6d/EDyzSTx6u\n Y9t2AB2WRoYnouews96EGtNlWL8OOY4OIGe/9YwHfEJ/ZBzZOSRAJ4RQzn/jfdtEZyve\n vrGK9aYfaHQoqz94svSIfuuRPBQ79iEfo+XxxxDkWZzaIqXzJfDufWDjXbMPVqU9yy7G\n YQFHzPRSgSfcMfokuzsQjssgHmRhf6VlHxFL6y75d7dXcIoO1bpqAy0xh5MQjxo7eU5X\n 4Yzw==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20230601; t=1695757801; x=1696362601;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc\n :subject:date:message-id:reply-to;\n bh=uJTj/yG05+kNxL5qN2Z68Ih6ZRkTJzsbo+tX9aImP4Q=;\n b=onEF1XUUka9wAHuibRKIZMkLWIAfYqU12Z1PYSCSgkOZF1LaEVypLik8MgF+YzD3Tx\n QhHQmyMSn4EXldDBfpwGMTS0XVr7uY1I7vflG5xnnYSnxEkquIQC4yh7hZZhsHR0DF4w\n MGW5E8am8McBdN8HIJyaZ/uiBOUs4IlTJL9KXDxliBhHX4jKqRHPFiSqyPt/xWtDrUyu\n elfjSDyIKceMjikJPw6f3vrBOl4dr0zuQ0tXXtKVk81/kvaJkyVmCAzfkWXOhhzANImI\n r7asyQypPO/mlykOlmekb5QO78dkBMouFe9c25HNoihq9vwbpT36rjcvojY5v1RTZyIi\n t7wA==", "X-Gm-Message-State": "AOJu0YwoWQHZHt4Z9cMG6po1Pzs5IQ8Z7UJivliqbILOca9hbt2ltaKS\n 2kMTm+1Nfuv6czmxS0ubZo34r98b3U3EfRTN7tA=", "X-Google-Smtp-Source": "\n AGHT+IFzvAAydcNlqALCblWijRPuPjEyYaJ93BTyHW1tJFMx6r5iowFi9SHz6io+sysr2eJENYwRiw==", "X-Received": "by 2002:a17:902:a988:b0:1c5:d8a3:8781 with SMTP id\n bh8-20020a170902a98800b001c5d8a38781mr10768899plb.55.1695757801054;\n Tue, 26 Sep 2023 12:50:01 -0700 (PDT)", "From": "Daniel Henrique Barboza <dbarboza@ventanamicro.com>", "To": "qemu-devel@nongnu.org", "Cc": "qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org,\n liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,\n Daniel Henrique Barboza <dbarboza@ventanamicro.com>", "Subject": "[PATCH 1/6] target/riscv/cpu.c: add zicntr extension flag", "Date": "Tue, 26 Sep 2023 16:49:45 -0300", "Message-ID": "<20230926194951.183767-2-dbarboza@ventanamicro.com>", "X-Mailer": "git-send-email 2.41.0", "In-Reply-To": "<20230926194951.183767-1-dbarboza@ventanamicro.com>", "References": "<20230926194951.183767-1-dbarboza@ventanamicro.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::62c;\n envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x62c.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "zicntr is the Base Counters and Timers extension described in chapter 12\nof the unprivileged spec. It describes support for RDCYCLE, RDTIME and\nRDINSTRET.\n\nQEMU already implements it way before it was a discrete extension.\nzicntr is part of the RVA22 profile, so let's add it to QEMU to make the\nfuture profile implementation flag complete.\n\nGiven than it represents an already existing feature, default it to\n'true'. Change the realize() time validation to disable it in case its\ndependency (icsr) isn't present.\n\nSigned-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>\n---\n target/riscv/cpu.c | 7 +++++++\n target/riscv/cpu_cfg.h | 1 +\n target/riscv/tcg/tcg-cpu.c | 4 ++++\n 3 files changed, 12 insertions(+)", "diff": "diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex 521bb88538..8783a415b1 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -79,6 +79,7 @@ const RISCVIsaExtData isa_edata_arr[] = {\n ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom),\n ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz),\n ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),\n+ ISA_EXT_DATA_ENTRY(zicntr, PRIV_VERSION_1_12_0, ext_icntr),\n ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr),\n ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei),\n ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl),\n@@ -1265,6 +1266,12 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {\n MULTI_EXT_CFG_BOOL(\"svnapot\", ext_svnapot, false),\n MULTI_EXT_CFG_BOOL(\"svpbmt\", ext_svpbmt, false),\n \n+ /*\n+ * Always default true - we'll disable it during\n+ * realize() if needed.\n+ */\n+ MULTI_EXT_CFG_BOOL(\"zicntr\", ext_icntr, true),\n+\n MULTI_EXT_CFG_BOOL(\"zba\", ext_zba, true),\n MULTI_EXT_CFG_BOOL(\"zbb\", ext_zbb, true),\n MULTI_EXT_CFG_BOOL(\"zbc\", ext_zbc, true),\ndiff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h\nindex 0e6a0f245c..671b8c7cb8 100644\n--- a/target/riscv/cpu_cfg.h\n+++ b/target/riscv/cpu_cfg.h\n@@ -62,6 +62,7 @@ struct RISCVCPUConfig {\n bool ext_zksh;\n bool ext_zkt;\n bool ext_ifencei;\n+ bool ext_icntr;\n bool ext_icsr;\n bool ext_icbom;\n bool ext_icboz;\ndiff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c\nindex a90ee63b06..ce0fde0f5d 100644\n--- a/target/riscv/tcg/tcg-cpu.c\n+++ b/target/riscv/tcg/tcg-cpu.c\n@@ -542,6 +542,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)\n cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zksh), true);\n }\n \n+ if (cpu->cfg.ext_icntr && !cpu->cfg.ext_icsr) {\n+ cpu->cfg.ext_icntr = false;\n+ }\n+\n /*\n * Disable isa extensions based on priv spec after we\n * validated and set everything we need.\n", "prefixes": [ "1/6" ] }