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GET /api/patches/1839925/?format=api
{ "id": 1839925, "url": "http://patchwork.ozlabs.org/api/patches/1839925/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20230926194951.183767-4-dbarboza@ventanamicro.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20230926194951.183767-4-dbarboza@ventanamicro.com>", "list_archive_url": null, "date": "2023-09-26T19:49:47", "name": "[3/6] target/riscv: add rva22u64 profile definition", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "99d0a008b36714f77c2cf9d34e291325c8e2d970", "submitter": { "id": 85468, "url": "http://patchwork.ozlabs.org/api/people/85468/?format=api", "name": "Daniel Henrique Barboza", "email": "dbarboza@ventanamicro.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20230926194951.183767-4-dbarboza@ventanamicro.com/mbox/", "series": [ { "id": 374996, "url": "http://patchwork.ozlabs.org/api/series/374996/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=374996", "date": "2023-09-26T19:49:50", "name": "riscv: RVA22U64 profile support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/374996/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1839925/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1839925/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ventanamicro.com header.i=@ventanamicro.com\n header.a=rsa-sha256 header.s=google header.b=e8S0kFC+;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4Rw9N969jyz1ypD\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 27 Sep 2023 05:51:05 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1qlE4S-0003s2-DJ; Tue, 26 Sep 2023 15:50:12 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <dbarboza@ventanamicro.com>)\n id 1qlE4Q-0003rW-1O\n for qemu-devel@nongnu.org; Tue, 26 Sep 2023 15:50:10 -0400", "from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <dbarboza@ventanamicro.com>)\n id 1qlE4O-0001X4-8Z\n for qemu-devel@nongnu.org; Tue, 26 Sep 2023 15:50:09 -0400", "by mail-pl1-x635.google.com with SMTP id\n d9443c01a7336-1c453379020so69945215ad.1\n for <qemu-devel@nongnu.org>; Tue, 26 Sep 2023 12:50:07 -0700 (PDT)", "from grind.. ([177.94.42.59]) by smtp.gmail.com with ESMTPSA id\n l6-20020a170902f68600b001c41e1e9ca7sm11386010plg.215.2023.09.26.12.50.04\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Tue, 26 Sep 2023 12:50:06 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=ventanamicro.com; s=google; t=1695757806; x=1696362606; darn=nongnu.org;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=s/ZboQFWxlADhWHzZ32NFd1Ok47zMwa/Fy7pwD6f5Rw=;\n b=e8S0kFC+tdQbsWvdBjzEnL3WWOh0CL2T95ygBVXcLUC7jhucnKS2+j7JPsYMRjaxjx\n 56brchfGJLpDOCOfWHG0LM8wBgTsCfYzo/3+Jdk2dfmH/7lOjQReR5MooUbqGnKfBlFu\n fVOJYkOP+HbeZ5yDVRNUNAcKXBXn7zZpXTpDW2kLi1BpNNcdT/CQwhZNanwWdQiGR9SY\n NKjrDSM33OystpYWiF1J0nRJFTe2RMZJKUytgKIaXtH0kxqLo7iCWgYvlayLL5eREmWE\n 7sbCRlxUBWJPf1gkKoYXjA84jBdZ/zYlgxFSg8K7f4nbUhMgJjl0QxoDGKkVJlFLp4LB\n 9C1w==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20230601; t=1695757806; x=1696362606;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc\n :subject:date:message-id:reply-to;\n bh=s/ZboQFWxlADhWHzZ32NFd1Ok47zMwa/Fy7pwD6f5Rw=;\n b=G+sWG2OSAP7ffUbF7DvlCMC9iXod2kTDvC6EbPqwtovRUzuNRnzZziIBDPmV9i+dui\n rVXnrPBgijD31oWasb9BfM2Or4Jo00qa/gqh2SUF2DXoCSEuwLvD3XFylzkGfRx/0Nxi\n BEi/UOLLYxnAhof8zgFG+RMXBeHsf8htLk8B7ln6ipKaYTbpd9lEXq7QzNT0oQ4/w7Gg\n 12xe/LC2kJpeOl5meLXPx09B70grPZn6hWC/paI/Cq7n4hm/Msp89s6ChWdC00y64l1I\n tlCO3peexq1TSR7+PpOCL0kzl/cSUpnY+w4OHMsFbLtebbrNcOtrq/g8KWdrEyto07uD\n RoqQ==", "X-Gm-Message-State": "AOJu0YzUqG5pvPhQ6vAdqmmDMkKrKDptFokCSHr3ANVxxs4QSIIvnxVC\n Sxc02I/YXHb/d3EnnQmGWM+YxdeavRxcipnEyw8=", "X-Google-Smtp-Source": "\n AGHT+IFv7Jz7JXpv3krEIsY4h2J88+yQVC+QJDpGifjVQicIcIUOzjugiJWGFmciYbcr4ACMyUuyXQ==", "X-Received": "by 2002:a17:903:2352:b0:1c3:e130:18f1 with SMTP id\n c18-20020a170903235200b001c3e13018f1mr9485663plh.20.1695757806572;\n Tue, 26 Sep 2023 12:50:06 -0700 (PDT)", "From": "Daniel Henrique Barboza <dbarboza@ventanamicro.com>", "To": "qemu-devel@nongnu.org", "Cc": "qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org,\n liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com,\n Daniel Henrique Barboza <dbarboza@ventanamicro.com>", "Subject": "[PATCH 3/6] target/riscv: add rva22u64 profile definition", "Date": "Tue, 26 Sep 2023 16:49:47 -0300", "Message-ID": "<20230926194951.183767-4-dbarboza@ventanamicro.com>", "X-Mailer": "git-send-email 2.41.0", "In-Reply-To": "<20230926194951.183767-1-dbarboza@ventanamicro.com>", "References": "<20230926194951.183767-1-dbarboza@ventanamicro.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::635;\n envelope-from=dbarboza@ventanamicro.com; helo=mail-pl1-x635.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "The rva22U64 profile, described in:\n\nhttps://github.com/riscv/riscv-profiles/blob/main/profiles.adoc#rva22-profiles\n\nContains a set of CPU extensions aimed for 64-bit userspace\napplications. Enabling this set to be enabled via a single user flag\nmakes it convenient to enable a predictable set of features for the CPU,\ngiving users more predicability when running/testing their workloads.\n\nQEMU implements all possible extensions of this profile. The exception\nis Zicbop (Cache-Block Prefetch Operations) that is not available since\nQEMU RISC-V does not implement a cache model. For this same reason all\nthe so called 'synthetic extensions' described in the profile that are\ncache related are ignored (Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa,\nZicclsm).\n\nAn abstraction called RISCVCPUProfile is created to store the profile.\n'ext_offsets' contains mandatory extensions that QEMU supports. Same\nthing with the 'misa_ext' mask. Optional extensions must be enabled\nmanually in the command line if desired.\n\nThe design here is to use the common target/riscv/cpu.c file to store\nthe profile declaration and export it to the accelerator files. Each\naccelerator is then responsible to expose it (or not) to users and how\nto enable the extensions.\n\nNext patches will implement the profile for TCG and KVM.\n\nSigned-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>\n---\n target/riscv/cpu.c | 16 ++++++++++++++++\n target/riscv/cpu.h | 10 ++++++++++\n 2 files changed, 26 insertions(+)", "diff": "diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c\nindex b3befccf89..c83807f179 100644\n--- a/target/riscv/cpu.c\n+++ b/target/riscv/cpu.c\n@@ -1376,6 +1376,22 @@ Property riscv_cpu_options[] = {\n DEFINE_PROP_END_OF_LIST(),\n };\n \n+/* Optional extensions left out: RVV, zfh, zkn, zks */\n+const RISCVCPUProfile RVA22U64 = {\n+ .name = \"rva22u64\",\n+ .misa_ext = RVM | RVA | RVF | RVD | RVC,\n+ .ext_offsets = {\n+ CPU_CFG_OFFSET(ext_icsr), CPU_CFG_OFFSET(ext_zihintpause),\n+ CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb),\n+ CPU_CFG_OFFSET(ext_zbs), CPU_CFG_OFFSET(ext_zfhmin),\n+ CPU_CFG_OFFSET(ext_zkt), CPU_CFG_OFFSET(ext_icntr),\n+ CPU_CFG_OFFSET(ext_ihpm), CPU_CFG_OFFSET(ext_icbom),\n+ CPU_CFG_OFFSET(ext_icboz),\n+\n+ RISCV_PROFILE_EXT_LIST_END\n+ }\n+};\n+\n static Property riscv_cpu_properties[] = {\n DEFINE_PROP_BOOL(\"debug\", RISCVCPU, cfg.debug, true),\n \ndiff --git a/target/riscv/cpu.h b/target/riscv/cpu.h\nindex 3f11e69223..615946b919 100644\n--- a/target/riscv/cpu.h\n+++ b/target/riscv/cpu.h\n@@ -66,6 +66,16 @@ const char *riscv_get_misa_ext_description(uint32_t bit);\n \n #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop)\n \n+typedef struct riscv_cpu_profile {\n+ const char *name;\n+ uint32_t misa_ext;\n+ const int32_t ext_offsets[];\n+} RISCVCPUProfile;\n+\n+#define RISCV_PROFILE_EXT_LIST_END -1\n+\n+extern const RISCVCPUProfile RVA22U64;\n+\n /* Privileged specification version */\n enum {\n PRIV_VERSION_1_10_0 = 0,\n", "prefixes": [ "3/6" ] }