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GET /api/patches/1825235/?format=api
{ "id": 1825235, "url": "http://patchwork.ozlabs.org/api/patches/1825235/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20230824092409.1492470-24-gaosong@loongson.cn/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20230824092409.1492470-24-gaosong@loongson.cn>", "list_archive_url": null, "date": "2023-08-24T09:24:01", "name": "[PULL,23/31] target/loongarch: Add avail_FP/FP_SP/FP_DP to check fpu instructions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "751618b3050a3feb84b5dbe178cc50899f40b315", "submitter": { "id": 82024, "url": "http://patchwork.ozlabs.org/api/people/82024/?format=api", "name": "gaosong", "email": "gaosong@loongson.cn" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20230824092409.1492470-24-gaosong@loongson.cn/mbox/", "series": [ { "id": 370173, "url": "http://patchwork.ozlabs.org/api/series/370173/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=370173", "date": "2023-08-24T09:23:41", "name": "[PULL,01/31] target/loongarch: Log I/O write accesses to CSR registers", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/370173/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1825235/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1825235/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)", "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4RWd7w1rSHz1yfF\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 24 Aug 2023 19:29:16 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1qZ6am-0005L9-O5; Thu, 24 Aug 2023 05:25:28 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <gaosong@loongson.cn>)\n id 1qZ6aH-0004CD-Ar\n for qemu-devel@nongnu.org; Thu, 24 Aug 2023 05:24:59 -0400", "from mail.loongson.cn ([114.242.206.163])\n by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from <gaosong@loongson.cn>) id 1qZ6aA-0003ii-Ei\n for qemu-devel@nongnu.org; Thu, 24 Aug 2023 05:24:54 -0400", "from loongson.cn (unknown [10.2.5.185])\n by gateway (Coremail) with SMTP id _____8CxfOrGIedkjHkbAA--.29103S3;\n Thu, 24 Aug 2023 17:24:22 +0800 (CST)", "from localhost.localdomain (unknown [10.2.5.185])\n by localhost.localdomain (Coremail) with SMTP id\n AQAAf8DxJ826IedkJjhiAA--.40637S25;\n Thu, 24 Aug 2023 17:24:21 +0800 (CST)" ], "From": "Song Gao <gaosong@loongson.cn>", "To": "qemu-devel@nongnu.org", "Cc": "stefanha@redhat.com,\n\trichard.henderson@linaro.org", "Subject": "[PULL 23/31] target/loongarch: Add avail_FP/FP_SP/FP_DP to check fpu\n instructions", "Date": "Thu, 24 Aug 2023 17:24:01 +0800", "Message-Id": "<20230824092409.1492470-24-gaosong@loongson.cn>", "X-Mailer": "git-send-email 2.39.1", "In-Reply-To": "<20230824092409.1492470-1-gaosong@loongson.cn>", "References": "<20230824092409.1492470-1-gaosong@loongson.cn>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-CM-TRANSID": "AQAAf8DxJ826IedkJjhiAA--.40637S25", "X-CM-SenderInfo": "5jdr20tqj6z05rqj20fqof0/", "X-Coremail-Antispam": "1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7\n ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx\n nUUI43ZEXa7xR_UUUUUUUUU==", "Received-SPF": "pass client-ip=114.242.206.163;\n envelope-from=gaosong@loongson.cn;\n helo=mail.loongson.cn", "X-Spam_score_int": "-18", "X-Spam_score": "-1.9", "X-Spam_bar": "-", "X-Spam_report": "(-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Song Gao <gaosong@loongson.cn>\nAcked-by: Richard Henderson <richard.henderson@linaro.org>\nMessage-ID: <20230822032724.1353391-12-gaosong@loongson.cn>\nMessage-Id: <20230822071959.35620-6-philmd@linaro.org>\n---\n .../loongarch/insn_trans/trans_farith.c.inc | 96 ++++++++++++-------\n target/loongarch/insn_trans/trans_fcmp.c.inc | 8 ++\n target/loongarch/insn_trans/trans_fcnv.c.inc | 56 +++++------\n .../loongarch/insn_trans/trans_fmemory.c.inc | 32 +++----\n target/loongarch/insn_trans/trans_fmov.c.inc | 48 ++++++++--\n target/loongarch/translate.c | 1 +\n target/loongarch/translate.h | 4 +\n 7 files changed, 159 insertions(+), 86 deletions(-)", "diff": "diff --git a/target/loongarch/insn_trans/trans_farith.c.inc b/target/loongarch/insn_trans/trans_farith.c.inc\nindex b1a1dc7b01..a7ced99fd3 100644\n--- a/target/loongarch/insn_trans/trans_farith.c.inc\n+++ b/target/loongarch/insn_trans/trans_farith.c.inc\n@@ -67,6 +67,10 @@ static bool trans_fcopysign_s(DisasContext *ctx, arg_fcopysign_s *a)\n TCGv src1 = get_fpr(ctx, a->fk);\n TCGv src2 = get_fpr(ctx, a->fj);\n \n+ if (!avail_FP_SP(ctx)) {\n+ return false;\n+ }\n+\n CHECK_FPE;\n \n tcg_gen_deposit_i64(dest, src1, src2, 0, 31);\n@@ -81,6 +85,10 @@ static bool trans_fcopysign_d(DisasContext *ctx, arg_fcopysign_d *a)\n TCGv src1 = get_fpr(ctx, a->fk);\n TCGv src2 = get_fpr(ctx, a->fj);\n \n+ if (!avail_FP_DP(ctx)) {\n+ return false;\n+ }\n+\n CHECK_FPE;\n \n tcg_gen_deposit_i64(dest, src1, src2, 0, 63);\n@@ -94,6 +102,10 @@ static bool trans_fabs_s(DisasContext *ctx, arg_fabs_s *a)\n TCGv dest = get_fpr(ctx, a->fd);\n TCGv src = get_fpr(ctx, a->fj);\n \n+ if (!avail_FP_SP(ctx)) {\n+ return false;\n+ }\n+\n CHECK_FPE;\n \n tcg_gen_andi_i64(dest, src, MAKE_64BIT_MASK(0, 31));\n@@ -108,6 +120,10 @@ static bool trans_fabs_d(DisasContext *ctx, arg_fabs_d *a)\n TCGv dest = get_fpr(ctx, a->fd);\n TCGv src = get_fpr(ctx, a->fj);\n \n+ if (!avail_FP_DP(ctx)) {\n+ return false;\n+ }\n+\n CHECK_FPE;\n \n tcg_gen_andi_i64(dest, src, MAKE_64BIT_MASK(0, 63));\n@@ -121,6 +137,10 @@ static bool trans_fneg_s(DisasContext *ctx, arg_fneg_s *a)\n TCGv dest = get_fpr(ctx, a->fd);\n TCGv src = get_fpr(ctx, a->fj);\n \n+ if (!avail_FP_SP(ctx)) {\n+ return false;\n+ }\n+\n CHECK_FPE;\n \n tcg_gen_xori_i64(dest, src, 0x80000000);\n@@ -135,6 +155,10 @@ static bool trans_fneg_d(DisasContext *ctx, arg_fneg_d *a)\n TCGv dest = get_fpr(ctx, a->fd);\n TCGv src = get_fpr(ctx, a->fj);\n \n+ if (!avail_FP_DP(ctx)) {\n+ return false;\n+ }\n+\n CHECK_FPE;\n \n tcg_gen_xori_i64(dest, src, 0x8000000000000000LL);\n@@ -143,41 +167,41 @@ static bool trans_fneg_d(DisasContext *ctx, arg_fneg_d *a)\n return true;\n }\n \n-TRANS(fadd_s, ALL, gen_fff, gen_helper_fadd_s)\n-TRANS(fadd_d, ALL, gen_fff, gen_helper_fadd_d)\n-TRANS(fsub_s, ALL, gen_fff, gen_helper_fsub_s)\n-TRANS(fsub_d, ALL, gen_fff, gen_helper_fsub_d)\n-TRANS(fmul_s, ALL, gen_fff, gen_helper_fmul_s)\n-TRANS(fmul_d, ALL, gen_fff, gen_helper_fmul_d)\n-TRANS(fdiv_s, ALL, gen_fff, gen_helper_fdiv_s)\n-TRANS(fdiv_d, ALL, gen_fff, gen_helper_fdiv_d)\n-TRANS(fmax_s, ALL, gen_fff, gen_helper_fmax_s)\n-TRANS(fmax_d, ALL, gen_fff, gen_helper_fmax_d)\n-TRANS(fmin_s, ALL, gen_fff, gen_helper_fmin_s)\n-TRANS(fmin_d, ALL, gen_fff, gen_helper_fmin_d)\n-TRANS(fmaxa_s, ALL, gen_fff, gen_helper_fmaxa_s)\n-TRANS(fmaxa_d, ALL, gen_fff, gen_helper_fmaxa_d)\n-TRANS(fmina_s, ALL, gen_fff, gen_helper_fmina_s)\n-TRANS(fmina_d, ALL, gen_fff, gen_helper_fmina_d)\n-TRANS(fscaleb_s, ALL, gen_fff, gen_helper_fscaleb_s)\n-TRANS(fscaleb_d, ALL, gen_fff, gen_helper_fscaleb_d)\n-TRANS(fsqrt_s, ALL, gen_ff, gen_helper_fsqrt_s)\n-TRANS(fsqrt_d, ALL, gen_ff, gen_helper_fsqrt_d)\n-TRANS(frecip_s, ALL, gen_ff, gen_helper_frecip_s)\n-TRANS(frecip_d, ALL, gen_ff, gen_helper_frecip_d)\n-TRANS(frsqrt_s, ALL, gen_ff, gen_helper_frsqrt_s)\n-TRANS(frsqrt_d, ALL, gen_ff, gen_helper_frsqrt_d)\n-TRANS(flogb_s, ALL, gen_ff, gen_helper_flogb_s)\n-TRANS(flogb_d, ALL, gen_ff, gen_helper_flogb_d)\n-TRANS(fclass_s, ALL, gen_ff, gen_helper_fclass_s)\n-TRANS(fclass_d, ALL, gen_ff, gen_helper_fclass_d)\n-TRANS(fmadd_s, ALL, gen_muladd, gen_helper_fmuladd_s, 0)\n-TRANS(fmadd_d, ALL, gen_muladd, gen_helper_fmuladd_d, 0)\n-TRANS(fmsub_s, ALL, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_c)\n-TRANS(fmsub_d, ALL, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_c)\n-TRANS(fnmadd_s, ALL, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_result)\n-TRANS(fnmadd_d, ALL, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_result)\n-TRANS(fnmsub_s, ALL, gen_muladd, gen_helper_fmuladd_s,\n+TRANS(fadd_s, FP_SP, gen_fff, gen_helper_fadd_s)\n+TRANS(fadd_d, FP_DP, gen_fff, gen_helper_fadd_d)\n+TRANS(fsub_s, FP_SP, gen_fff, gen_helper_fsub_s)\n+TRANS(fsub_d, FP_DP, gen_fff, gen_helper_fsub_d)\n+TRANS(fmul_s, FP_SP, gen_fff, gen_helper_fmul_s)\n+TRANS(fmul_d, FP_DP, gen_fff, gen_helper_fmul_d)\n+TRANS(fdiv_s, FP_SP, gen_fff, gen_helper_fdiv_s)\n+TRANS(fdiv_d, FP_DP, gen_fff, gen_helper_fdiv_d)\n+TRANS(fmax_s, FP_SP, gen_fff, gen_helper_fmax_s)\n+TRANS(fmax_d, FP_DP, gen_fff, gen_helper_fmax_d)\n+TRANS(fmin_s, FP_SP, gen_fff, gen_helper_fmin_s)\n+TRANS(fmin_d, FP_DP, gen_fff, gen_helper_fmin_d)\n+TRANS(fmaxa_s, FP_SP, gen_fff, gen_helper_fmaxa_s)\n+TRANS(fmaxa_d, FP_DP, gen_fff, gen_helper_fmaxa_d)\n+TRANS(fmina_s, FP_SP, gen_fff, gen_helper_fmina_s)\n+TRANS(fmina_d, FP_DP, gen_fff, gen_helper_fmina_d)\n+TRANS(fscaleb_s, FP_SP, gen_fff, gen_helper_fscaleb_s)\n+TRANS(fscaleb_d, FP_DP, gen_fff, gen_helper_fscaleb_d)\n+TRANS(fsqrt_s, FP_SP, gen_ff, gen_helper_fsqrt_s)\n+TRANS(fsqrt_d, FP_DP, gen_ff, gen_helper_fsqrt_d)\n+TRANS(frecip_s, FP_SP, gen_ff, gen_helper_frecip_s)\n+TRANS(frecip_d, FP_DP, gen_ff, gen_helper_frecip_d)\n+TRANS(frsqrt_s, FP_SP, gen_ff, gen_helper_frsqrt_s)\n+TRANS(frsqrt_d, FP_DP, gen_ff, gen_helper_frsqrt_d)\n+TRANS(flogb_s, FP_SP, gen_ff, gen_helper_flogb_s)\n+TRANS(flogb_d, FP_DP, gen_ff, gen_helper_flogb_d)\n+TRANS(fclass_s, FP_SP, gen_ff, gen_helper_fclass_s)\n+TRANS(fclass_d, FP_DP, gen_ff, gen_helper_fclass_d)\n+TRANS(fmadd_s, FP_SP, gen_muladd, gen_helper_fmuladd_s, 0)\n+TRANS(fmadd_d, FP_DP, gen_muladd, gen_helper_fmuladd_d, 0)\n+TRANS(fmsub_s, FP_SP, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_c)\n+TRANS(fmsub_d, FP_DP, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_c)\n+TRANS(fnmadd_s, FP_SP, gen_muladd, gen_helper_fmuladd_s, float_muladd_negate_result)\n+TRANS(fnmadd_d, FP_DP, gen_muladd, gen_helper_fmuladd_d, float_muladd_negate_result)\n+TRANS(fnmsub_s, FP_SP, gen_muladd, gen_helper_fmuladd_s,\n float_muladd_negate_c | float_muladd_negate_result)\n-TRANS(fnmsub_d, ALL, gen_muladd, gen_helper_fmuladd_d,\n+TRANS(fnmsub_d, FP_DP, gen_muladd, gen_helper_fmuladd_d,\n float_muladd_negate_c | float_muladd_negate_result)\ndiff --git a/target/loongarch/insn_trans/trans_fcmp.c.inc b/target/loongarch/insn_trans/trans_fcmp.c.inc\nindex a78868dbc4..43d5866a67 100644\n--- a/target/loongarch/insn_trans/trans_fcmp.c.inc\n+++ b/target/loongarch/insn_trans/trans_fcmp.c.inc\n@@ -29,6 +29,10 @@ static bool trans_fcmp_cond_s(DisasContext *ctx, arg_fcmp_cond_s *a)\n uint32_t flags;\n void (*fn)(TCGv, TCGv_env, TCGv, TCGv, TCGv_i32);\n \n+ if (!avail_FP_SP(ctx)) {\n+ return false;\n+ }\n+\n CHECK_FPE;\n \n var = tcg_temp_new();\n@@ -49,6 +53,10 @@ static bool trans_fcmp_cond_d(DisasContext *ctx, arg_fcmp_cond_d *a)\n uint32_t flags;\n void (*fn)(TCGv, TCGv_env, TCGv, TCGv, TCGv_i32);\n \n+ if (!avail_FP_DP(ctx)) {\n+ return false;\n+ }\n+\n CHECK_FPE;\n \n var = tcg_temp_new();\ndiff --git a/target/loongarch/insn_trans/trans_fcnv.c.inc b/target/loongarch/insn_trans/trans_fcnv.c.inc\nindex 329a2d6872..833c059d6d 100644\n--- a/target/loongarch/insn_trans/trans_fcnv.c.inc\n+++ b/target/loongarch/insn_trans/trans_fcnv.c.inc\n@@ -3,31 +3,31 @@\n * Copyright (c) 2021 Loongson Technology Corporation Limited\n */\n \n-TRANS(fcvt_s_d, ALL, gen_ff, gen_helper_fcvt_s_d)\n-TRANS(fcvt_d_s, ALL, gen_ff, gen_helper_fcvt_d_s)\n-TRANS(ftintrm_w_s, ALL, gen_ff, gen_helper_ftintrm_w_s)\n-TRANS(ftintrm_w_d, ALL, gen_ff, gen_helper_ftintrm_w_d)\n-TRANS(ftintrm_l_s, ALL, gen_ff, gen_helper_ftintrm_l_s)\n-TRANS(ftintrm_l_d, ALL, gen_ff, gen_helper_ftintrm_l_d)\n-TRANS(ftintrp_w_s, ALL, gen_ff, gen_helper_ftintrp_w_s)\n-TRANS(ftintrp_w_d, ALL, gen_ff, gen_helper_ftintrp_w_d)\n-TRANS(ftintrp_l_s, ALL, gen_ff, gen_helper_ftintrp_l_s)\n-TRANS(ftintrp_l_d, ALL, gen_ff, gen_helper_ftintrp_l_d)\n-TRANS(ftintrz_w_s, ALL, gen_ff, gen_helper_ftintrz_w_s)\n-TRANS(ftintrz_w_d, ALL, gen_ff, gen_helper_ftintrz_w_d)\n-TRANS(ftintrz_l_s, ALL, gen_ff, gen_helper_ftintrz_l_s)\n-TRANS(ftintrz_l_d, ALL, gen_ff, gen_helper_ftintrz_l_d)\n-TRANS(ftintrne_w_s, ALL, gen_ff, gen_helper_ftintrne_w_s)\n-TRANS(ftintrne_w_d, ALL, gen_ff, gen_helper_ftintrne_w_d)\n-TRANS(ftintrne_l_s, ALL, gen_ff, gen_helper_ftintrne_l_s)\n-TRANS(ftintrne_l_d, ALL, gen_ff, gen_helper_ftintrne_l_d)\n-TRANS(ftint_w_s, ALL, gen_ff, gen_helper_ftint_w_s)\n-TRANS(ftint_w_d, ALL, gen_ff, gen_helper_ftint_w_d)\n-TRANS(ftint_l_s, ALL, gen_ff, gen_helper_ftint_l_s)\n-TRANS(ftint_l_d, ALL, gen_ff, gen_helper_ftint_l_d)\n-TRANS(ffint_s_w, ALL, gen_ff, gen_helper_ffint_s_w)\n-TRANS(ffint_s_l, ALL, gen_ff, gen_helper_ffint_s_l)\n-TRANS(ffint_d_w, ALL, gen_ff, gen_helper_ffint_d_w)\n-TRANS(ffint_d_l, ALL, gen_ff, gen_helper_ffint_d_l)\n-TRANS(frint_s, ALL, gen_ff, gen_helper_frint_s)\n-TRANS(frint_d, ALL, gen_ff, gen_helper_frint_d)\n+TRANS(fcvt_s_d, FP_DP, gen_ff, gen_helper_fcvt_s_d)\n+TRANS(fcvt_d_s, FP_DP, gen_ff, gen_helper_fcvt_d_s)\n+TRANS(ftintrm_w_s, FP_SP, gen_ff, gen_helper_ftintrm_w_s)\n+TRANS(ftintrm_w_d, FP_DP, gen_ff, gen_helper_ftintrm_w_d)\n+TRANS(ftintrm_l_s, FP_SP, gen_ff, gen_helper_ftintrm_l_s)\n+TRANS(ftintrm_l_d, FP_DP, gen_ff, gen_helper_ftintrm_l_d)\n+TRANS(ftintrp_w_s, FP_SP, gen_ff, gen_helper_ftintrp_w_s)\n+TRANS(ftintrp_w_d, FP_DP, gen_ff, gen_helper_ftintrp_w_d)\n+TRANS(ftintrp_l_s, FP_SP, gen_ff, gen_helper_ftintrp_l_s)\n+TRANS(ftintrp_l_d, FP_DP, gen_ff, gen_helper_ftintrp_l_d)\n+TRANS(ftintrz_w_s, FP_SP, gen_ff, gen_helper_ftintrz_w_s)\n+TRANS(ftintrz_w_d, FP_DP, gen_ff, gen_helper_ftintrz_w_d)\n+TRANS(ftintrz_l_s, FP_SP, gen_ff, gen_helper_ftintrz_l_s)\n+TRANS(ftintrz_l_d, FP_DP, gen_ff, gen_helper_ftintrz_l_d)\n+TRANS(ftintrne_w_s, FP_SP, gen_ff, gen_helper_ftintrne_w_s)\n+TRANS(ftintrne_w_d, FP_DP, gen_ff, gen_helper_ftintrne_w_d)\n+TRANS(ftintrne_l_s, FP_SP, gen_ff, gen_helper_ftintrne_l_s)\n+TRANS(ftintrne_l_d, FP_DP, gen_ff, gen_helper_ftintrne_l_d)\n+TRANS(ftint_w_s, FP_SP, gen_ff, gen_helper_ftint_w_s)\n+TRANS(ftint_w_d, FP_DP, gen_ff, gen_helper_ftint_w_d)\n+TRANS(ftint_l_s, FP_SP, gen_ff, gen_helper_ftint_l_s)\n+TRANS(ftint_l_d, FP_DP, gen_ff, gen_helper_ftint_l_d)\n+TRANS(ffint_s_w, FP_SP, gen_ff, gen_helper_ffint_s_w)\n+TRANS(ffint_s_l, FP_SP, gen_ff, gen_helper_ffint_s_l)\n+TRANS(ffint_d_w, FP_DP, gen_ff, gen_helper_ffint_d_w)\n+TRANS(ffint_d_l, FP_DP, gen_ff, gen_helper_ffint_d_l)\n+TRANS(frint_s, FP_SP, gen_ff, gen_helper_frint_s)\n+TRANS(frint_d, FP_DP, gen_ff, gen_helper_frint_d)\ndiff --git a/target/loongarch/insn_trans/trans_fmemory.c.inc b/target/loongarch/insn_trans/trans_fmemory.c.inc\nindex 8e3b4522c9..5ddb8a473b 100644\n--- a/target/loongarch/insn_trans/trans_fmemory.c.inc\n+++ b/target/loongarch/insn_trans/trans_fmemory.c.inc\n@@ -140,19 +140,19 @@ static bool gen_fstore_le(DisasContext *ctx, arg_frr *a, MemOp mop)\n return true;\n }\n \n-TRANS(fld_s, ALL, gen_fload_i, MO_TEUL)\n-TRANS(fst_s, ALL, gen_fstore_i, MO_TEUL)\n-TRANS(fld_d, ALL, gen_fload_i, MO_TEUQ)\n-TRANS(fst_d, ALL, gen_fstore_i, MO_TEUQ)\n-TRANS(fldx_s, ALL, gen_floadx, MO_TEUL)\n-TRANS(fldx_d, ALL, gen_floadx, MO_TEUQ)\n-TRANS(fstx_s, ALL, gen_fstorex, MO_TEUL)\n-TRANS(fstx_d, ALL, gen_fstorex, MO_TEUQ)\n-TRANS(fldgt_s, ALL, gen_fload_gt, MO_TEUL)\n-TRANS(fldgt_d, ALL, gen_fload_gt, MO_TEUQ)\n-TRANS(fldle_s, ALL, gen_fload_le, MO_TEUL)\n-TRANS(fldle_d, ALL, gen_fload_le, MO_TEUQ)\n-TRANS(fstgt_s, ALL, gen_fstore_gt, MO_TEUL)\n-TRANS(fstgt_d, ALL, gen_fstore_gt, MO_TEUQ)\n-TRANS(fstle_s, ALL, gen_fstore_le, MO_TEUL)\n-TRANS(fstle_d, ALL, gen_fstore_le, MO_TEUQ)\n+TRANS(fld_s, FP_SP, gen_fload_i, MO_TEUL)\n+TRANS(fst_s, FP_SP, gen_fstore_i, MO_TEUL)\n+TRANS(fld_d, FP_DP, gen_fload_i, MO_TEUQ)\n+TRANS(fst_d, FP_DP, gen_fstore_i, MO_TEUQ)\n+TRANS(fldx_s, FP_SP, gen_floadx, MO_TEUL)\n+TRANS(fldx_d, FP_DP, gen_floadx, MO_TEUQ)\n+TRANS(fstx_s, FP_SP, gen_fstorex, MO_TEUL)\n+TRANS(fstx_d, FP_DP, gen_fstorex, MO_TEUQ)\n+TRANS(fldgt_s, FP_SP, gen_fload_gt, MO_TEUL)\n+TRANS(fldgt_d, FP_DP, gen_fload_gt, MO_TEUQ)\n+TRANS(fldle_s, FP_SP, gen_fload_le, MO_TEUL)\n+TRANS(fldle_d, FP_DP, gen_fload_le, MO_TEUQ)\n+TRANS(fstgt_s, FP_SP, gen_fstore_gt, MO_TEUL)\n+TRANS(fstgt_d, FP_DP, gen_fstore_gt, MO_TEUQ)\n+TRANS(fstle_s, FP_SP, gen_fstore_le, MO_TEUL)\n+TRANS(fstle_d, FP_DP, gen_fstore_le, MO_TEUQ)\ndiff --git a/target/loongarch/insn_trans/trans_fmov.c.inc b/target/loongarch/insn_trans/trans_fmov.c.inc\nindex 385bbb7929..928e127820 100644\n--- a/target/loongarch/insn_trans/trans_fmov.c.inc\n+++ b/target/loongarch/insn_trans/trans_fmov.c.inc\n@@ -15,6 +15,10 @@ static bool trans_fsel(DisasContext *ctx, arg_fsel *a)\n TCGv src2 = get_fpr(ctx, a->fk);\n TCGv cond;\n \n+ if (!avail_FP(ctx)) {\n+ return false;\n+ }\n+\n CHECK_FPE;\n \n cond = tcg_temp_new();\n@@ -48,6 +52,10 @@ static bool gen_r2f(DisasContext *ctx, arg_fr *a,\n TCGv src = gpr_src(ctx, a->rj, EXT_NONE);\n TCGv dest = get_fpr(ctx, a->fd);\n \n+ if (!avail_FP(ctx)) {\n+ return false;\n+ }\n+\n CHECK_FPE;\n \n func(dest, src);\n@@ -62,6 +70,10 @@ static bool gen_f2r(DisasContext *ctx, arg_rf *a,\n TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);\n TCGv src = get_fpr(ctx, a->fj);\n \n+ if (!avail_FP(ctx)) {\n+ return false;\n+ }\n+\n CHECK_FPE;\n \n func(dest, src);\n@@ -75,6 +87,10 @@ static bool trans_movgr2fcsr(DisasContext *ctx, arg_movgr2fcsr *a)\n uint32_t mask = fcsr_mask[a->fcsrd];\n TCGv Rj = gpr_src(ctx, a->rj, EXT_NONE);\n \n+ if (!avail_FP(ctx)) {\n+ return false;\n+ }\n+\n CHECK_FPE;\n \n if (mask == UINT32_MAX) {\n@@ -105,6 +121,10 @@ static bool trans_movfcsr2gr(DisasContext *ctx, arg_movfcsr2gr *a)\n {\n TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);\n \n+ if (!avail_FP(ctx)) {\n+ return false;\n+ }\n+\n CHECK_FPE;\n \n tcg_gen_ld32u_i64(dest, cpu_env, offsetof(CPULoongArchState, fcsr0));\n@@ -134,6 +154,10 @@ static bool trans_movfr2cf(DisasContext *ctx, arg_movfr2cf *a)\n TCGv t0;\n TCGv src = get_fpr(ctx, a->fj);\n \n+ if (!avail_FP(ctx)) {\n+ return false;\n+ }\n+\n CHECK_FPE;\n \n t0 = tcg_temp_new();\n@@ -147,6 +171,10 @@ static bool trans_movcf2fr(DisasContext *ctx, arg_movcf2fr *a)\n {\n TCGv dest = get_fpr(ctx, a->fd);\n \n+ if (!avail_FP(ctx)) {\n+ return false;\n+ }\n+\n CHECK_FPE;\n \n tcg_gen_ld8u_tl(dest, cpu_env,\n@@ -160,6 +188,10 @@ static bool trans_movgr2cf(DisasContext *ctx, arg_movgr2cf *a)\n {\n TCGv t0;\n \n+ if (!avail_FP(ctx)) {\n+ return false;\n+ }\n+\n CHECK_FPE;\n \n t0 = tcg_temp_new();\n@@ -171,6 +203,10 @@ static bool trans_movgr2cf(DisasContext *ctx, arg_movgr2cf *a)\n \n static bool trans_movcf2gr(DisasContext *ctx, arg_movcf2gr *a)\n {\n+ if (!avail_FP(ctx)) {\n+ return false;\n+ }\n+\n CHECK_FPE;\n \n tcg_gen_ld8u_tl(gpr_dst(ctx, a->rd, EXT_NONE), cpu_env,\n@@ -178,11 +214,11 @@ static bool trans_movcf2gr(DisasContext *ctx, arg_movcf2gr *a)\n return true;\n }\n \n-TRANS(fmov_s, ALL, gen_f2f, tcg_gen_mov_tl, true)\n-TRANS(fmov_d, ALL, gen_f2f, tcg_gen_mov_tl, false)\n-TRANS(movgr2fr_w, ALL, gen_r2f, gen_movgr2fr_w)\n+TRANS(fmov_s, FP_SP, gen_f2f, tcg_gen_mov_tl, true)\n+TRANS(fmov_d, FP_DP, gen_f2f, tcg_gen_mov_tl, false)\n+TRANS(movgr2fr_w, FP_SP, gen_r2f, gen_movgr2fr_w)\n TRANS(movgr2fr_d, 64, gen_r2f, tcg_gen_mov_tl)\n-TRANS(movgr2frh_w, ALL, gen_r2f, gen_movgr2frh_w)\n-TRANS(movfr2gr_s, ALL, gen_f2r, tcg_gen_ext32s_tl)\n+TRANS(movgr2frh_w, FP_DP, gen_r2f, gen_movgr2frh_w)\n+TRANS(movfr2gr_s, FP_SP, gen_f2r, tcg_gen_ext32s_tl)\n TRANS(movfr2gr_d, 64, gen_f2r, tcg_gen_mov_tl)\n-TRANS(movfrh2gr_s, ALL, gen_f2r, gen_movfrh2gr_s)\n+TRANS(movfrh2gr_s, FP_DP, gen_f2r, gen_movfrh2gr_s)\ndiff --git a/target/loongarch/translate.c b/target/loongarch/translate.c\nindex 6967e12fc3..fd393ed76d 100644\n--- a/target/loongarch/translate.c\n+++ b/target/loongarch/translate.c\n@@ -129,6 +129,7 @@ static void loongarch_tr_init_disas_context(DisasContextBase *dcbase,\n ctx->zero = tcg_constant_tl(0);\n \n ctx->cpucfg1 = env->cpucfg[1];\n+ ctx->cpucfg2 = env->cpucfg[2];\n }\n \n static void loongarch_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)\ndiff --git a/target/loongarch/translate.h b/target/loongarch/translate.h\nindex 1342446242..0f244cd83b 100644\n--- a/target/loongarch/translate.h\n+++ b/target/loongarch/translate.h\n@@ -17,6 +17,9 @@\n #define avail_ALL(C) true\n #define avail_64(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, ARCH) == \\\n CPUCFG1_ARCH_LA64)\n+#define avail_FP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP))\n+#define avail_FP_SP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_SP))\n+#define avail_FP_DP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_DP))\n \n /*\n * If an operation is being performed on less than TARGET_LONG_BITS,\n@@ -40,6 +43,7 @@ typedef struct DisasContext {\n bool la64; /* LoongArch64 mode */\n bool va32; /* 32-bit virtual address */\n uint32_t cpucfg1;\n+ uint32_t cpucfg2;\n } DisasContext;\n \n void generate_exception(DisasContext *ctx, int excp);\n", "prefixes": [ "PULL", "23/31" ] }