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GET /api/patches/1825228/?format=api
{ "id": 1825228, "url": "http://patchwork.ozlabs.org/api/patches/1825228/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20230824092409.1492470-15-gaosong@loongson.cn/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20230824092409.1492470-15-gaosong@loongson.cn>", "list_archive_url": null, "date": "2023-08-24T09:23:52", "name": "[PULL,14/31] target/loongarch: Extract make_address_i() helper", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f3dd35402a71f1ee005f520c4acae5210968fecf", "submitter": { "id": 82024, "url": "http://patchwork.ozlabs.org/api/people/82024/?format=api", "name": "gaosong", "email": "gaosong@loongson.cn" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20230824092409.1492470-15-gaosong@loongson.cn/mbox/", "series": [ { "id": 370173, "url": "http://patchwork.ozlabs.org/api/series/370173/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=370173", "date": "2023-08-24T09:23:41", "name": "[PULL,01/31] target/loongarch: Log I/O write accesses to CSR registers", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/370173/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1825228/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1825228/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)", "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4RWd6W5xwHz1yfF\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 24 Aug 2023 19:28:03 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1qZ6bT-0003HO-NF; Thu, 24 Aug 2023 05:26:11 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <gaosong@loongson.cn>)\n id 1qZ6bR-0002wH-On\n for qemu-devel@nongnu.org; Thu, 24 Aug 2023 05:26:09 -0400", "from mail.loongson.cn ([114.242.206.163])\n by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from <gaosong@loongson.cn>) id 1qZ6bO-0004D7-2u\n for qemu-devel@nongnu.org; Thu, 24 Aug 2023 05:26:09 -0400", "from loongson.cn (unknown [10.2.5.185])\n by gateway (Coremail) with SMTP id _____8BxyerCIedkYXkbAA--.46669S3;\n Thu, 24 Aug 2023 17:24:18 +0800 (CST)", "from localhost.localdomain (unknown [10.2.5.185])\n by localhost.localdomain (Coremail) with SMTP id\n AQAAf8DxJ826IedkJjhiAA--.40637S16;\n Thu, 24 Aug 2023 17:24:18 +0800 (CST)" ], "From": "Song Gao <gaosong@loongson.cn>", "To": "qemu-devel@nongnu.org", "Cc": "stefanha@redhat.com, richard.henderson@linaro.org, Jiajie Chen <c@jia.je>,\n\t=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>", "Subject": "[PULL 14/31] target/loongarch: Extract make_address_i() helper", "Date": "Thu, 24 Aug 2023 17:23:52 +0800", "Message-Id": "<20230824092409.1492470-15-gaosong@loongson.cn>", "X-Mailer": "git-send-email 2.39.1", "In-Reply-To": "<20230824092409.1492470-1-gaosong@loongson.cn>", "References": "<20230824092409.1492470-1-gaosong@loongson.cn>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-CM-TRANSID": "AQAAf8DxJ826IedkJjhiAA--.40637S16", "X-CM-SenderInfo": "5jdr20tqj6z05rqj20fqof0/", "X-Coremail-Antispam": "1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7\n ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx\n nUUI43ZEXa7xR_UUUUUUUUU==", "Received-SPF": "pass client-ip=114.242.206.163;\n envelope-from=gaosong@loongson.cn;\n helo=mail.loongson.cn", "X-Spam_score_int": "-18", "X-Spam_score": "-1.9", "X-Spam_bar": "-", "X-Spam_report": "(-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Jiajie Chen <c@jia.je>\n\nSigned-off-by: Jiajie Chen <c@jia.je>\nCo-authored-by: Richard Henderson <richard.henderson@linaro.org>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nSigned-off-by: Song Gao <gaosong@loongson.cn>\nReviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>\nMessage-ID: <20230822032724.1353391-6-gaosong@loongson.cn>\n[PMD: Extract helper from bigger patch]\nSigned-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\nMessage-Id: <20230822071405.35386-7-philmd@linaro.org>\n---\n .../loongarch/insn_trans/trans_atomic.c.inc | 5 +--\n .../loongarch/insn_trans/trans_branch.c.inc | 3 +-\n .../loongarch/insn_trans/trans_fmemory.c.inc | 12 ++-----\n target/loongarch/insn_trans/trans_lsx.c.inc | 32 +++++--------------\n .../loongarch/insn_trans/trans_memory.c.inc | 28 +++++-----------\n target/loongarch/translate.c | 6 ++++\n 6 files changed, 29 insertions(+), 57 deletions(-)", "diff": "diff --git a/target/loongarch/insn_trans/trans_atomic.c.inc b/target/loongarch/insn_trans/trans_atomic.c.inc\nindex 612709f2a7..fbc081448d 100644\n--- a/target/loongarch/insn_trans/trans_atomic.c.inc\n+++ b/target/loongarch/insn_trans/trans_atomic.c.inc\n@@ -7,9 +7,8 @@ static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp mop)\n {\n TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);\n TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);\n- TCGv t0 = tcg_temp_new();\n+ TCGv t0 = make_address_i(ctx, src1, a->imm);\n \n- tcg_gen_addi_tl(t0, src1, a->imm);\n tcg_gen_qemu_ld_i64(dest, t0, ctx->mem_idx, mop);\n tcg_gen_st_tl(t0, cpu_env, offsetof(CPULoongArchState, lladdr));\n tcg_gen_st_tl(dest, cpu_env, offsetof(CPULoongArchState, llval));\n@@ -62,6 +61,8 @@ static bool gen_am(DisasContext *ctx, arg_rrr *a,\n return false;\n }\n \n+ addr = make_address_i(ctx, addr, 0);\n+\n func(dest, addr, val, ctx->mem_idx, mop);\n gen_set_gpr(a->rd, dest, EXT_NONE);\n \ndiff --git a/target/loongarch/insn_trans/trans_branch.c.inc b/target/loongarch/insn_trans/trans_branch.c.inc\nindex a860f7e733..3ad34bcc05 100644\n--- a/target/loongarch/insn_trans/trans_branch.c.inc\n+++ b/target/loongarch/insn_trans/trans_branch.c.inc\n@@ -23,7 +23,8 @@ static bool trans_jirl(DisasContext *ctx, arg_jirl *a)\n TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);\n TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);\n \n- tcg_gen_addi_tl(cpu_pc, src1, a->imm);\n+ TCGv addr = make_address_i(ctx, src1, a->imm);\n+ tcg_gen_mov_tl(cpu_pc, addr);\n tcg_gen_movi_tl(dest, ctx->base.pc_next + 4);\n gen_set_gpr(a->rd, dest, EXT_NONE);\n tcg_gen_lookup_and_goto_ptr();\ndiff --git a/target/loongarch/insn_trans/trans_fmemory.c.inc b/target/loongarch/insn_trans/trans_fmemory.c.inc\nindex 88ad209338..bd3aba2c49 100644\n--- a/target/loongarch/insn_trans/trans_fmemory.c.inc\n+++ b/target/loongarch/insn_trans/trans_fmemory.c.inc\n@@ -17,11 +17,7 @@ static bool gen_fload_i(DisasContext *ctx, arg_fr_i *a, MemOp mop)\n \n CHECK_FPE;\n \n- if (a->imm) {\n- TCGv temp = tcg_temp_new();\n- tcg_gen_addi_tl(temp, addr, a->imm);\n- addr = temp;\n- }\n+ addr = make_address_i(ctx, addr, a->imm);\n \n tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);\n maybe_nanbox_load(dest, mop);\n@@ -37,11 +33,7 @@ static bool gen_fstore_i(DisasContext *ctx, arg_fr_i *a, MemOp mop)\n \n CHECK_FPE;\n \n- if (a->imm) {\n- TCGv temp = tcg_temp_new();\n- tcg_gen_addi_tl(temp, addr, a->imm);\n- addr = temp;\n- }\n+ addr = make_address_i(ctx, addr, a->imm);\n \n tcg_gen_qemu_st_tl(src, addr, ctx->mem_idx, mop);\n \ndiff --git a/target/loongarch/insn_trans/trans_lsx.c.inc b/target/loongarch/insn_trans/trans_lsx.c.inc\nindex 875cb7d51d..50153d6d0b 100644\n--- a/target/loongarch/insn_trans/trans_lsx.c.inc\n+++ b/target/loongarch/insn_trans/trans_lsx.c.inc\n@@ -4255,7 +4255,7 @@ TRANS(vextrins_d, gen_vv_i, gen_helper_vextrins_d)\n \n static bool trans_vld(DisasContext *ctx, arg_vr_i *a)\n {\n- TCGv addr, temp;\n+ TCGv addr;\n TCGv_i64 rl, rh;\n TCGv_i128 val;\n \n@@ -4266,11 +4266,7 @@ static bool trans_vld(DisasContext *ctx, arg_vr_i *a)\n rl = tcg_temp_new_i64();\n rh = tcg_temp_new_i64();\n \n- if (a->imm) {\n- temp = tcg_temp_new();\n- tcg_gen_addi_tl(temp, addr, a->imm);\n- addr = temp;\n- }\n+ addr = make_address_i(ctx, addr, a->imm);\n \n tcg_gen_qemu_ld_i128(val, addr, ctx->mem_idx, MO_128 | MO_TE);\n tcg_gen_extr_i128_i64(rl, rh, val);\n@@ -4282,7 +4278,7 @@ static bool trans_vld(DisasContext *ctx, arg_vr_i *a)\n \n static bool trans_vst(DisasContext *ctx, arg_vr_i *a)\n {\n- TCGv addr, temp;\n+ TCGv addr;\n TCGv_i128 val;\n TCGv_i64 ah, al;\n \n@@ -4293,11 +4289,7 @@ static bool trans_vst(DisasContext *ctx, arg_vr_i *a)\n ah = tcg_temp_new_i64();\n al = tcg_temp_new_i64();\n \n- if (a->imm) {\n- temp = tcg_temp_new();\n- tcg_gen_addi_tl(temp, addr, a->imm);\n- addr = temp;\n- }\n+ addr = make_address_i(ctx, addr, a->imm);\n \n get_vreg64(ah, a->vd, 1);\n get_vreg64(al, a->vd, 0);\n@@ -4356,7 +4348,7 @@ static bool trans_vstx(DisasContext *ctx, arg_vrr *a)\n #define VLDREPL(NAME, MO) \\\n static bool trans_## NAME (DisasContext *ctx, arg_vr_i *a) \\\n { \\\n- TCGv addr, temp; \\\n+ TCGv addr; \\\n TCGv_i64 val; \\\n \\\n CHECK_SXE; \\\n@@ -4364,11 +4356,7 @@ static bool trans_## NAME (DisasContext *ctx, arg_vr_i *a) \\\n addr = gpr_src(ctx, a->rj, EXT_NONE); \\\n val = tcg_temp_new_i64(); \\\n \\\n- if (a->imm) { \\\n- temp = tcg_temp_new(); \\\n- tcg_gen_addi_tl(temp, addr, a->imm); \\\n- addr = temp; \\\n- } \\\n+ addr = make_address_i(ctx, addr, a->imm); \\\n \\\n tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, MO); \\\n tcg_gen_gvec_dup_i64(MO, vec_full_offset(a->vd), 16, ctx->vl/8, val); \\\n@@ -4384,7 +4372,7 @@ VLDREPL(vldrepl_d, MO_64)\n #define VSTELM(NAME, MO, E) \\\n static bool trans_## NAME (DisasContext *ctx, arg_vr_ii *a) \\\n { \\\n- TCGv addr, temp; \\\n+ TCGv addr; \\\n TCGv_i64 val; \\\n \\\n CHECK_SXE; \\\n@@ -4392,11 +4380,7 @@ static bool trans_## NAME (DisasContext *ctx, arg_vr_ii *a) \\\n addr = gpr_src(ctx, a->rj, EXT_NONE); \\\n val = tcg_temp_new_i64(); \\\n \\\n- if (a->imm) { \\\n- temp = tcg_temp_new(); \\\n- tcg_gen_addi_tl(temp, addr, a->imm); \\\n- addr = temp; \\\n- } \\\n+ addr = make_address_i(ctx, addr, a->imm); \\\n \\\n tcg_gen_ld_i64(val, cpu_env, \\\n offsetof(CPULoongArchState, fpr[a->vd].vreg.E(a->imm2))); \\\ndiff --git a/target/loongarch/insn_trans/trans_memory.c.inc b/target/loongarch/insn_trans/trans_memory.c.inc\nindex ccebd0a4e0..88953f0ab0 100644\n--- a/target/loongarch/insn_trans/trans_memory.c.inc\n+++ b/target/loongarch/insn_trans/trans_memory.c.inc\n@@ -8,11 +8,7 @@ static bool gen_load(DisasContext *ctx, arg_rr_i *a, MemOp mop)\n TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);\n TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);\n \n- if (a->imm) {\n- TCGv temp = tcg_temp_new();\n- tcg_gen_addi_tl(temp, addr, a->imm);\n- addr = temp;\n- }\n+ addr = make_address_i(ctx, addr, a->imm);\n \n tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);\n gen_set_gpr(a->rd, dest, EXT_NONE);\n@@ -24,11 +20,7 @@ static bool gen_store(DisasContext *ctx, arg_rr_i *a, MemOp mop)\n TCGv data = gpr_src(ctx, a->rd, EXT_NONE);\n TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);\n \n- if (a->imm) {\n- TCGv temp = tcg_temp_new();\n- tcg_gen_addi_tl(temp, addr, a->imm);\n- addr = temp;\n- }\n+ addr = make_address_i(ctx, addr, a->imm);\n \n tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop);\n return true;\n@@ -66,6 +58,7 @@ static bool gen_load_gt(DisasContext *ctx, arg_rrr *a, MemOp mop)\n TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);\n \n gen_helper_asrtgt_d(cpu_env, src1, src2);\n+ src1 = make_address_i(ctx, src1, 0);\n tcg_gen_qemu_ld_tl(dest, src1, ctx->mem_idx, mop);\n gen_set_gpr(a->rd, dest, EXT_NONE);\n \n@@ -79,6 +72,7 @@ static bool gen_load_le(DisasContext *ctx, arg_rrr *a, MemOp mop)\n TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);\n \n gen_helper_asrtle_d(cpu_env, src1, src2);\n+ src1 = make_address_i(ctx, src1, 0);\n tcg_gen_qemu_ld_tl(dest, src1, ctx->mem_idx, mop);\n gen_set_gpr(a->rd, dest, EXT_NONE);\n \n@@ -92,6 +86,7 @@ static bool gen_store_gt(DisasContext *ctx, arg_rrr *a, MemOp mop)\n TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);\n \n gen_helper_asrtgt_d(cpu_env, src1, src2);\n+ src1 = make_address_i(ctx, src1, 0);\n tcg_gen_qemu_st_tl(data, src1, ctx->mem_idx, mop);\n \n return true;\n@@ -104,6 +99,7 @@ static bool gen_store_le(DisasContext *ctx, arg_rrr *a, MemOp mop)\n TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);\n \n gen_helper_asrtle_d(cpu_env, src1, src2);\n+ src1 = make_address_i(ctx, src1, 0);\n tcg_gen_qemu_st_tl(data, src1, ctx->mem_idx, mop);\n \n return true;\n@@ -131,11 +127,7 @@ static bool gen_ldptr(DisasContext *ctx, arg_rr_i *a, MemOp mop)\n TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);\n TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);\n \n- if (a->imm) {\n- TCGv temp = tcg_temp_new();\n- tcg_gen_addi_tl(temp, addr, a->imm);\n- addr = temp;\n- }\n+ addr = make_address_i(ctx, addr, a->imm);\n \n tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);\n gen_set_gpr(a->rd, dest, EXT_NONE);\n@@ -147,11 +139,7 @@ static bool gen_stptr(DisasContext *ctx, arg_rr_i *a, MemOp mop)\n TCGv data = gpr_src(ctx, a->rd, EXT_NONE);\n TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);\n \n- if (a->imm) {\n- TCGv temp = tcg_temp_new();\n- tcg_gen_addi_tl(temp, addr, a->imm);\n- addr = temp;\n- }\n+ addr = make_address_i(ctx, addr, a->imm);\n \n tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop);\n return true;\ndiff --git a/target/loongarch/translate.c b/target/loongarch/translate.c\nindex a68a979a55..acc54d7587 100644\n--- a/target/loongarch/translate.c\n+++ b/target/loongarch/translate.c\n@@ -220,6 +220,12 @@ static TCGv make_address_x(DisasContext *ctx, TCGv base, TCGv addend)\n return base;\n }\n \n+static TCGv make_address_i(DisasContext *ctx, TCGv base, target_long ofs)\n+{\n+ TCGv addend = ofs ? tcg_constant_tl(ofs) : NULL;\n+ return make_address_x(ctx, base, addend);\n+}\n+\n #include \"decode-insns.c.inc\"\n #include \"insn_trans/trans_arith.c.inc\"\n #include \"insn_trans/trans_shift.c.inc\"\n", "prefixes": [ "PULL", "14/31" ] }