Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/1825226/?format=api
{ "id": 1825226, "url": "http://patchwork.ozlabs.org/api/patches/1825226/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20230824092409.1492470-27-gaosong@loongson.cn/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20230824092409.1492470-27-gaosong@loongson.cn>", "list_archive_url": null, "date": "2023-08-24T09:24:04", "name": "[PULL,26/31] target/loongarch: Add avail_LSX to check LSX instructions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "54877370a20159f3f827b6ceb98d3c8aa45ba637", "submitter": { "id": 82024, "url": "http://patchwork.ozlabs.org/api/people/82024/?format=api", "name": "gaosong", "email": "gaosong@loongson.cn" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20230824092409.1492470-27-gaosong@loongson.cn/mbox/", "series": [ { "id": 370173, "url": "http://patchwork.ozlabs.org/api/series/370173/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=370173", "date": "2023-08-24T09:23:41", "name": "[PULL,01/31] target/loongarch: Log I/O write accesses to CSR registers", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/370173/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1825226/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1825226/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)", "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4RWd4t4ZZbz1yfF\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 24 Aug 2023 19:26:38 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1qZ6ar-00067L-JP; Thu, 24 Aug 2023 05:25:33 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <gaosong@loongson.cn>)\n id 1qZ6aM-0004Fv-H3\n for qemu-devel@nongnu.org; Thu, 24 Aug 2023 05:25:10 -0400", "from mail.loongson.cn ([114.242.206.163])\n by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from <gaosong@loongson.cn>) id 1qZ6aE-0003jf-42\n for qemu-devel@nongnu.org; Thu, 24 Aug 2023 05:25:01 -0400", "from loongson.cn (unknown [10.2.5.185])\n by gateway (Coremail) with SMTP id _____8CxNvHHIedklnkbAA--.55968S3;\n Thu, 24 Aug 2023 17:24:23 +0800 (CST)", "from localhost.localdomain (unknown [10.2.5.185])\n by localhost.localdomain (Coremail) with SMTP id\n AQAAf8DxJ826IedkJjhiAA--.40637S28;\n Thu, 24 Aug 2023 17:24:23 +0800 (CST)" ], "From": "Song Gao <gaosong@loongson.cn>", "To": "qemu-devel@nongnu.org", "Cc": "stefanha@redhat.com,\n\trichard.henderson@linaro.org", "Subject": "[PULL 26/31] target/loongarch: Add avail_LSX to check LSX\n instructions", "Date": "Thu, 24 Aug 2023 17:24:04 +0800", "Message-Id": "<20230824092409.1492470-27-gaosong@loongson.cn>", "X-Mailer": "git-send-email 2.39.1", "In-Reply-To": "<20230824092409.1492470-1-gaosong@loongson.cn>", "References": "<20230824092409.1492470-1-gaosong@loongson.cn>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-CM-TRANSID": "AQAAf8DxJ826IedkJjhiAA--.40637S28", "X-CM-SenderInfo": "5jdr20tqj6z05rqj20fqof0/", "X-Coremail-Antispam": "1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7\n ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx\n nUUI43ZEXa7xR_UUUUUUUUU==", "Received-SPF": "pass client-ip=114.242.206.163;\n envelope-from=gaosong@loongson.cn;\n helo=mail.loongson.cn", "X-Spam_score_int": "-18", "X-Spam_score": "-1.9", "X-Spam_bar": "-", "X-Spam_report": "(-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Signed-off-by: Song Gao <gaosong@loongson.cn>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nMessage-ID: <20230822032724.1353391-15-gaosong@loongson.cn>\nMessage-Id: <20230822073026.35776-1-philmd@linaro.org>\n---\n target/loongarch/insn_trans/trans_lsx.c.inc | 1482 ++++++++++---------\n target/loongarch/translate.h | 2 +\n 2 files changed, 823 insertions(+), 661 deletions(-)", "diff": "diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc b/target/loongarch/insn_trans/trans_lsx.c.inc\nindex 45e0e738ad..5fbf2718f7 100644\n--- a/target/loongarch/insn_trans/trans_lsx.c.inc\n+++ b/target/loongarch/insn_trans/trans_lsx.c.inc\n@@ -135,16 +135,20 @@ static bool gvec_subi(DisasContext *ctx, arg_vv_i *a, MemOp mop)\n return true;\n }\n \n-TRANS(vadd_b, ALL, gvec_vvv, MO_8, tcg_gen_gvec_add)\n-TRANS(vadd_h, ALL, gvec_vvv, MO_16, tcg_gen_gvec_add)\n-TRANS(vadd_w, ALL, gvec_vvv, MO_32, tcg_gen_gvec_add)\n-TRANS(vadd_d, ALL, gvec_vvv, MO_64, tcg_gen_gvec_add)\n+TRANS(vadd_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_add)\n+TRANS(vadd_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_add)\n+TRANS(vadd_w, LSX, gvec_vvv, MO_32, tcg_gen_gvec_add)\n+TRANS(vadd_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_add)\n \n #define VADDSUB_Q(NAME) \\\n static bool trans_v## NAME ##_q(DisasContext *ctx, arg_vvv *a) \\\n { \\\n TCGv_i64 rh, rl, ah, al, bh, bl; \\\n \\\n+ if (!avail_LSX(ctx)) { \\\n+ return false; \\\n+ } \\\n+ \\\n CHECK_SXE; \\\n \\\n rh = tcg_temp_new_i64(); \\\n@@ -170,58 +174,58 @@ static bool trans_v## NAME ##_q(DisasContext *ctx, arg_vvv *a) \\\n VADDSUB_Q(add)\n VADDSUB_Q(sub)\n \n-TRANS(vsub_b, ALL, gvec_vvv, MO_8, tcg_gen_gvec_sub)\n-TRANS(vsub_h, ALL, gvec_vvv, MO_16, tcg_gen_gvec_sub)\n-TRANS(vsub_w, ALL, gvec_vvv, MO_32, tcg_gen_gvec_sub)\n-TRANS(vsub_d, ALL, gvec_vvv, MO_64, tcg_gen_gvec_sub)\n-\n-TRANS(vaddi_bu, ALL, gvec_vv_i, MO_8, tcg_gen_gvec_addi)\n-TRANS(vaddi_hu, ALL, gvec_vv_i, MO_16, tcg_gen_gvec_addi)\n-TRANS(vaddi_wu, ALL, gvec_vv_i, MO_32, tcg_gen_gvec_addi)\n-TRANS(vaddi_du, ALL, gvec_vv_i, MO_64, tcg_gen_gvec_addi)\n-TRANS(vsubi_bu, ALL, gvec_subi, MO_8)\n-TRANS(vsubi_hu, ALL, gvec_subi, MO_16)\n-TRANS(vsubi_wu, ALL, gvec_subi, MO_32)\n-TRANS(vsubi_du, ALL, gvec_subi, MO_64)\n-\n-TRANS(vneg_b, ALL, gvec_vv, MO_8, tcg_gen_gvec_neg)\n-TRANS(vneg_h, ALL, gvec_vv, MO_16, tcg_gen_gvec_neg)\n-TRANS(vneg_w, ALL, gvec_vv, MO_32, tcg_gen_gvec_neg)\n-TRANS(vneg_d, ALL, gvec_vv, MO_64, tcg_gen_gvec_neg)\n-\n-TRANS(vsadd_b, ALL, gvec_vvv, MO_8, tcg_gen_gvec_ssadd)\n-TRANS(vsadd_h, ALL, gvec_vvv, MO_16, tcg_gen_gvec_ssadd)\n-TRANS(vsadd_w, ALL, gvec_vvv, MO_32, tcg_gen_gvec_ssadd)\n-TRANS(vsadd_d, ALL, gvec_vvv, MO_64, tcg_gen_gvec_ssadd)\n-TRANS(vsadd_bu, ALL, gvec_vvv, MO_8, tcg_gen_gvec_usadd)\n-TRANS(vsadd_hu, ALL, gvec_vvv, MO_16, tcg_gen_gvec_usadd)\n-TRANS(vsadd_wu, ALL, gvec_vvv, MO_32, tcg_gen_gvec_usadd)\n-TRANS(vsadd_du, ALL, gvec_vvv, MO_64, tcg_gen_gvec_usadd)\n-TRANS(vssub_b, ALL, gvec_vvv, MO_8, tcg_gen_gvec_sssub)\n-TRANS(vssub_h, ALL, gvec_vvv, MO_16, tcg_gen_gvec_sssub)\n-TRANS(vssub_w, ALL, gvec_vvv, MO_32, tcg_gen_gvec_sssub)\n-TRANS(vssub_d, ALL, gvec_vvv, MO_64, tcg_gen_gvec_sssub)\n-TRANS(vssub_bu, ALL, gvec_vvv, MO_8, tcg_gen_gvec_ussub)\n-TRANS(vssub_hu, ALL, gvec_vvv, MO_16, tcg_gen_gvec_ussub)\n-TRANS(vssub_wu, ALL, gvec_vvv, MO_32, tcg_gen_gvec_ussub)\n-TRANS(vssub_du, ALL, gvec_vvv, MO_64, tcg_gen_gvec_ussub)\n-\n-TRANS(vhaddw_h_b, ALL, gen_vvv, gen_helper_vhaddw_h_b)\n-TRANS(vhaddw_w_h, ALL, gen_vvv, gen_helper_vhaddw_w_h)\n-TRANS(vhaddw_d_w, ALL, gen_vvv, gen_helper_vhaddw_d_w)\n-TRANS(vhaddw_q_d, ALL, gen_vvv, gen_helper_vhaddw_q_d)\n-TRANS(vhaddw_hu_bu, ALL, gen_vvv, gen_helper_vhaddw_hu_bu)\n-TRANS(vhaddw_wu_hu, ALL, gen_vvv, gen_helper_vhaddw_wu_hu)\n-TRANS(vhaddw_du_wu, ALL, gen_vvv, gen_helper_vhaddw_du_wu)\n-TRANS(vhaddw_qu_du, ALL, gen_vvv, gen_helper_vhaddw_qu_du)\n-TRANS(vhsubw_h_b, ALL, gen_vvv, gen_helper_vhsubw_h_b)\n-TRANS(vhsubw_w_h, ALL, gen_vvv, gen_helper_vhsubw_w_h)\n-TRANS(vhsubw_d_w, ALL, gen_vvv, gen_helper_vhsubw_d_w)\n-TRANS(vhsubw_q_d, ALL, gen_vvv, gen_helper_vhsubw_q_d)\n-TRANS(vhsubw_hu_bu, ALL, gen_vvv, gen_helper_vhsubw_hu_bu)\n-TRANS(vhsubw_wu_hu, ALL, gen_vvv, gen_helper_vhsubw_wu_hu)\n-TRANS(vhsubw_du_wu, ALL, gen_vvv, gen_helper_vhsubw_du_wu)\n-TRANS(vhsubw_qu_du, ALL, gen_vvv, gen_helper_vhsubw_qu_du)\n+TRANS(vsub_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_sub)\n+TRANS(vsub_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_sub)\n+TRANS(vsub_w, LSX, gvec_vvv, MO_32, tcg_gen_gvec_sub)\n+TRANS(vsub_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_sub)\n+\n+TRANS(vaddi_bu, LSX, gvec_vv_i, MO_8, tcg_gen_gvec_addi)\n+TRANS(vaddi_hu, LSX, gvec_vv_i, MO_16, tcg_gen_gvec_addi)\n+TRANS(vaddi_wu, LSX, gvec_vv_i, MO_32, tcg_gen_gvec_addi)\n+TRANS(vaddi_du, LSX, gvec_vv_i, MO_64, tcg_gen_gvec_addi)\n+TRANS(vsubi_bu, LSX, gvec_subi, MO_8)\n+TRANS(vsubi_hu, LSX, gvec_subi, MO_16)\n+TRANS(vsubi_wu, LSX, gvec_subi, MO_32)\n+TRANS(vsubi_du, LSX, gvec_subi, MO_64)\n+\n+TRANS(vneg_b, LSX, gvec_vv, MO_8, tcg_gen_gvec_neg)\n+TRANS(vneg_h, LSX, gvec_vv, MO_16, tcg_gen_gvec_neg)\n+TRANS(vneg_w, LSX, gvec_vv, MO_32, tcg_gen_gvec_neg)\n+TRANS(vneg_d, LSX, gvec_vv, MO_64, tcg_gen_gvec_neg)\n+\n+TRANS(vsadd_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_ssadd)\n+TRANS(vsadd_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_ssadd)\n+TRANS(vsadd_w, LSX, gvec_vvv, MO_32, tcg_gen_gvec_ssadd)\n+TRANS(vsadd_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_ssadd)\n+TRANS(vsadd_bu, LSX, gvec_vvv, MO_8, tcg_gen_gvec_usadd)\n+TRANS(vsadd_hu, LSX, gvec_vvv, MO_16, tcg_gen_gvec_usadd)\n+TRANS(vsadd_wu, LSX, gvec_vvv, MO_32, tcg_gen_gvec_usadd)\n+TRANS(vsadd_du, LSX, gvec_vvv, MO_64, tcg_gen_gvec_usadd)\n+TRANS(vssub_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_sssub)\n+TRANS(vssub_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_sssub)\n+TRANS(vssub_w, LSX, gvec_vvv, MO_32, tcg_gen_gvec_sssub)\n+TRANS(vssub_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_sssub)\n+TRANS(vssub_bu, LSX, gvec_vvv, MO_8, tcg_gen_gvec_ussub)\n+TRANS(vssub_hu, LSX, gvec_vvv, MO_16, tcg_gen_gvec_ussub)\n+TRANS(vssub_wu, LSX, gvec_vvv, MO_32, tcg_gen_gvec_ussub)\n+TRANS(vssub_du, LSX, gvec_vvv, MO_64, tcg_gen_gvec_ussub)\n+\n+TRANS(vhaddw_h_b, LSX, gen_vvv, gen_helper_vhaddw_h_b)\n+TRANS(vhaddw_w_h, LSX, gen_vvv, gen_helper_vhaddw_w_h)\n+TRANS(vhaddw_d_w, LSX, gen_vvv, gen_helper_vhaddw_d_w)\n+TRANS(vhaddw_q_d, LSX, gen_vvv, gen_helper_vhaddw_q_d)\n+TRANS(vhaddw_hu_bu, LSX, gen_vvv, gen_helper_vhaddw_hu_bu)\n+TRANS(vhaddw_wu_hu, LSX, gen_vvv, gen_helper_vhaddw_wu_hu)\n+TRANS(vhaddw_du_wu, LSX, gen_vvv, gen_helper_vhaddw_du_wu)\n+TRANS(vhaddw_qu_du, LSX, gen_vvv, gen_helper_vhaddw_qu_du)\n+TRANS(vhsubw_h_b, LSX, gen_vvv, gen_helper_vhsubw_h_b)\n+TRANS(vhsubw_w_h, LSX, gen_vvv, gen_helper_vhsubw_w_h)\n+TRANS(vhsubw_d_w, LSX, gen_vvv, gen_helper_vhsubw_d_w)\n+TRANS(vhsubw_q_d, LSX, gen_vvv, gen_helper_vhsubw_q_d)\n+TRANS(vhsubw_hu_bu, LSX, gen_vvv, gen_helper_vhsubw_hu_bu)\n+TRANS(vhsubw_wu_hu, LSX, gen_vvv, gen_helper_vhsubw_wu_hu)\n+TRANS(vhsubw_du_wu, LSX, gen_vvv, gen_helper_vhsubw_du_wu)\n+TRANS(vhsubw_qu_du, LSX, gen_vvv, gen_helper_vhsubw_qu_du)\n \n static void gen_vaddwev_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)\n {\n@@ -301,10 +305,10 @@ static void do_vaddwev_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vaddwev_h_b, ALL, gvec_vvv, MO_8, do_vaddwev_s)\n-TRANS(vaddwev_w_h, ALL, gvec_vvv, MO_16, do_vaddwev_s)\n-TRANS(vaddwev_d_w, ALL, gvec_vvv, MO_32, do_vaddwev_s)\n-TRANS(vaddwev_q_d, ALL, gvec_vvv, MO_64, do_vaddwev_s)\n+TRANS(vaddwev_h_b, LSX, gvec_vvv, MO_8, do_vaddwev_s)\n+TRANS(vaddwev_w_h, LSX, gvec_vvv, MO_16, do_vaddwev_s)\n+TRANS(vaddwev_d_w, LSX, gvec_vvv, MO_32, do_vaddwev_s)\n+TRANS(vaddwev_q_d, LSX, gvec_vvv, MO_64, do_vaddwev_s)\n \n static void gen_vaddwod_w_h(TCGv_i32 t, TCGv_i32 a, TCGv_i32 b)\n {\n@@ -380,10 +384,10 @@ static void do_vaddwod_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vaddwod_h_b, ALL, gvec_vvv, MO_8, do_vaddwod_s)\n-TRANS(vaddwod_w_h, ALL, gvec_vvv, MO_16, do_vaddwod_s)\n-TRANS(vaddwod_d_w, ALL, gvec_vvv, MO_32, do_vaddwod_s)\n-TRANS(vaddwod_q_d, ALL, gvec_vvv, MO_64, do_vaddwod_s)\n+TRANS(vaddwod_h_b, LSX, gvec_vvv, MO_8, do_vaddwod_s)\n+TRANS(vaddwod_w_h, LSX, gvec_vvv, MO_16, do_vaddwod_s)\n+TRANS(vaddwod_d_w, LSX, gvec_vvv, MO_32, do_vaddwod_s)\n+TRANS(vaddwod_q_d, LSX, gvec_vvv, MO_64, do_vaddwod_s)\n \n static void gen_vsubwev_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)\n {\n@@ -463,10 +467,10 @@ static void do_vsubwev_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vsubwev_h_b, ALL, gvec_vvv, MO_8, do_vsubwev_s)\n-TRANS(vsubwev_w_h, ALL, gvec_vvv, MO_16, do_vsubwev_s)\n-TRANS(vsubwev_d_w, ALL, gvec_vvv, MO_32, do_vsubwev_s)\n-TRANS(vsubwev_q_d, ALL, gvec_vvv, MO_64, do_vsubwev_s)\n+TRANS(vsubwev_h_b, LSX, gvec_vvv, MO_8, do_vsubwev_s)\n+TRANS(vsubwev_w_h, LSX, gvec_vvv, MO_16, do_vsubwev_s)\n+TRANS(vsubwev_d_w, LSX, gvec_vvv, MO_32, do_vsubwev_s)\n+TRANS(vsubwev_q_d, LSX, gvec_vvv, MO_64, do_vsubwev_s)\n \n static void gen_vsubwod_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)\n {\n@@ -542,10 +546,10 @@ static void do_vsubwod_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vsubwod_h_b, ALL, gvec_vvv, MO_8, do_vsubwod_s)\n-TRANS(vsubwod_w_h, ALL, gvec_vvv, MO_16, do_vsubwod_s)\n-TRANS(vsubwod_d_w, ALL, gvec_vvv, MO_32, do_vsubwod_s)\n-TRANS(vsubwod_q_d, ALL, gvec_vvv, MO_64, do_vsubwod_s)\n+TRANS(vsubwod_h_b, LSX, gvec_vvv, MO_8, do_vsubwod_s)\n+TRANS(vsubwod_w_h, LSX, gvec_vvv, MO_16, do_vsubwod_s)\n+TRANS(vsubwod_d_w, LSX, gvec_vvv, MO_32, do_vsubwod_s)\n+TRANS(vsubwod_q_d, LSX, gvec_vvv, MO_64, do_vsubwod_s)\n \n static void gen_vaddwev_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)\n {\n@@ -617,10 +621,10 @@ static void do_vaddwev_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vaddwev_h_bu, ALL, gvec_vvv, MO_8, do_vaddwev_u)\n-TRANS(vaddwev_w_hu, ALL, gvec_vvv, MO_16, do_vaddwev_u)\n-TRANS(vaddwev_d_wu, ALL, gvec_vvv, MO_32, do_vaddwev_u)\n-TRANS(vaddwev_q_du, ALL, gvec_vvv, MO_64, do_vaddwev_u)\n+TRANS(vaddwev_h_bu, LSX, gvec_vvv, MO_8, do_vaddwev_u)\n+TRANS(vaddwev_w_hu, LSX, gvec_vvv, MO_16, do_vaddwev_u)\n+TRANS(vaddwev_d_wu, LSX, gvec_vvv, MO_32, do_vaddwev_u)\n+TRANS(vaddwev_q_du, LSX, gvec_vvv, MO_64, do_vaddwev_u)\n \n static void gen_vaddwod_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)\n {\n@@ -696,10 +700,10 @@ static void do_vaddwod_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vaddwod_h_bu, ALL, gvec_vvv, MO_8, do_vaddwod_u)\n-TRANS(vaddwod_w_hu, ALL, gvec_vvv, MO_16, do_vaddwod_u)\n-TRANS(vaddwod_d_wu, ALL, gvec_vvv, MO_32, do_vaddwod_u)\n-TRANS(vaddwod_q_du, ALL, gvec_vvv, MO_64, do_vaddwod_u)\n+TRANS(vaddwod_h_bu, LSX, gvec_vvv, MO_8, do_vaddwod_u)\n+TRANS(vaddwod_w_hu, LSX, gvec_vvv, MO_16, do_vaddwod_u)\n+TRANS(vaddwod_d_wu, LSX, gvec_vvv, MO_32, do_vaddwod_u)\n+TRANS(vaddwod_q_du, LSX, gvec_vvv, MO_64, do_vaddwod_u)\n \n static void gen_vsubwev_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)\n {\n@@ -771,10 +775,10 @@ static void do_vsubwev_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vsubwev_h_bu, ALL, gvec_vvv, MO_8, do_vsubwev_u)\n-TRANS(vsubwev_w_hu, ALL, gvec_vvv, MO_16, do_vsubwev_u)\n-TRANS(vsubwev_d_wu, ALL, gvec_vvv, MO_32, do_vsubwev_u)\n-TRANS(vsubwev_q_du, ALL, gvec_vvv, MO_64, do_vsubwev_u)\n+TRANS(vsubwev_h_bu, LSX, gvec_vvv, MO_8, do_vsubwev_u)\n+TRANS(vsubwev_w_hu, LSX, gvec_vvv, MO_16, do_vsubwev_u)\n+TRANS(vsubwev_d_wu, LSX, gvec_vvv, MO_32, do_vsubwev_u)\n+TRANS(vsubwev_q_du, LSX, gvec_vvv, MO_64, do_vsubwev_u)\n \n static void gen_vsubwod_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)\n {\n@@ -850,10 +854,10 @@ static void do_vsubwod_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vsubwod_h_bu, ALL, gvec_vvv, MO_8, do_vsubwod_u)\n-TRANS(vsubwod_w_hu, ALL, gvec_vvv, MO_16, do_vsubwod_u)\n-TRANS(vsubwod_d_wu, ALL, gvec_vvv, MO_32, do_vsubwod_u)\n-TRANS(vsubwod_q_du, ALL, gvec_vvv, MO_64, do_vsubwod_u)\n+TRANS(vsubwod_h_bu, LSX, gvec_vvv, MO_8, do_vsubwod_u)\n+TRANS(vsubwod_w_hu, LSX, gvec_vvv, MO_16, do_vsubwod_u)\n+TRANS(vsubwod_d_wu, LSX, gvec_vvv, MO_32, do_vsubwod_u)\n+TRANS(vsubwod_q_du, LSX, gvec_vvv, MO_64, do_vsubwod_u)\n \n static void gen_vaddwev_u_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)\n {\n@@ -933,10 +937,10 @@ static void do_vaddwev_u_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vaddwev_h_bu_b, ALL, gvec_vvv, MO_8, do_vaddwev_u_s)\n-TRANS(vaddwev_w_hu_h, ALL, gvec_vvv, MO_16, do_vaddwev_u_s)\n-TRANS(vaddwev_d_wu_w, ALL, gvec_vvv, MO_32, do_vaddwev_u_s)\n-TRANS(vaddwev_q_du_d, ALL, gvec_vvv, MO_64, do_vaddwev_u_s)\n+TRANS(vaddwev_h_bu_b, LSX, gvec_vvv, MO_8, do_vaddwev_u_s)\n+TRANS(vaddwev_w_hu_h, LSX, gvec_vvv, MO_16, do_vaddwev_u_s)\n+TRANS(vaddwev_d_wu_w, LSX, gvec_vvv, MO_32, do_vaddwev_u_s)\n+TRANS(vaddwev_q_du_d, LSX, gvec_vvv, MO_64, do_vaddwev_u_s)\n \n static void gen_vaddwod_u_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)\n {\n@@ -1013,10 +1017,10 @@ static void do_vaddwod_u_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vaddwod_h_bu_b, ALL, gvec_vvv, MO_8, do_vaddwod_u_s)\n-TRANS(vaddwod_w_hu_h, ALL, gvec_vvv, MO_16, do_vaddwod_u_s)\n-TRANS(vaddwod_d_wu_w, ALL, gvec_vvv, MO_32, do_vaddwod_u_s)\n-TRANS(vaddwod_q_du_d, ALL, gvec_vvv, MO_64, do_vaddwod_u_s)\n+TRANS(vaddwod_h_bu_b, LSX, gvec_vvv, MO_8, do_vaddwod_u_s)\n+TRANS(vaddwod_w_hu_h, LSX, gvec_vvv, MO_16, do_vaddwod_u_s)\n+TRANS(vaddwod_d_wu_w, LSX, gvec_vvv, MO_32, do_vaddwod_u_s)\n+TRANS(vaddwod_q_du_d, LSX, gvec_vvv, MO_64, do_vaddwod_u_s)\n \n static void do_vavg(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b,\n void (*gen_shr_vec)(unsigned, TCGv_vec,\n@@ -1125,14 +1129,14 @@ static void do_vavg_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vavg_b, ALL, gvec_vvv, MO_8, do_vavg_s)\n-TRANS(vavg_h, ALL, gvec_vvv, MO_16, do_vavg_s)\n-TRANS(vavg_w, ALL, gvec_vvv, MO_32, do_vavg_s)\n-TRANS(vavg_d, ALL, gvec_vvv, MO_64, do_vavg_s)\n-TRANS(vavg_bu, ALL, gvec_vvv, MO_8, do_vavg_u)\n-TRANS(vavg_hu, ALL, gvec_vvv, MO_16, do_vavg_u)\n-TRANS(vavg_wu, ALL, gvec_vvv, MO_32, do_vavg_u)\n-TRANS(vavg_du, ALL, gvec_vvv, MO_64, do_vavg_u)\n+TRANS(vavg_b, LSX, gvec_vvv, MO_8, do_vavg_s)\n+TRANS(vavg_h, LSX, gvec_vvv, MO_16, do_vavg_s)\n+TRANS(vavg_w, LSX, gvec_vvv, MO_32, do_vavg_s)\n+TRANS(vavg_d, LSX, gvec_vvv, MO_64, do_vavg_s)\n+TRANS(vavg_bu, LSX, gvec_vvv, MO_8, do_vavg_u)\n+TRANS(vavg_hu, LSX, gvec_vvv, MO_16, do_vavg_u)\n+TRANS(vavg_wu, LSX, gvec_vvv, MO_32, do_vavg_u)\n+TRANS(vavg_du, LSX, gvec_vvv, MO_64, do_vavg_u)\n \n static void do_vavgr_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n uint32_t vk_ofs, uint32_t oprsz, uint32_t maxsz)\n@@ -1206,14 +1210,14 @@ static void do_vavgr_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vavgr_b, ALL, gvec_vvv, MO_8, do_vavgr_s)\n-TRANS(vavgr_h, ALL, gvec_vvv, MO_16, do_vavgr_s)\n-TRANS(vavgr_w, ALL, gvec_vvv, MO_32, do_vavgr_s)\n-TRANS(vavgr_d, ALL, gvec_vvv, MO_64, do_vavgr_s)\n-TRANS(vavgr_bu, ALL, gvec_vvv, MO_8, do_vavgr_u)\n-TRANS(vavgr_hu, ALL, gvec_vvv, MO_16, do_vavgr_u)\n-TRANS(vavgr_wu, ALL, gvec_vvv, MO_32, do_vavgr_u)\n-TRANS(vavgr_du, ALL, gvec_vvv, MO_64, do_vavgr_u)\n+TRANS(vavgr_b, LSX, gvec_vvv, MO_8, do_vavgr_s)\n+TRANS(vavgr_h, LSX, gvec_vvv, MO_16, do_vavgr_s)\n+TRANS(vavgr_w, LSX, gvec_vvv, MO_32, do_vavgr_s)\n+TRANS(vavgr_d, LSX, gvec_vvv, MO_64, do_vavgr_s)\n+TRANS(vavgr_bu, LSX, gvec_vvv, MO_8, do_vavgr_u)\n+TRANS(vavgr_hu, LSX, gvec_vvv, MO_16, do_vavgr_u)\n+TRANS(vavgr_wu, LSX, gvec_vvv, MO_32, do_vavgr_u)\n+TRANS(vavgr_du, LSX, gvec_vvv, MO_64, do_vavgr_u)\n \n static void gen_vabsd_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)\n {\n@@ -1301,14 +1305,14 @@ static void do_vabsd_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vabsd_b, ALL, gvec_vvv, MO_8, do_vabsd_s)\n-TRANS(vabsd_h, ALL, gvec_vvv, MO_16, do_vabsd_s)\n-TRANS(vabsd_w, ALL, gvec_vvv, MO_32, do_vabsd_s)\n-TRANS(vabsd_d, ALL, gvec_vvv, MO_64, do_vabsd_s)\n-TRANS(vabsd_bu, ALL, gvec_vvv, MO_8, do_vabsd_u)\n-TRANS(vabsd_hu, ALL, gvec_vvv, MO_16, do_vabsd_u)\n-TRANS(vabsd_wu, ALL, gvec_vvv, MO_32, do_vabsd_u)\n-TRANS(vabsd_du, ALL, gvec_vvv, MO_64, do_vabsd_u)\n+TRANS(vabsd_b, LSX, gvec_vvv, MO_8, do_vabsd_s)\n+TRANS(vabsd_h, LSX, gvec_vvv, MO_16, do_vabsd_s)\n+TRANS(vabsd_w, LSX, gvec_vvv, MO_32, do_vabsd_s)\n+TRANS(vabsd_d, LSX, gvec_vvv, MO_64, do_vabsd_s)\n+TRANS(vabsd_bu, LSX, gvec_vvv, MO_8, do_vabsd_u)\n+TRANS(vabsd_hu, LSX, gvec_vvv, MO_16, do_vabsd_u)\n+TRANS(vabsd_wu, LSX, gvec_vvv, MO_32, do_vabsd_u)\n+TRANS(vabsd_du, LSX, gvec_vvv, MO_64, do_vabsd_u)\n \n static void gen_vadda(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)\n {\n@@ -1358,28 +1362,28 @@ static void do_vadda(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vadda_b, ALL, gvec_vvv, MO_8, do_vadda)\n-TRANS(vadda_h, ALL, gvec_vvv, MO_16, do_vadda)\n-TRANS(vadda_w, ALL, gvec_vvv, MO_32, do_vadda)\n-TRANS(vadda_d, ALL, gvec_vvv, MO_64, do_vadda)\n-\n-TRANS(vmax_b, ALL, gvec_vvv, MO_8, tcg_gen_gvec_smax)\n-TRANS(vmax_h, ALL, gvec_vvv, MO_16, tcg_gen_gvec_smax)\n-TRANS(vmax_w, ALL, gvec_vvv, MO_32, tcg_gen_gvec_smax)\n-TRANS(vmax_d, ALL, gvec_vvv, MO_64, tcg_gen_gvec_smax)\n-TRANS(vmax_bu, ALL, gvec_vvv, MO_8, tcg_gen_gvec_umax)\n-TRANS(vmax_hu, ALL, gvec_vvv, MO_16, tcg_gen_gvec_umax)\n-TRANS(vmax_wu, ALL, gvec_vvv, MO_32, tcg_gen_gvec_umax)\n-TRANS(vmax_du, ALL, gvec_vvv, MO_64, tcg_gen_gvec_umax)\n-\n-TRANS(vmin_b, ALL, gvec_vvv, MO_8, tcg_gen_gvec_smin)\n-TRANS(vmin_h, ALL, gvec_vvv, MO_16, tcg_gen_gvec_smin)\n-TRANS(vmin_w, ALL, gvec_vvv, MO_32, tcg_gen_gvec_smin)\n-TRANS(vmin_d, ALL, gvec_vvv, MO_64, tcg_gen_gvec_smin)\n-TRANS(vmin_bu, ALL, gvec_vvv, MO_8, tcg_gen_gvec_umin)\n-TRANS(vmin_hu, ALL, gvec_vvv, MO_16, tcg_gen_gvec_umin)\n-TRANS(vmin_wu, ALL, gvec_vvv, MO_32, tcg_gen_gvec_umin)\n-TRANS(vmin_du, ALL, gvec_vvv, MO_64, tcg_gen_gvec_umin)\n+TRANS(vadda_b, LSX, gvec_vvv, MO_8, do_vadda)\n+TRANS(vadda_h, LSX, gvec_vvv, MO_16, do_vadda)\n+TRANS(vadda_w, LSX, gvec_vvv, MO_32, do_vadda)\n+TRANS(vadda_d, LSX, gvec_vvv, MO_64, do_vadda)\n+\n+TRANS(vmax_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_smax)\n+TRANS(vmax_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_smax)\n+TRANS(vmax_w, LSX, gvec_vvv, MO_32, tcg_gen_gvec_smax)\n+TRANS(vmax_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_smax)\n+TRANS(vmax_bu, LSX, gvec_vvv, MO_8, tcg_gen_gvec_umax)\n+TRANS(vmax_hu, LSX, gvec_vvv, MO_16, tcg_gen_gvec_umax)\n+TRANS(vmax_wu, LSX, gvec_vvv, MO_32, tcg_gen_gvec_umax)\n+TRANS(vmax_du, LSX, gvec_vvv, MO_64, tcg_gen_gvec_umax)\n+\n+TRANS(vmin_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_smin)\n+TRANS(vmin_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_smin)\n+TRANS(vmin_w, LSX, gvec_vvv, MO_32, tcg_gen_gvec_smin)\n+TRANS(vmin_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_smin)\n+TRANS(vmin_bu, LSX, gvec_vvv, MO_8, tcg_gen_gvec_umin)\n+TRANS(vmin_hu, LSX, gvec_vvv, MO_16, tcg_gen_gvec_umin)\n+TRANS(vmin_wu, LSX, gvec_vvv, MO_32, tcg_gen_gvec_umin)\n+TRANS(vmin_du, LSX, gvec_vvv, MO_64, tcg_gen_gvec_umin)\n \n static void gen_vmini_s(unsigned vece, TCGv_vec t, TCGv_vec a, int64_t imm)\n {\n@@ -1473,14 +1477,14 @@ static void do_vmini_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, imm, &op[vece]);\n }\n \n-TRANS(vmini_b, ALL, gvec_vv_i, MO_8, do_vmini_s)\n-TRANS(vmini_h, ALL, gvec_vv_i, MO_16, do_vmini_s)\n-TRANS(vmini_w, ALL, gvec_vv_i, MO_32, do_vmini_s)\n-TRANS(vmini_d, ALL, gvec_vv_i, MO_64, do_vmini_s)\n-TRANS(vmini_bu, ALL, gvec_vv_i, MO_8, do_vmini_u)\n-TRANS(vmini_hu, ALL, gvec_vv_i, MO_16, do_vmini_u)\n-TRANS(vmini_wu, ALL, gvec_vv_i, MO_32, do_vmini_u)\n-TRANS(vmini_du, ALL, gvec_vv_i, MO_64, do_vmini_u)\n+TRANS(vmini_b, LSX, gvec_vv_i, MO_8, do_vmini_s)\n+TRANS(vmini_h, LSX, gvec_vv_i, MO_16, do_vmini_s)\n+TRANS(vmini_w, LSX, gvec_vv_i, MO_32, do_vmini_s)\n+TRANS(vmini_d, LSX, gvec_vv_i, MO_64, do_vmini_s)\n+TRANS(vmini_bu, LSX, gvec_vv_i, MO_8, do_vmini_u)\n+TRANS(vmini_hu, LSX, gvec_vv_i, MO_16, do_vmini_u)\n+TRANS(vmini_wu, LSX, gvec_vv_i, MO_32, do_vmini_u)\n+TRANS(vmini_du, LSX, gvec_vv_i, MO_64, do_vmini_u)\n \n static void do_vmaxi_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n int64_t imm, uint32_t oprsz, uint32_t maxsz)\n@@ -1554,19 +1558,19 @@ static void do_vmaxi_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, imm, &op[vece]);\n }\n \n-TRANS(vmaxi_b, ALL, gvec_vv_i, MO_8, do_vmaxi_s)\n-TRANS(vmaxi_h, ALL, gvec_vv_i, MO_16, do_vmaxi_s)\n-TRANS(vmaxi_w, ALL, gvec_vv_i, MO_32, do_vmaxi_s)\n-TRANS(vmaxi_d, ALL, gvec_vv_i, MO_64, do_vmaxi_s)\n-TRANS(vmaxi_bu, ALL, gvec_vv_i, MO_8, do_vmaxi_u)\n-TRANS(vmaxi_hu, ALL, gvec_vv_i, MO_16, do_vmaxi_u)\n-TRANS(vmaxi_wu, ALL, gvec_vv_i, MO_32, do_vmaxi_u)\n-TRANS(vmaxi_du, ALL, gvec_vv_i, MO_64, do_vmaxi_u)\n+TRANS(vmaxi_b, LSX, gvec_vv_i, MO_8, do_vmaxi_s)\n+TRANS(vmaxi_h, LSX, gvec_vv_i, MO_16, do_vmaxi_s)\n+TRANS(vmaxi_w, LSX, gvec_vv_i, MO_32, do_vmaxi_s)\n+TRANS(vmaxi_d, LSX, gvec_vv_i, MO_64, do_vmaxi_s)\n+TRANS(vmaxi_bu, LSX, gvec_vv_i, MO_8, do_vmaxi_u)\n+TRANS(vmaxi_hu, LSX, gvec_vv_i, MO_16, do_vmaxi_u)\n+TRANS(vmaxi_wu, LSX, gvec_vv_i, MO_32, do_vmaxi_u)\n+TRANS(vmaxi_du, LSX, gvec_vv_i, MO_64, do_vmaxi_u)\n \n-TRANS(vmul_b, ALL, gvec_vvv, MO_8, tcg_gen_gvec_mul)\n-TRANS(vmul_h, ALL, gvec_vvv, MO_16, tcg_gen_gvec_mul)\n-TRANS(vmul_w, ALL, gvec_vvv, MO_32, tcg_gen_gvec_mul)\n-TRANS(vmul_d, ALL, gvec_vvv, MO_64, tcg_gen_gvec_mul)\n+TRANS(vmul_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_mul)\n+TRANS(vmul_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_mul)\n+TRANS(vmul_w, LSX, gvec_vvv, MO_32, tcg_gen_gvec_mul)\n+TRANS(vmul_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_mul)\n \n static void gen_vmuh_w(TCGv_i32 t, TCGv_i32 a, TCGv_i32 b)\n {\n@@ -1607,10 +1611,10 @@ static void do_vmuh_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vmuh_b, ALL, gvec_vvv, MO_8, do_vmuh_s)\n-TRANS(vmuh_h, ALL, gvec_vvv, MO_16, do_vmuh_s)\n-TRANS(vmuh_w, ALL, gvec_vvv, MO_32, do_vmuh_s)\n-TRANS(vmuh_d, ALL, gvec_vvv, MO_64, do_vmuh_s)\n+TRANS(vmuh_b, LSX, gvec_vvv, MO_8, do_vmuh_s)\n+TRANS(vmuh_h, LSX, gvec_vvv, MO_16, do_vmuh_s)\n+TRANS(vmuh_w, LSX, gvec_vvv, MO_32, do_vmuh_s)\n+TRANS(vmuh_d, LSX, gvec_vvv, MO_64, do_vmuh_s)\n \n static void gen_vmuh_wu(TCGv_i32 t, TCGv_i32 a, TCGv_i32 b)\n {\n@@ -1651,10 +1655,10 @@ static void do_vmuh_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vmuh_bu, ALL, gvec_vvv, MO_8, do_vmuh_u)\n-TRANS(vmuh_hu, ALL, gvec_vvv, MO_16, do_vmuh_u)\n-TRANS(vmuh_wu, ALL, gvec_vvv, MO_32, do_vmuh_u)\n-TRANS(vmuh_du, ALL, gvec_vvv, MO_64, do_vmuh_u)\n+TRANS(vmuh_bu, LSX, gvec_vvv, MO_8, do_vmuh_u)\n+TRANS(vmuh_hu, LSX, gvec_vvv, MO_16, do_vmuh_u)\n+TRANS(vmuh_wu, LSX, gvec_vvv, MO_32, do_vmuh_u)\n+TRANS(vmuh_du, LSX, gvec_vvv, MO_64, do_vmuh_u)\n \n static void gen_vmulwev_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)\n {\n@@ -1724,9 +1728,9 @@ static void do_vmulwev_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vmulwev_h_b, ALL, gvec_vvv, MO_8, do_vmulwev_s)\n-TRANS(vmulwev_w_h, ALL, gvec_vvv, MO_16, do_vmulwev_s)\n-TRANS(vmulwev_d_w, ALL, gvec_vvv, MO_32, do_vmulwev_s)\n+TRANS(vmulwev_h_b, LSX, gvec_vvv, MO_8, do_vmulwev_s)\n+TRANS(vmulwev_w_h, LSX, gvec_vvv, MO_16, do_vmulwev_s)\n+TRANS(vmulwev_d_w, LSX, gvec_vvv, MO_32, do_vmulwev_s)\n \n static void tcg_gen_mulus2_i64(TCGv_i64 rl, TCGv_i64 rh,\n TCGv_i64 arg1, TCGv_i64 arg2)\n@@ -1739,6 +1743,10 @@ static bool trans_## NAME (DisasContext *ctx, arg_vvv *a) \\\n { \\\n TCGv_i64 rh, rl, arg1, arg2; \\\n \\\n+ if (!avail_LSX(ctx)) { \\\n+ return false; \\\n+ } \\\n+ \\\n rh = tcg_temp_new_i64(); \\\n rl = tcg_temp_new_i64(); \\\n arg1 = tcg_temp_new_i64(); \\\n@@ -1828,9 +1836,9 @@ static void do_vmulwod_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vmulwod_h_b, ALL, gvec_vvv, MO_8, do_vmulwod_s)\n-TRANS(vmulwod_w_h, ALL, gvec_vvv, MO_16, do_vmulwod_s)\n-TRANS(vmulwod_d_w, ALL, gvec_vvv, MO_32, do_vmulwod_s)\n+TRANS(vmulwod_h_b, LSX, gvec_vvv, MO_8, do_vmulwod_s)\n+TRANS(vmulwod_w_h, LSX, gvec_vvv, MO_16, do_vmulwod_s)\n+TRANS(vmulwod_d_w, LSX, gvec_vvv, MO_32, do_vmulwod_s)\n \n static void gen_vmulwev_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)\n {\n@@ -1898,9 +1906,9 @@ static void do_vmulwev_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vmulwev_h_bu, ALL, gvec_vvv, MO_8, do_vmulwev_u)\n-TRANS(vmulwev_w_hu, ALL, gvec_vvv, MO_16, do_vmulwev_u)\n-TRANS(vmulwev_d_wu, ALL, gvec_vvv, MO_32, do_vmulwev_u)\n+TRANS(vmulwev_h_bu, LSX, gvec_vvv, MO_8, do_vmulwev_u)\n+TRANS(vmulwev_w_hu, LSX, gvec_vvv, MO_16, do_vmulwev_u)\n+TRANS(vmulwev_d_wu, LSX, gvec_vvv, MO_32, do_vmulwev_u)\n \n static void gen_vmulwod_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)\n {\n@@ -1968,9 +1976,9 @@ static void do_vmulwod_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vmulwod_h_bu, ALL, gvec_vvv, MO_8, do_vmulwod_u)\n-TRANS(vmulwod_w_hu, ALL, gvec_vvv, MO_16, do_vmulwod_u)\n-TRANS(vmulwod_d_wu, ALL, gvec_vvv, MO_32, do_vmulwod_u)\n+TRANS(vmulwod_h_bu, LSX, gvec_vvv, MO_8, do_vmulwod_u)\n+TRANS(vmulwod_w_hu, LSX, gvec_vvv, MO_16, do_vmulwod_u)\n+TRANS(vmulwod_d_wu, LSX, gvec_vvv, MO_32, do_vmulwod_u)\n \n static void gen_vmulwev_u_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)\n {\n@@ -2040,9 +2048,9 @@ static void do_vmulwev_u_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vmulwev_h_bu_b, ALL, gvec_vvv, MO_8, do_vmulwev_u_s)\n-TRANS(vmulwev_w_hu_h, ALL, gvec_vvv, MO_16, do_vmulwev_u_s)\n-TRANS(vmulwev_d_wu_w, ALL, gvec_vvv, MO_32, do_vmulwev_u_s)\n+TRANS(vmulwev_h_bu_b, LSX, gvec_vvv, MO_8, do_vmulwev_u_s)\n+TRANS(vmulwev_w_hu_h, LSX, gvec_vvv, MO_16, do_vmulwev_u_s)\n+TRANS(vmulwev_d_wu_w, LSX, gvec_vvv, MO_32, do_vmulwev_u_s)\n \n static void gen_vmulwod_u_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)\n {\n@@ -2109,9 +2117,9 @@ static void do_vmulwod_u_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vmulwod_h_bu_b, ALL, gvec_vvv, MO_8, do_vmulwod_u_s)\n-TRANS(vmulwod_w_hu_h, ALL, gvec_vvv, MO_16, do_vmulwod_u_s)\n-TRANS(vmulwod_d_wu_w, ALL, gvec_vvv, MO_32, do_vmulwod_u_s)\n+TRANS(vmulwod_h_bu_b, LSX, gvec_vvv, MO_8, do_vmulwod_u_s)\n+TRANS(vmulwod_w_hu_h, LSX, gvec_vvv, MO_16, do_vmulwod_u_s)\n+TRANS(vmulwod_d_wu_w, LSX, gvec_vvv, MO_32, do_vmulwod_u_s)\n \n static void gen_vmadd(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)\n {\n@@ -2182,10 +2190,10 @@ static void do_vmadd(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vmadd_b, ALL, gvec_vvv, MO_8, do_vmadd)\n-TRANS(vmadd_h, ALL, gvec_vvv, MO_16, do_vmadd)\n-TRANS(vmadd_w, ALL, gvec_vvv, MO_32, do_vmadd)\n-TRANS(vmadd_d, ALL, gvec_vvv, MO_64, do_vmadd)\n+TRANS(vmadd_b, LSX, gvec_vvv, MO_8, do_vmadd)\n+TRANS(vmadd_h, LSX, gvec_vvv, MO_16, do_vmadd)\n+TRANS(vmadd_w, LSX, gvec_vvv, MO_32, do_vmadd)\n+TRANS(vmadd_d, LSX, gvec_vvv, MO_64, do_vmadd)\n \n static void gen_vmsub(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)\n {\n@@ -2256,10 +2264,10 @@ static void do_vmsub(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vmsub_b, ALL, gvec_vvv, MO_8, do_vmsub)\n-TRANS(vmsub_h, ALL, gvec_vvv, MO_16, do_vmsub)\n-TRANS(vmsub_w, ALL, gvec_vvv, MO_32, do_vmsub)\n-TRANS(vmsub_d, ALL, gvec_vvv, MO_64, do_vmsub)\n+TRANS(vmsub_b, LSX, gvec_vvv, MO_8, do_vmsub)\n+TRANS(vmsub_h, LSX, gvec_vvv, MO_16, do_vmsub)\n+TRANS(vmsub_w, LSX, gvec_vvv, MO_32, do_vmsub)\n+TRANS(vmsub_d, LSX, gvec_vvv, MO_64, do_vmsub)\n \n static void gen_vmaddwev_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)\n {\n@@ -2331,15 +2339,19 @@ static void do_vmaddwev_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vmaddwev_h_b, ALL, gvec_vvv, MO_8, do_vmaddwev_s)\n-TRANS(vmaddwev_w_h, ALL, gvec_vvv, MO_16, do_vmaddwev_s)\n-TRANS(vmaddwev_d_w, ALL, gvec_vvv, MO_32, do_vmaddwev_s)\n+TRANS(vmaddwev_h_b, LSX, gvec_vvv, MO_8, do_vmaddwev_s)\n+TRANS(vmaddwev_w_h, LSX, gvec_vvv, MO_16, do_vmaddwev_s)\n+TRANS(vmaddwev_d_w, LSX, gvec_vvv, MO_32, do_vmaddwev_s)\n \n #define VMADD_Q(NAME, FN, idx1, idx2) \\\n static bool trans_## NAME (DisasContext *ctx, arg_vvv *a) \\\n { \\\n TCGv_i64 rh, rl, arg1, arg2, th, tl; \\\n \\\n+ if (!avail_LSX(ctx)) { \\\n+ return false; \\\n+ } \\\n+ \\\n rh = tcg_temp_new_i64(); \\\n rl = tcg_temp_new_i64(); \\\n arg1 = tcg_temp_new_i64(); \\\n@@ -2435,9 +2447,9 @@ static void do_vmaddwod_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vmaddwod_h_b, ALL, gvec_vvv, MO_8, do_vmaddwod_s)\n-TRANS(vmaddwod_w_h, ALL, gvec_vvv, MO_16, do_vmaddwod_s)\n-TRANS(vmaddwod_d_w, ALL, gvec_vvv, MO_32, do_vmaddwod_s)\n+TRANS(vmaddwod_h_b, LSX, gvec_vvv, MO_8, do_vmaddwod_s)\n+TRANS(vmaddwod_w_h, LSX, gvec_vvv, MO_16, do_vmaddwod_s)\n+TRANS(vmaddwod_d_w, LSX, gvec_vvv, MO_32, do_vmaddwod_s)\n \n static void gen_vmaddwev_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)\n {\n@@ -2505,9 +2517,9 @@ static void do_vmaddwev_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vmaddwev_h_bu, ALL, gvec_vvv, MO_8, do_vmaddwev_u)\n-TRANS(vmaddwev_w_hu, ALL, gvec_vvv, MO_16, do_vmaddwev_u)\n-TRANS(vmaddwev_d_wu, ALL, gvec_vvv, MO_32, do_vmaddwev_u)\n+TRANS(vmaddwev_h_bu, LSX, gvec_vvv, MO_8, do_vmaddwev_u)\n+TRANS(vmaddwev_w_hu, LSX, gvec_vvv, MO_16, do_vmaddwev_u)\n+TRANS(vmaddwev_d_wu, LSX, gvec_vvv, MO_32, do_vmaddwev_u)\n \n static void gen_vmaddwod_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)\n {\n@@ -2576,9 +2588,9 @@ static void do_vmaddwod_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vmaddwod_h_bu, ALL, gvec_vvv, MO_8, do_vmaddwod_u)\n-TRANS(vmaddwod_w_hu, ALL, gvec_vvv, MO_16, do_vmaddwod_u)\n-TRANS(vmaddwod_d_wu, ALL, gvec_vvv, MO_32, do_vmaddwod_u)\n+TRANS(vmaddwod_h_bu, LSX, gvec_vvv, MO_8, do_vmaddwod_u)\n+TRANS(vmaddwod_w_hu, LSX, gvec_vvv, MO_16, do_vmaddwod_u)\n+TRANS(vmaddwod_d_wu, LSX, gvec_vvv, MO_32, do_vmaddwod_u)\n \n static void gen_vmaddwev_u_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)\n {\n@@ -2649,9 +2661,9 @@ static void do_vmaddwev_u_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vmaddwev_h_bu_b, ALL, gvec_vvv, MO_8, do_vmaddwev_u_s)\n-TRANS(vmaddwev_w_hu_h, ALL, gvec_vvv, MO_16, do_vmaddwev_u_s)\n-TRANS(vmaddwev_d_wu_w, ALL, gvec_vvv, MO_32, do_vmaddwev_u_s)\n+TRANS(vmaddwev_h_bu_b, LSX, gvec_vvv, MO_8, do_vmaddwev_u_s)\n+TRANS(vmaddwev_w_hu_h, LSX, gvec_vvv, MO_16, do_vmaddwev_u_s)\n+TRANS(vmaddwev_d_wu_w, LSX, gvec_vvv, MO_32, do_vmaddwev_u_s)\n \n static void gen_vmaddwod_u_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)\n {\n@@ -2721,26 +2733,26 @@ static void do_vmaddwod_u_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vmaddwod_h_bu_b, ALL, gvec_vvv, MO_8, do_vmaddwod_u_s)\n-TRANS(vmaddwod_w_hu_h, ALL, gvec_vvv, MO_16, do_vmaddwod_u_s)\n-TRANS(vmaddwod_d_wu_w, ALL, gvec_vvv, MO_32, do_vmaddwod_u_s)\n-\n-TRANS(vdiv_b, ALL, gen_vvv, gen_helper_vdiv_b)\n-TRANS(vdiv_h, ALL, gen_vvv, gen_helper_vdiv_h)\n-TRANS(vdiv_w, ALL, gen_vvv, gen_helper_vdiv_w)\n-TRANS(vdiv_d, ALL, gen_vvv, gen_helper_vdiv_d)\n-TRANS(vdiv_bu, ALL, gen_vvv, gen_helper_vdiv_bu)\n-TRANS(vdiv_hu, ALL, gen_vvv, gen_helper_vdiv_hu)\n-TRANS(vdiv_wu, ALL, gen_vvv, gen_helper_vdiv_wu)\n-TRANS(vdiv_du, ALL, gen_vvv, gen_helper_vdiv_du)\n-TRANS(vmod_b, ALL, gen_vvv, gen_helper_vmod_b)\n-TRANS(vmod_h, ALL, gen_vvv, gen_helper_vmod_h)\n-TRANS(vmod_w, ALL, gen_vvv, gen_helper_vmod_w)\n-TRANS(vmod_d, ALL, gen_vvv, gen_helper_vmod_d)\n-TRANS(vmod_bu, ALL, gen_vvv, gen_helper_vmod_bu)\n-TRANS(vmod_hu, ALL, gen_vvv, gen_helper_vmod_hu)\n-TRANS(vmod_wu, ALL, gen_vvv, gen_helper_vmod_wu)\n-TRANS(vmod_du, ALL, gen_vvv, gen_helper_vmod_du)\n+TRANS(vmaddwod_h_bu_b, LSX, gvec_vvv, MO_8, do_vmaddwod_u_s)\n+TRANS(vmaddwod_w_hu_h, LSX, gvec_vvv, MO_16, do_vmaddwod_u_s)\n+TRANS(vmaddwod_d_wu_w, LSX, gvec_vvv, MO_32, do_vmaddwod_u_s)\n+\n+TRANS(vdiv_b, LSX, gen_vvv, gen_helper_vdiv_b)\n+TRANS(vdiv_h, LSX, gen_vvv, gen_helper_vdiv_h)\n+TRANS(vdiv_w, LSX, gen_vvv, gen_helper_vdiv_w)\n+TRANS(vdiv_d, LSX, gen_vvv, gen_helper_vdiv_d)\n+TRANS(vdiv_bu, LSX, gen_vvv, gen_helper_vdiv_bu)\n+TRANS(vdiv_hu, LSX, gen_vvv, gen_helper_vdiv_hu)\n+TRANS(vdiv_wu, LSX, gen_vvv, gen_helper_vdiv_wu)\n+TRANS(vdiv_du, LSX, gen_vvv, gen_helper_vdiv_du)\n+TRANS(vmod_b, LSX, gen_vvv, gen_helper_vmod_b)\n+TRANS(vmod_h, LSX, gen_vvv, gen_helper_vmod_h)\n+TRANS(vmod_w, LSX, gen_vvv, gen_helper_vmod_w)\n+TRANS(vmod_d, LSX, gen_vvv, gen_helper_vmod_d)\n+TRANS(vmod_bu, LSX, gen_vvv, gen_helper_vmod_bu)\n+TRANS(vmod_hu, LSX, gen_vvv, gen_helper_vmod_hu)\n+TRANS(vmod_wu, LSX, gen_vvv, gen_helper_vmod_wu)\n+TRANS(vmod_du, LSX, gen_vvv, gen_helper_vmod_du)\n \n static void gen_vsat_s(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec max)\n {\n@@ -2789,10 +2801,10 @@ static void do_vsat_s(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_constant_i64((1ll<< imm) -1), &op[vece]);\n }\n \n-TRANS(vsat_b, ALL, gvec_vv_i, MO_8, do_vsat_s)\n-TRANS(vsat_h, ALL, gvec_vv_i, MO_16, do_vsat_s)\n-TRANS(vsat_w, ALL, gvec_vv_i, MO_32, do_vsat_s)\n-TRANS(vsat_d, ALL, gvec_vv_i, MO_64, do_vsat_s)\n+TRANS(vsat_b, LSX, gvec_vv_i, MO_8, do_vsat_s)\n+TRANS(vsat_h, LSX, gvec_vv_i, MO_16, do_vsat_s)\n+TRANS(vsat_w, LSX, gvec_vv_i, MO_32, do_vsat_s)\n+TRANS(vsat_d, LSX, gvec_vv_i, MO_64, do_vsat_s)\n \n static void gen_vsat_u(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec max)\n {\n@@ -2838,19 +2850,19 @@ static void do_vsat_u(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_constant_i64(max), &op[vece]);\n }\n \n-TRANS(vsat_bu, ALL, gvec_vv_i, MO_8, do_vsat_u)\n-TRANS(vsat_hu, ALL, gvec_vv_i, MO_16, do_vsat_u)\n-TRANS(vsat_wu, ALL, gvec_vv_i, MO_32, do_vsat_u)\n-TRANS(vsat_du, ALL, gvec_vv_i, MO_64, do_vsat_u)\n+TRANS(vsat_bu, LSX, gvec_vv_i, MO_8, do_vsat_u)\n+TRANS(vsat_hu, LSX, gvec_vv_i, MO_16, do_vsat_u)\n+TRANS(vsat_wu, LSX, gvec_vv_i, MO_32, do_vsat_u)\n+TRANS(vsat_du, LSX, gvec_vv_i, MO_64, do_vsat_u)\n \n-TRANS(vexth_h_b, ALL, gen_vv, gen_helper_vexth_h_b)\n-TRANS(vexth_w_h, ALL, gen_vv, gen_helper_vexth_w_h)\n-TRANS(vexth_d_w, ALL, gen_vv, gen_helper_vexth_d_w)\n-TRANS(vexth_q_d, ALL, gen_vv, gen_helper_vexth_q_d)\n-TRANS(vexth_hu_bu, ALL, gen_vv, gen_helper_vexth_hu_bu)\n-TRANS(vexth_wu_hu, ALL, gen_vv, gen_helper_vexth_wu_hu)\n-TRANS(vexth_du_wu, ALL, gen_vv, gen_helper_vexth_du_wu)\n-TRANS(vexth_qu_du, ALL, gen_vv, gen_helper_vexth_qu_du)\n+TRANS(vexth_h_b, LSX, gen_vv, gen_helper_vexth_h_b)\n+TRANS(vexth_w_h, LSX, gen_vv, gen_helper_vexth_w_h)\n+TRANS(vexth_d_w, LSX, gen_vv, gen_helper_vexth_d_w)\n+TRANS(vexth_q_d, LSX, gen_vv, gen_helper_vexth_q_d)\n+TRANS(vexth_hu_bu, LSX, gen_vv, gen_helper_vexth_hu_bu)\n+TRANS(vexth_wu_hu, LSX, gen_vv, gen_helper_vexth_wu_hu)\n+TRANS(vexth_du_wu, LSX, gen_vv, gen_helper_vexth_du_wu)\n+TRANS(vexth_qu_du, LSX, gen_vv, gen_helper_vexth_qu_du)\n \n static void gen_vsigncov(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b)\n {\n@@ -2900,17 +2912,17 @@ static void do_vsigncov(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vsigncov_b, ALL, gvec_vvv, MO_8, do_vsigncov)\n-TRANS(vsigncov_h, ALL, gvec_vvv, MO_16, do_vsigncov)\n-TRANS(vsigncov_w, ALL, gvec_vvv, MO_32, do_vsigncov)\n-TRANS(vsigncov_d, ALL, gvec_vvv, MO_64, do_vsigncov)\n+TRANS(vsigncov_b, LSX, gvec_vvv, MO_8, do_vsigncov)\n+TRANS(vsigncov_h, LSX, gvec_vvv, MO_16, do_vsigncov)\n+TRANS(vsigncov_w, LSX, gvec_vvv, MO_32, do_vsigncov)\n+TRANS(vsigncov_d, LSX, gvec_vvv, MO_64, do_vsigncov)\n \n-TRANS(vmskltz_b, ALL, gen_vv, gen_helper_vmskltz_b)\n-TRANS(vmskltz_h, ALL, gen_vv, gen_helper_vmskltz_h)\n-TRANS(vmskltz_w, ALL, gen_vv, gen_helper_vmskltz_w)\n-TRANS(vmskltz_d, ALL, gen_vv, gen_helper_vmskltz_d)\n-TRANS(vmskgez_b, ALL, gen_vv, gen_helper_vmskgez_b)\n-TRANS(vmsknz_b, ALL, gen_vv, gen_helper_vmsknz_b)\n+TRANS(vmskltz_b, LSX, gen_vv, gen_helper_vmskltz_b)\n+TRANS(vmskltz_h, LSX, gen_vv, gen_helper_vmskltz_h)\n+TRANS(vmskltz_w, LSX, gen_vv, gen_helper_vmskltz_w)\n+TRANS(vmskltz_d, LSX, gen_vv, gen_helper_vmskltz_d)\n+TRANS(vmskgez_b, LSX, gen_vv, gen_helper_vmskgez_b)\n+TRANS(vmsknz_b, LSX, gen_vv, gen_helper_vmsknz_b)\n \n #define EXPAND_BYTE(bit) ((uint64_t)(bit ? 0xff : 0))\n \n@@ -3032,6 +3044,11 @@ static bool trans_vldi(DisasContext *ctx, arg_vldi *a)\n {\n int sel, vece;\n uint64_t value;\n+\n+ if (!avail_LSX(ctx)) {\n+ return false;\n+ }\n+\n CHECK_SXE;\n \n sel = (a->imm >> 12) & 0x1;\n@@ -3049,15 +3066,19 @@ static bool trans_vldi(DisasContext *ctx, arg_vldi *a)\n return true;\n }\n \n-TRANS(vand_v, ALL, gvec_vvv, MO_64, tcg_gen_gvec_and)\n-TRANS(vor_v, ALL, gvec_vvv, MO_64, tcg_gen_gvec_or)\n-TRANS(vxor_v, ALL, gvec_vvv, MO_64, tcg_gen_gvec_xor)\n-TRANS(vnor_v, ALL, gvec_vvv, MO_64, tcg_gen_gvec_nor)\n+TRANS(vand_v, LSX, gvec_vvv, MO_64, tcg_gen_gvec_and)\n+TRANS(vor_v, LSX, gvec_vvv, MO_64, tcg_gen_gvec_or)\n+TRANS(vxor_v, LSX, gvec_vvv, MO_64, tcg_gen_gvec_xor)\n+TRANS(vnor_v, LSX, gvec_vvv, MO_64, tcg_gen_gvec_nor)\n \n static bool trans_vandn_v(DisasContext *ctx, arg_vvv *a)\n {\n uint32_t vd_ofs, vj_ofs, vk_ofs;\n \n+ if (!avail_LSX(ctx)) {\n+ return false;\n+ }\n+\n CHECK_SXE;\n \n vd_ofs = vec_full_offset(a->vd);\n@@ -3067,10 +3088,10 @@ static bool trans_vandn_v(DisasContext *ctx, arg_vvv *a)\n tcg_gen_gvec_andc(MO_64, vd_ofs, vk_ofs, vj_ofs, 16, ctx->vl/8);\n return true;\n }\n-TRANS(vorn_v, ALL, gvec_vvv, MO_64, tcg_gen_gvec_orc)\n-TRANS(vandi_b, ALL, gvec_vv_i, MO_8, tcg_gen_gvec_andi)\n-TRANS(vori_b, ALL, gvec_vv_i, MO_8, tcg_gen_gvec_ori)\n-TRANS(vxori_b, ALL, gvec_vv_i, MO_8, tcg_gen_gvec_xori)\n+TRANS(vorn_v, LSX, gvec_vvv, MO_64, tcg_gen_gvec_orc)\n+TRANS(vandi_b, LSX, gvec_vv_i, MO_8, tcg_gen_gvec_andi)\n+TRANS(vori_b, LSX, gvec_vv_i, MO_8, tcg_gen_gvec_ori)\n+TRANS(vxori_b, LSX, gvec_vv_i, MO_8, tcg_gen_gvec_xori)\n \n static void gen_vnori(unsigned vece, TCGv_vec t, TCGv_vec a, int64_t imm)\n {\n@@ -3103,176 +3124,176 @@ static void do_vnori_b(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, imm, &op);\n }\n \n-TRANS(vnori_b, ALL, gvec_vv_i, MO_8, do_vnori_b)\n-\n-TRANS(vsll_b, ALL, gvec_vvv, MO_8, tcg_gen_gvec_shlv)\n-TRANS(vsll_h, ALL, gvec_vvv, MO_16, tcg_gen_gvec_shlv)\n-TRANS(vsll_w, ALL, gvec_vvv, MO_32, tcg_gen_gvec_shlv)\n-TRANS(vsll_d, ALL, gvec_vvv, MO_64, tcg_gen_gvec_shlv)\n-TRANS(vslli_b, ALL, gvec_vv_i, MO_8, tcg_gen_gvec_shli)\n-TRANS(vslli_h, ALL, gvec_vv_i, MO_16, tcg_gen_gvec_shli)\n-TRANS(vslli_w, ALL, gvec_vv_i, MO_32, tcg_gen_gvec_shli)\n-TRANS(vslli_d, ALL, gvec_vv_i, MO_64, tcg_gen_gvec_shli)\n-\n-TRANS(vsrl_b, ALL, gvec_vvv, MO_8, tcg_gen_gvec_shrv)\n-TRANS(vsrl_h, ALL, gvec_vvv, MO_16, tcg_gen_gvec_shrv)\n-TRANS(vsrl_w, ALL, gvec_vvv, MO_32, tcg_gen_gvec_shrv)\n-TRANS(vsrl_d, ALL, gvec_vvv, MO_64, tcg_gen_gvec_shrv)\n-TRANS(vsrli_b, ALL, gvec_vv_i, MO_8, tcg_gen_gvec_shri)\n-TRANS(vsrli_h, ALL, gvec_vv_i, MO_16, tcg_gen_gvec_shri)\n-TRANS(vsrli_w, ALL, gvec_vv_i, MO_32, tcg_gen_gvec_shri)\n-TRANS(vsrli_d, ALL, gvec_vv_i, MO_64, tcg_gen_gvec_shri)\n-\n-TRANS(vsra_b, ALL, gvec_vvv, MO_8, tcg_gen_gvec_sarv)\n-TRANS(vsra_h, ALL, gvec_vvv, MO_16, tcg_gen_gvec_sarv)\n-TRANS(vsra_w, ALL, gvec_vvv, MO_32, tcg_gen_gvec_sarv)\n-TRANS(vsra_d, ALL, gvec_vvv, MO_64, tcg_gen_gvec_sarv)\n-TRANS(vsrai_b, ALL, gvec_vv_i, MO_8, tcg_gen_gvec_sari)\n-TRANS(vsrai_h, ALL, gvec_vv_i, MO_16, tcg_gen_gvec_sari)\n-TRANS(vsrai_w, ALL, gvec_vv_i, MO_32, tcg_gen_gvec_sari)\n-TRANS(vsrai_d, ALL, gvec_vv_i, MO_64, tcg_gen_gvec_sari)\n-\n-TRANS(vrotr_b, ALL, gvec_vvv, MO_8, tcg_gen_gvec_rotrv)\n-TRANS(vrotr_h, ALL, gvec_vvv, MO_16, tcg_gen_gvec_rotrv)\n-TRANS(vrotr_w, ALL, gvec_vvv, MO_32, tcg_gen_gvec_rotrv)\n-TRANS(vrotr_d, ALL, gvec_vvv, MO_64, tcg_gen_gvec_rotrv)\n-TRANS(vrotri_b, ALL, gvec_vv_i, MO_8, tcg_gen_gvec_rotri)\n-TRANS(vrotri_h, ALL, gvec_vv_i, MO_16, tcg_gen_gvec_rotri)\n-TRANS(vrotri_w, ALL, gvec_vv_i, MO_32, tcg_gen_gvec_rotri)\n-TRANS(vrotri_d, ALL, gvec_vv_i, MO_64, tcg_gen_gvec_rotri)\n-\n-TRANS(vsllwil_h_b, ALL, gen_vv_i, gen_helper_vsllwil_h_b)\n-TRANS(vsllwil_w_h, ALL, gen_vv_i, gen_helper_vsllwil_w_h)\n-TRANS(vsllwil_d_w, ALL, gen_vv_i, gen_helper_vsllwil_d_w)\n-TRANS(vextl_q_d, ALL, gen_vv, gen_helper_vextl_q_d)\n-TRANS(vsllwil_hu_bu, ALL, gen_vv_i, gen_helper_vsllwil_hu_bu)\n-TRANS(vsllwil_wu_hu, ALL, gen_vv_i, gen_helper_vsllwil_wu_hu)\n-TRANS(vsllwil_du_wu, ALL, gen_vv_i, gen_helper_vsllwil_du_wu)\n-TRANS(vextl_qu_du, ALL, gen_vv, gen_helper_vextl_qu_du)\n-\n-TRANS(vsrlr_b, ALL, gen_vvv, gen_helper_vsrlr_b)\n-TRANS(vsrlr_h, ALL, gen_vvv, gen_helper_vsrlr_h)\n-TRANS(vsrlr_w, ALL, gen_vvv, gen_helper_vsrlr_w)\n-TRANS(vsrlr_d, ALL, gen_vvv, gen_helper_vsrlr_d)\n-TRANS(vsrlri_b, ALL, gen_vv_i, gen_helper_vsrlri_b)\n-TRANS(vsrlri_h, ALL, gen_vv_i, gen_helper_vsrlri_h)\n-TRANS(vsrlri_w, ALL, gen_vv_i, gen_helper_vsrlri_w)\n-TRANS(vsrlri_d, ALL, gen_vv_i, gen_helper_vsrlri_d)\n-\n-TRANS(vsrar_b, ALL, gen_vvv, gen_helper_vsrar_b)\n-TRANS(vsrar_h, ALL, gen_vvv, gen_helper_vsrar_h)\n-TRANS(vsrar_w, ALL, gen_vvv, gen_helper_vsrar_w)\n-TRANS(vsrar_d, ALL, gen_vvv, gen_helper_vsrar_d)\n-TRANS(vsrari_b, ALL, gen_vv_i, gen_helper_vsrari_b)\n-TRANS(vsrari_h, ALL, gen_vv_i, gen_helper_vsrari_h)\n-TRANS(vsrari_w, ALL, gen_vv_i, gen_helper_vsrari_w)\n-TRANS(vsrari_d, ALL, gen_vv_i, gen_helper_vsrari_d)\n-\n-TRANS(vsrln_b_h, ALL, gen_vvv, gen_helper_vsrln_b_h)\n-TRANS(vsrln_h_w, ALL, gen_vvv, gen_helper_vsrln_h_w)\n-TRANS(vsrln_w_d, ALL, gen_vvv, gen_helper_vsrln_w_d)\n-TRANS(vsran_b_h, ALL, gen_vvv, gen_helper_vsran_b_h)\n-TRANS(vsran_h_w, ALL, gen_vvv, gen_helper_vsran_h_w)\n-TRANS(vsran_w_d, ALL, gen_vvv, gen_helper_vsran_w_d)\n-\n-TRANS(vsrlni_b_h, ALL, gen_vv_i, gen_helper_vsrlni_b_h)\n-TRANS(vsrlni_h_w, ALL, gen_vv_i, gen_helper_vsrlni_h_w)\n-TRANS(vsrlni_w_d, ALL, gen_vv_i, gen_helper_vsrlni_w_d)\n-TRANS(vsrlni_d_q, ALL, gen_vv_i, gen_helper_vsrlni_d_q)\n-TRANS(vsrani_b_h, ALL, gen_vv_i, gen_helper_vsrani_b_h)\n-TRANS(vsrani_h_w, ALL, gen_vv_i, gen_helper_vsrani_h_w)\n-TRANS(vsrani_w_d, ALL, gen_vv_i, gen_helper_vsrani_w_d)\n-TRANS(vsrani_d_q, ALL, gen_vv_i, gen_helper_vsrani_d_q)\n-\n-TRANS(vsrlrn_b_h, ALL, gen_vvv, gen_helper_vsrlrn_b_h)\n-TRANS(vsrlrn_h_w, ALL, gen_vvv, gen_helper_vsrlrn_h_w)\n-TRANS(vsrlrn_w_d, ALL, gen_vvv, gen_helper_vsrlrn_w_d)\n-TRANS(vsrarn_b_h, ALL, gen_vvv, gen_helper_vsrarn_b_h)\n-TRANS(vsrarn_h_w, ALL, gen_vvv, gen_helper_vsrarn_h_w)\n-TRANS(vsrarn_w_d, ALL, gen_vvv, gen_helper_vsrarn_w_d)\n-\n-TRANS(vsrlrni_b_h, ALL, gen_vv_i, gen_helper_vsrlrni_b_h)\n-TRANS(vsrlrni_h_w, ALL, gen_vv_i, gen_helper_vsrlrni_h_w)\n-TRANS(vsrlrni_w_d, ALL, gen_vv_i, gen_helper_vsrlrni_w_d)\n-TRANS(vsrlrni_d_q, ALL, gen_vv_i, gen_helper_vsrlrni_d_q)\n-TRANS(vsrarni_b_h, ALL, gen_vv_i, gen_helper_vsrarni_b_h)\n-TRANS(vsrarni_h_w, ALL, gen_vv_i, gen_helper_vsrarni_h_w)\n-TRANS(vsrarni_w_d, ALL, gen_vv_i, gen_helper_vsrarni_w_d)\n-TRANS(vsrarni_d_q, ALL, gen_vv_i, gen_helper_vsrarni_d_q)\n-\n-TRANS(vssrln_b_h, ALL, gen_vvv, gen_helper_vssrln_b_h)\n-TRANS(vssrln_h_w, ALL, gen_vvv, gen_helper_vssrln_h_w)\n-TRANS(vssrln_w_d, ALL, gen_vvv, gen_helper_vssrln_w_d)\n-TRANS(vssran_b_h, ALL, gen_vvv, gen_helper_vssran_b_h)\n-TRANS(vssran_h_w, ALL, gen_vvv, gen_helper_vssran_h_w)\n-TRANS(vssran_w_d, ALL, gen_vvv, gen_helper_vssran_w_d)\n-TRANS(vssrln_bu_h, ALL, gen_vvv, gen_helper_vssrln_bu_h)\n-TRANS(vssrln_hu_w, ALL, gen_vvv, gen_helper_vssrln_hu_w)\n-TRANS(vssrln_wu_d, ALL, gen_vvv, gen_helper_vssrln_wu_d)\n-TRANS(vssran_bu_h, ALL, gen_vvv, gen_helper_vssran_bu_h)\n-TRANS(vssran_hu_w, ALL, gen_vvv, gen_helper_vssran_hu_w)\n-TRANS(vssran_wu_d, ALL, gen_vvv, gen_helper_vssran_wu_d)\n-\n-TRANS(vssrlni_b_h, ALL, gen_vv_i, gen_helper_vssrlni_b_h)\n-TRANS(vssrlni_h_w, ALL, gen_vv_i, gen_helper_vssrlni_h_w)\n-TRANS(vssrlni_w_d, ALL, gen_vv_i, gen_helper_vssrlni_w_d)\n-TRANS(vssrlni_d_q, ALL, gen_vv_i, gen_helper_vssrlni_d_q)\n-TRANS(vssrani_b_h, ALL, gen_vv_i, gen_helper_vssrani_b_h)\n-TRANS(vssrani_h_w, ALL, gen_vv_i, gen_helper_vssrani_h_w)\n-TRANS(vssrani_w_d, ALL, gen_vv_i, gen_helper_vssrani_w_d)\n-TRANS(vssrani_d_q, ALL, gen_vv_i, gen_helper_vssrani_d_q)\n-TRANS(vssrlni_bu_h, ALL, gen_vv_i, gen_helper_vssrlni_bu_h)\n-TRANS(vssrlni_hu_w, ALL, gen_vv_i, gen_helper_vssrlni_hu_w)\n-TRANS(vssrlni_wu_d, ALL, gen_vv_i, gen_helper_vssrlni_wu_d)\n-TRANS(vssrlni_du_q, ALL, gen_vv_i, gen_helper_vssrlni_du_q)\n-TRANS(vssrani_bu_h, ALL, gen_vv_i, gen_helper_vssrani_bu_h)\n-TRANS(vssrani_hu_w, ALL, gen_vv_i, gen_helper_vssrani_hu_w)\n-TRANS(vssrani_wu_d, ALL, gen_vv_i, gen_helper_vssrani_wu_d)\n-TRANS(vssrani_du_q, ALL, gen_vv_i, gen_helper_vssrani_du_q)\n-\n-TRANS(vssrlrn_b_h, ALL, gen_vvv, gen_helper_vssrlrn_b_h)\n-TRANS(vssrlrn_h_w, ALL, gen_vvv, gen_helper_vssrlrn_h_w)\n-TRANS(vssrlrn_w_d, ALL, gen_vvv, gen_helper_vssrlrn_w_d)\n-TRANS(vssrarn_b_h, ALL, gen_vvv, gen_helper_vssrarn_b_h)\n-TRANS(vssrarn_h_w, ALL, gen_vvv, gen_helper_vssrarn_h_w)\n-TRANS(vssrarn_w_d, ALL, gen_vvv, gen_helper_vssrarn_w_d)\n-TRANS(vssrlrn_bu_h, ALL, gen_vvv, gen_helper_vssrlrn_bu_h)\n-TRANS(vssrlrn_hu_w, ALL, gen_vvv, gen_helper_vssrlrn_hu_w)\n-TRANS(vssrlrn_wu_d, ALL, gen_vvv, gen_helper_vssrlrn_wu_d)\n-TRANS(vssrarn_bu_h, ALL, gen_vvv, gen_helper_vssrarn_bu_h)\n-TRANS(vssrarn_hu_w, ALL, gen_vvv, gen_helper_vssrarn_hu_w)\n-TRANS(vssrarn_wu_d, ALL, gen_vvv, gen_helper_vssrarn_wu_d)\n-\n-TRANS(vssrlrni_b_h, ALL, gen_vv_i, gen_helper_vssrlrni_b_h)\n-TRANS(vssrlrni_h_w, ALL, gen_vv_i, gen_helper_vssrlrni_h_w)\n-TRANS(vssrlrni_w_d, ALL, gen_vv_i, gen_helper_vssrlrni_w_d)\n-TRANS(vssrlrni_d_q, ALL, gen_vv_i, gen_helper_vssrlrni_d_q)\n-TRANS(vssrarni_b_h, ALL, gen_vv_i, gen_helper_vssrarni_b_h)\n-TRANS(vssrarni_h_w, ALL, gen_vv_i, gen_helper_vssrarni_h_w)\n-TRANS(vssrarni_w_d, ALL, gen_vv_i, gen_helper_vssrarni_w_d)\n-TRANS(vssrarni_d_q, ALL, gen_vv_i, gen_helper_vssrarni_d_q)\n-TRANS(vssrlrni_bu_h, ALL, gen_vv_i, gen_helper_vssrlrni_bu_h)\n-TRANS(vssrlrni_hu_w, ALL, gen_vv_i, gen_helper_vssrlrni_hu_w)\n-TRANS(vssrlrni_wu_d, ALL, gen_vv_i, gen_helper_vssrlrni_wu_d)\n-TRANS(vssrlrni_du_q, ALL, gen_vv_i, gen_helper_vssrlrni_du_q)\n-TRANS(vssrarni_bu_h, ALL, gen_vv_i, gen_helper_vssrarni_bu_h)\n-TRANS(vssrarni_hu_w, ALL, gen_vv_i, gen_helper_vssrarni_hu_w)\n-TRANS(vssrarni_wu_d, ALL, gen_vv_i, gen_helper_vssrarni_wu_d)\n-TRANS(vssrarni_du_q, ALL, gen_vv_i, gen_helper_vssrarni_du_q)\n-\n-TRANS(vclo_b, ALL, gen_vv, gen_helper_vclo_b)\n-TRANS(vclo_h, ALL, gen_vv, gen_helper_vclo_h)\n-TRANS(vclo_w, ALL, gen_vv, gen_helper_vclo_w)\n-TRANS(vclo_d, ALL, gen_vv, gen_helper_vclo_d)\n-TRANS(vclz_b, ALL, gen_vv, gen_helper_vclz_b)\n-TRANS(vclz_h, ALL, gen_vv, gen_helper_vclz_h)\n-TRANS(vclz_w, ALL, gen_vv, gen_helper_vclz_w)\n-TRANS(vclz_d, ALL, gen_vv, gen_helper_vclz_d)\n-\n-TRANS(vpcnt_b, ALL, gen_vv, gen_helper_vpcnt_b)\n-TRANS(vpcnt_h, ALL, gen_vv, gen_helper_vpcnt_h)\n-TRANS(vpcnt_w, ALL, gen_vv, gen_helper_vpcnt_w)\n-TRANS(vpcnt_d, ALL, gen_vv, gen_helper_vpcnt_d)\n+TRANS(vnori_b, LSX, gvec_vv_i, MO_8, do_vnori_b)\n+\n+TRANS(vsll_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_shlv)\n+TRANS(vsll_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_shlv)\n+TRANS(vsll_w, LSX, gvec_vvv, MO_32, tcg_gen_gvec_shlv)\n+TRANS(vsll_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_shlv)\n+TRANS(vslli_b, LSX, gvec_vv_i, MO_8, tcg_gen_gvec_shli)\n+TRANS(vslli_h, LSX, gvec_vv_i, MO_16, tcg_gen_gvec_shli)\n+TRANS(vslli_w, LSX, gvec_vv_i, MO_32, tcg_gen_gvec_shli)\n+TRANS(vslli_d, LSX, gvec_vv_i, MO_64, tcg_gen_gvec_shli)\n+\n+TRANS(vsrl_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_shrv)\n+TRANS(vsrl_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_shrv)\n+TRANS(vsrl_w, LSX, gvec_vvv, MO_32, tcg_gen_gvec_shrv)\n+TRANS(vsrl_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_shrv)\n+TRANS(vsrli_b, LSX, gvec_vv_i, MO_8, tcg_gen_gvec_shri)\n+TRANS(vsrli_h, LSX, gvec_vv_i, MO_16, tcg_gen_gvec_shri)\n+TRANS(vsrli_w, LSX, gvec_vv_i, MO_32, tcg_gen_gvec_shri)\n+TRANS(vsrli_d, LSX, gvec_vv_i, MO_64, tcg_gen_gvec_shri)\n+\n+TRANS(vsra_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_sarv)\n+TRANS(vsra_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_sarv)\n+TRANS(vsra_w, LSX, gvec_vvv, MO_32, tcg_gen_gvec_sarv)\n+TRANS(vsra_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_sarv)\n+TRANS(vsrai_b, LSX, gvec_vv_i, MO_8, tcg_gen_gvec_sari)\n+TRANS(vsrai_h, LSX, gvec_vv_i, MO_16, tcg_gen_gvec_sari)\n+TRANS(vsrai_w, LSX, gvec_vv_i, MO_32, tcg_gen_gvec_sari)\n+TRANS(vsrai_d, LSX, gvec_vv_i, MO_64, tcg_gen_gvec_sari)\n+\n+TRANS(vrotr_b, LSX, gvec_vvv, MO_8, tcg_gen_gvec_rotrv)\n+TRANS(vrotr_h, LSX, gvec_vvv, MO_16, tcg_gen_gvec_rotrv)\n+TRANS(vrotr_w, LSX, gvec_vvv, MO_32, tcg_gen_gvec_rotrv)\n+TRANS(vrotr_d, LSX, gvec_vvv, MO_64, tcg_gen_gvec_rotrv)\n+TRANS(vrotri_b, LSX, gvec_vv_i, MO_8, tcg_gen_gvec_rotri)\n+TRANS(vrotri_h, LSX, gvec_vv_i, MO_16, tcg_gen_gvec_rotri)\n+TRANS(vrotri_w, LSX, gvec_vv_i, MO_32, tcg_gen_gvec_rotri)\n+TRANS(vrotri_d, LSX, gvec_vv_i, MO_64, tcg_gen_gvec_rotri)\n+\n+TRANS(vsllwil_h_b, LSX, gen_vv_i, gen_helper_vsllwil_h_b)\n+TRANS(vsllwil_w_h, LSX, gen_vv_i, gen_helper_vsllwil_w_h)\n+TRANS(vsllwil_d_w, LSX, gen_vv_i, gen_helper_vsllwil_d_w)\n+TRANS(vextl_q_d, LSX, gen_vv, gen_helper_vextl_q_d)\n+TRANS(vsllwil_hu_bu, LSX, gen_vv_i, gen_helper_vsllwil_hu_bu)\n+TRANS(vsllwil_wu_hu, LSX, gen_vv_i, gen_helper_vsllwil_wu_hu)\n+TRANS(vsllwil_du_wu, LSX, gen_vv_i, gen_helper_vsllwil_du_wu)\n+TRANS(vextl_qu_du, LSX, gen_vv, gen_helper_vextl_qu_du)\n+\n+TRANS(vsrlr_b, LSX, gen_vvv, gen_helper_vsrlr_b)\n+TRANS(vsrlr_h, LSX, gen_vvv, gen_helper_vsrlr_h)\n+TRANS(vsrlr_w, LSX, gen_vvv, gen_helper_vsrlr_w)\n+TRANS(vsrlr_d, LSX, gen_vvv, gen_helper_vsrlr_d)\n+TRANS(vsrlri_b, LSX, gen_vv_i, gen_helper_vsrlri_b)\n+TRANS(vsrlri_h, LSX, gen_vv_i, gen_helper_vsrlri_h)\n+TRANS(vsrlri_w, LSX, gen_vv_i, gen_helper_vsrlri_w)\n+TRANS(vsrlri_d, LSX, gen_vv_i, gen_helper_vsrlri_d)\n+\n+TRANS(vsrar_b, LSX, gen_vvv, gen_helper_vsrar_b)\n+TRANS(vsrar_h, LSX, gen_vvv, gen_helper_vsrar_h)\n+TRANS(vsrar_w, LSX, gen_vvv, gen_helper_vsrar_w)\n+TRANS(vsrar_d, LSX, gen_vvv, gen_helper_vsrar_d)\n+TRANS(vsrari_b, LSX, gen_vv_i, gen_helper_vsrari_b)\n+TRANS(vsrari_h, LSX, gen_vv_i, gen_helper_vsrari_h)\n+TRANS(vsrari_w, LSX, gen_vv_i, gen_helper_vsrari_w)\n+TRANS(vsrari_d, LSX, gen_vv_i, gen_helper_vsrari_d)\n+\n+TRANS(vsrln_b_h, LSX, gen_vvv, gen_helper_vsrln_b_h)\n+TRANS(vsrln_h_w, LSX, gen_vvv, gen_helper_vsrln_h_w)\n+TRANS(vsrln_w_d, LSX, gen_vvv, gen_helper_vsrln_w_d)\n+TRANS(vsran_b_h, LSX, gen_vvv, gen_helper_vsran_b_h)\n+TRANS(vsran_h_w, LSX, gen_vvv, gen_helper_vsran_h_w)\n+TRANS(vsran_w_d, LSX, gen_vvv, gen_helper_vsran_w_d)\n+\n+TRANS(vsrlni_b_h, LSX, gen_vv_i, gen_helper_vsrlni_b_h)\n+TRANS(vsrlni_h_w, LSX, gen_vv_i, gen_helper_vsrlni_h_w)\n+TRANS(vsrlni_w_d, LSX, gen_vv_i, gen_helper_vsrlni_w_d)\n+TRANS(vsrlni_d_q, LSX, gen_vv_i, gen_helper_vsrlni_d_q)\n+TRANS(vsrani_b_h, LSX, gen_vv_i, gen_helper_vsrani_b_h)\n+TRANS(vsrani_h_w, LSX, gen_vv_i, gen_helper_vsrani_h_w)\n+TRANS(vsrani_w_d, LSX, gen_vv_i, gen_helper_vsrani_w_d)\n+TRANS(vsrani_d_q, LSX, gen_vv_i, gen_helper_vsrani_d_q)\n+\n+TRANS(vsrlrn_b_h, LSX, gen_vvv, gen_helper_vsrlrn_b_h)\n+TRANS(vsrlrn_h_w, LSX, gen_vvv, gen_helper_vsrlrn_h_w)\n+TRANS(vsrlrn_w_d, LSX, gen_vvv, gen_helper_vsrlrn_w_d)\n+TRANS(vsrarn_b_h, LSX, gen_vvv, gen_helper_vsrarn_b_h)\n+TRANS(vsrarn_h_w, LSX, gen_vvv, gen_helper_vsrarn_h_w)\n+TRANS(vsrarn_w_d, LSX, gen_vvv, gen_helper_vsrarn_w_d)\n+\n+TRANS(vsrlrni_b_h, LSX, gen_vv_i, gen_helper_vsrlrni_b_h)\n+TRANS(vsrlrni_h_w, LSX, gen_vv_i, gen_helper_vsrlrni_h_w)\n+TRANS(vsrlrni_w_d, LSX, gen_vv_i, gen_helper_vsrlrni_w_d)\n+TRANS(vsrlrni_d_q, LSX, gen_vv_i, gen_helper_vsrlrni_d_q)\n+TRANS(vsrarni_b_h, LSX, gen_vv_i, gen_helper_vsrarni_b_h)\n+TRANS(vsrarni_h_w, LSX, gen_vv_i, gen_helper_vsrarni_h_w)\n+TRANS(vsrarni_w_d, LSX, gen_vv_i, gen_helper_vsrarni_w_d)\n+TRANS(vsrarni_d_q, LSX, gen_vv_i, gen_helper_vsrarni_d_q)\n+\n+TRANS(vssrln_b_h, LSX, gen_vvv, gen_helper_vssrln_b_h)\n+TRANS(vssrln_h_w, LSX, gen_vvv, gen_helper_vssrln_h_w)\n+TRANS(vssrln_w_d, LSX, gen_vvv, gen_helper_vssrln_w_d)\n+TRANS(vssran_b_h, LSX, gen_vvv, gen_helper_vssran_b_h)\n+TRANS(vssran_h_w, LSX, gen_vvv, gen_helper_vssran_h_w)\n+TRANS(vssran_w_d, LSX, gen_vvv, gen_helper_vssran_w_d)\n+TRANS(vssrln_bu_h, LSX, gen_vvv, gen_helper_vssrln_bu_h)\n+TRANS(vssrln_hu_w, LSX, gen_vvv, gen_helper_vssrln_hu_w)\n+TRANS(vssrln_wu_d, LSX, gen_vvv, gen_helper_vssrln_wu_d)\n+TRANS(vssran_bu_h, LSX, gen_vvv, gen_helper_vssran_bu_h)\n+TRANS(vssran_hu_w, LSX, gen_vvv, gen_helper_vssran_hu_w)\n+TRANS(vssran_wu_d, LSX, gen_vvv, gen_helper_vssran_wu_d)\n+\n+TRANS(vssrlni_b_h, LSX, gen_vv_i, gen_helper_vssrlni_b_h)\n+TRANS(vssrlni_h_w, LSX, gen_vv_i, gen_helper_vssrlni_h_w)\n+TRANS(vssrlni_w_d, LSX, gen_vv_i, gen_helper_vssrlni_w_d)\n+TRANS(vssrlni_d_q, LSX, gen_vv_i, gen_helper_vssrlni_d_q)\n+TRANS(vssrani_b_h, LSX, gen_vv_i, gen_helper_vssrani_b_h)\n+TRANS(vssrani_h_w, LSX, gen_vv_i, gen_helper_vssrani_h_w)\n+TRANS(vssrani_w_d, LSX, gen_vv_i, gen_helper_vssrani_w_d)\n+TRANS(vssrani_d_q, LSX, gen_vv_i, gen_helper_vssrani_d_q)\n+TRANS(vssrlni_bu_h, LSX, gen_vv_i, gen_helper_vssrlni_bu_h)\n+TRANS(vssrlni_hu_w, LSX, gen_vv_i, gen_helper_vssrlni_hu_w)\n+TRANS(vssrlni_wu_d, LSX, gen_vv_i, gen_helper_vssrlni_wu_d)\n+TRANS(vssrlni_du_q, LSX, gen_vv_i, gen_helper_vssrlni_du_q)\n+TRANS(vssrani_bu_h, LSX, gen_vv_i, gen_helper_vssrani_bu_h)\n+TRANS(vssrani_hu_w, LSX, gen_vv_i, gen_helper_vssrani_hu_w)\n+TRANS(vssrani_wu_d, LSX, gen_vv_i, gen_helper_vssrani_wu_d)\n+TRANS(vssrani_du_q, LSX, gen_vv_i, gen_helper_vssrani_du_q)\n+\n+TRANS(vssrlrn_b_h, LSX, gen_vvv, gen_helper_vssrlrn_b_h)\n+TRANS(vssrlrn_h_w, LSX, gen_vvv, gen_helper_vssrlrn_h_w)\n+TRANS(vssrlrn_w_d, LSX, gen_vvv, gen_helper_vssrlrn_w_d)\n+TRANS(vssrarn_b_h, LSX, gen_vvv, gen_helper_vssrarn_b_h)\n+TRANS(vssrarn_h_w, LSX, gen_vvv, gen_helper_vssrarn_h_w)\n+TRANS(vssrarn_w_d, LSX, gen_vvv, gen_helper_vssrarn_w_d)\n+TRANS(vssrlrn_bu_h, LSX, gen_vvv, gen_helper_vssrlrn_bu_h)\n+TRANS(vssrlrn_hu_w, LSX, gen_vvv, gen_helper_vssrlrn_hu_w)\n+TRANS(vssrlrn_wu_d, LSX, gen_vvv, gen_helper_vssrlrn_wu_d)\n+TRANS(vssrarn_bu_h, LSX, gen_vvv, gen_helper_vssrarn_bu_h)\n+TRANS(vssrarn_hu_w, LSX, gen_vvv, gen_helper_vssrarn_hu_w)\n+TRANS(vssrarn_wu_d, LSX, gen_vvv, gen_helper_vssrarn_wu_d)\n+\n+TRANS(vssrlrni_b_h, LSX, gen_vv_i, gen_helper_vssrlrni_b_h)\n+TRANS(vssrlrni_h_w, LSX, gen_vv_i, gen_helper_vssrlrni_h_w)\n+TRANS(vssrlrni_w_d, LSX, gen_vv_i, gen_helper_vssrlrni_w_d)\n+TRANS(vssrlrni_d_q, LSX, gen_vv_i, gen_helper_vssrlrni_d_q)\n+TRANS(vssrarni_b_h, LSX, gen_vv_i, gen_helper_vssrarni_b_h)\n+TRANS(vssrarni_h_w, LSX, gen_vv_i, gen_helper_vssrarni_h_w)\n+TRANS(vssrarni_w_d, LSX, gen_vv_i, gen_helper_vssrarni_w_d)\n+TRANS(vssrarni_d_q, LSX, gen_vv_i, gen_helper_vssrarni_d_q)\n+TRANS(vssrlrni_bu_h, LSX, gen_vv_i, gen_helper_vssrlrni_bu_h)\n+TRANS(vssrlrni_hu_w, LSX, gen_vv_i, gen_helper_vssrlrni_hu_w)\n+TRANS(vssrlrni_wu_d, LSX, gen_vv_i, gen_helper_vssrlrni_wu_d)\n+TRANS(vssrlrni_du_q, LSX, gen_vv_i, gen_helper_vssrlrni_du_q)\n+TRANS(vssrarni_bu_h, LSX, gen_vv_i, gen_helper_vssrarni_bu_h)\n+TRANS(vssrarni_hu_w, LSX, gen_vv_i, gen_helper_vssrarni_hu_w)\n+TRANS(vssrarni_wu_d, LSX, gen_vv_i, gen_helper_vssrarni_wu_d)\n+TRANS(vssrarni_du_q, LSX, gen_vv_i, gen_helper_vssrarni_du_q)\n+\n+TRANS(vclo_b, LSX, gen_vv, gen_helper_vclo_b)\n+TRANS(vclo_h, LSX, gen_vv, gen_helper_vclo_h)\n+TRANS(vclo_w, LSX, gen_vv, gen_helper_vclo_w)\n+TRANS(vclo_d, LSX, gen_vv, gen_helper_vclo_d)\n+TRANS(vclz_b, LSX, gen_vv, gen_helper_vclz_b)\n+TRANS(vclz_h, LSX, gen_vv, gen_helper_vclz_h)\n+TRANS(vclz_w, LSX, gen_vv, gen_helper_vclz_w)\n+TRANS(vclz_d, LSX, gen_vv, gen_helper_vclz_d)\n+\n+TRANS(vpcnt_b, LSX, gen_vv, gen_helper_vpcnt_b)\n+TRANS(vpcnt_h, LSX, gen_vv, gen_helper_vpcnt_h)\n+TRANS(vpcnt_w, LSX, gen_vv, gen_helper_vpcnt_w)\n+TRANS(vpcnt_d, LSX, gen_vv, gen_helper_vpcnt_d)\n \n static void do_vbit(unsigned vece, TCGv_vec t, TCGv_vec a, TCGv_vec b,\n void (*func)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec))\n@@ -3340,10 +3361,10 @@ static void do_vbitclr(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vbitclr_b, ALL, gvec_vvv, MO_8, do_vbitclr)\n-TRANS(vbitclr_h, ALL, gvec_vvv, MO_16, do_vbitclr)\n-TRANS(vbitclr_w, ALL, gvec_vvv, MO_32, do_vbitclr)\n-TRANS(vbitclr_d, ALL, gvec_vvv, MO_64, do_vbitclr)\n+TRANS(vbitclr_b, LSX, gvec_vvv, MO_8, do_vbitclr)\n+TRANS(vbitclr_h, LSX, gvec_vvv, MO_16, do_vbitclr)\n+TRANS(vbitclr_w, LSX, gvec_vvv, MO_32, do_vbitclr)\n+TRANS(vbitclr_d, LSX, gvec_vvv, MO_64, do_vbitclr)\n \n static void do_vbiti(unsigned vece, TCGv_vec t, TCGv_vec a, int64_t imm,\n void (*func)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec))\n@@ -3410,10 +3431,10 @@ static void do_vbitclri(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, imm, &op[vece]);\n }\n \n-TRANS(vbitclri_b, ALL, gvec_vv_i, MO_8, do_vbitclri)\n-TRANS(vbitclri_h, ALL, gvec_vv_i, MO_16, do_vbitclri)\n-TRANS(vbitclri_w, ALL, gvec_vv_i, MO_32, do_vbitclri)\n-TRANS(vbitclri_d, ALL, gvec_vv_i, MO_64, do_vbitclri)\n+TRANS(vbitclri_b, LSX, gvec_vv_i, MO_8, do_vbitclri)\n+TRANS(vbitclri_h, LSX, gvec_vv_i, MO_16, do_vbitclri)\n+TRANS(vbitclri_w, LSX, gvec_vv_i, MO_32, do_vbitclri)\n+TRANS(vbitclri_d, LSX, gvec_vv_i, MO_64, do_vbitclri)\n \n static void do_vbitset(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n uint32_t vk_ofs, uint32_t oprsz, uint32_t maxsz)\n@@ -3451,10 +3472,10 @@ static void do_vbitset(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vbitset_b, ALL, gvec_vvv, MO_8, do_vbitset)\n-TRANS(vbitset_h, ALL, gvec_vvv, MO_16, do_vbitset)\n-TRANS(vbitset_w, ALL, gvec_vvv, MO_32, do_vbitset)\n-TRANS(vbitset_d, ALL, gvec_vvv, MO_64, do_vbitset)\n+TRANS(vbitset_b, LSX, gvec_vvv, MO_8, do_vbitset)\n+TRANS(vbitset_h, LSX, gvec_vvv, MO_16, do_vbitset)\n+TRANS(vbitset_w, LSX, gvec_vvv, MO_32, do_vbitset)\n+TRANS(vbitset_d, LSX, gvec_vvv, MO_64, do_vbitset)\n \n static void do_vbitseti(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n int64_t imm, uint32_t oprsz, uint32_t maxsz)\n@@ -3492,10 +3513,10 @@ static void do_vbitseti(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, imm, &op[vece]);\n }\n \n-TRANS(vbitseti_b, ALL, gvec_vv_i, MO_8, do_vbitseti)\n-TRANS(vbitseti_h, ALL, gvec_vv_i, MO_16, do_vbitseti)\n-TRANS(vbitseti_w, ALL, gvec_vv_i, MO_32, do_vbitseti)\n-TRANS(vbitseti_d, ALL, gvec_vv_i, MO_64, do_vbitseti)\n+TRANS(vbitseti_b, LSX, gvec_vv_i, MO_8, do_vbitseti)\n+TRANS(vbitseti_h, LSX, gvec_vv_i, MO_16, do_vbitseti)\n+TRANS(vbitseti_w, LSX, gvec_vv_i, MO_32, do_vbitseti)\n+TRANS(vbitseti_d, LSX, gvec_vv_i, MO_64, do_vbitseti)\n \n static void do_vbitrev(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n uint32_t vk_ofs, uint32_t oprsz, uint32_t maxsz)\n@@ -3533,10 +3554,10 @@ static void do_vbitrev(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_3(vd_ofs, vj_ofs, vk_ofs, oprsz, maxsz, &op[vece]);\n }\n \n-TRANS(vbitrev_b, ALL, gvec_vvv, MO_8, do_vbitrev)\n-TRANS(vbitrev_h, ALL, gvec_vvv, MO_16, do_vbitrev)\n-TRANS(vbitrev_w, ALL, gvec_vvv, MO_32, do_vbitrev)\n-TRANS(vbitrev_d, ALL, gvec_vvv, MO_64, do_vbitrev)\n+TRANS(vbitrev_b, LSX, gvec_vvv, MO_8, do_vbitrev)\n+TRANS(vbitrev_h, LSX, gvec_vvv, MO_16, do_vbitrev)\n+TRANS(vbitrev_w, LSX, gvec_vvv, MO_32, do_vbitrev)\n+TRANS(vbitrev_d, LSX, gvec_vvv, MO_64, do_vbitrev)\n \n static void do_vbitrevi(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n int64_t imm, uint32_t oprsz, uint32_t maxsz)\n@@ -3574,112 +3595,112 @@ static void do_vbitrevi(unsigned vece, uint32_t vd_ofs, uint32_t vj_ofs,\n tcg_gen_gvec_2i(vd_ofs, vj_ofs, oprsz, maxsz, imm, &op[vece]);\n }\n \n-TRANS(vbitrevi_b, ALL, gvec_vv_i, MO_8, do_vbitrevi)\n-TRANS(vbitrevi_h, ALL, gvec_vv_i, MO_16, do_vbitrevi)\n-TRANS(vbitrevi_w, ALL, gvec_vv_i, MO_32, do_vbitrevi)\n-TRANS(vbitrevi_d, ALL, gvec_vv_i, MO_64, do_vbitrevi)\n-\n-TRANS(vfrstp_b, ALL, gen_vvv, gen_helper_vfrstp_b)\n-TRANS(vfrstp_h, ALL, gen_vvv, gen_helper_vfrstp_h)\n-TRANS(vfrstpi_b, ALL, gen_vv_i, gen_helper_vfrstpi_b)\n-TRANS(vfrstpi_h, ALL, gen_vv_i, gen_helper_vfrstpi_h)\n-\n-TRANS(vfadd_s, ALL, gen_vvv, gen_helper_vfadd_s)\n-TRANS(vfadd_d, ALL, gen_vvv, gen_helper_vfadd_d)\n-TRANS(vfsub_s, ALL, gen_vvv, gen_helper_vfsub_s)\n-TRANS(vfsub_d, ALL, gen_vvv, gen_helper_vfsub_d)\n-TRANS(vfmul_s, ALL, gen_vvv, gen_helper_vfmul_s)\n-TRANS(vfmul_d, ALL, gen_vvv, gen_helper_vfmul_d)\n-TRANS(vfdiv_s, ALL, gen_vvv, gen_helper_vfdiv_s)\n-TRANS(vfdiv_d, ALL, gen_vvv, gen_helper_vfdiv_d)\n-\n-TRANS(vfmadd_s, ALL, gen_vvvv, gen_helper_vfmadd_s)\n-TRANS(vfmadd_d, ALL, gen_vvvv, gen_helper_vfmadd_d)\n-TRANS(vfmsub_s, ALL, gen_vvvv, gen_helper_vfmsub_s)\n-TRANS(vfmsub_d, ALL, gen_vvvv, gen_helper_vfmsub_d)\n-TRANS(vfnmadd_s, ALL, gen_vvvv, gen_helper_vfnmadd_s)\n-TRANS(vfnmadd_d, ALL, gen_vvvv, gen_helper_vfnmadd_d)\n-TRANS(vfnmsub_s, ALL, gen_vvvv, gen_helper_vfnmsub_s)\n-TRANS(vfnmsub_d, ALL, gen_vvvv, gen_helper_vfnmsub_d)\n-\n-TRANS(vfmax_s, ALL, gen_vvv, gen_helper_vfmax_s)\n-TRANS(vfmax_d, ALL, gen_vvv, gen_helper_vfmax_d)\n-TRANS(vfmin_s, ALL, gen_vvv, gen_helper_vfmin_s)\n-TRANS(vfmin_d, ALL, gen_vvv, gen_helper_vfmin_d)\n-\n-TRANS(vfmaxa_s, ALL, gen_vvv, gen_helper_vfmaxa_s)\n-TRANS(vfmaxa_d, ALL, gen_vvv, gen_helper_vfmaxa_d)\n-TRANS(vfmina_s, ALL, gen_vvv, gen_helper_vfmina_s)\n-TRANS(vfmina_d, ALL, gen_vvv, gen_helper_vfmina_d)\n-\n-TRANS(vflogb_s, ALL, gen_vv, gen_helper_vflogb_s)\n-TRANS(vflogb_d, ALL, gen_vv, gen_helper_vflogb_d)\n-\n-TRANS(vfclass_s, ALL, gen_vv, gen_helper_vfclass_s)\n-TRANS(vfclass_d, ALL, gen_vv, gen_helper_vfclass_d)\n-\n-TRANS(vfsqrt_s, ALL, gen_vv, gen_helper_vfsqrt_s)\n-TRANS(vfsqrt_d, ALL, gen_vv, gen_helper_vfsqrt_d)\n-TRANS(vfrecip_s, ALL, gen_vv, gen_helper_vfrecip_s)\n-TRANS(vfrecip_d, ALL, gen_vv, gen_helper_vfrecip_d)\n-TRANS(vfrsqrt_s, ALL, gen_vv, gen_helper_vfrsqrt_s)\n-TRANS(vfrsqrt_d, ALL, gen_vv, gen_helper_vfrsqrt_d)\n-\n-TRANS(vfcvtl_s_h, ALL, gen_vv, gen_helper_vfcvtl_s_h)\n-TRANS(vfcvth_s_h, ALL, gen_vv, gen_helper_vfcvth_s_h)\n-TRANS(vfcvtl_d_s, ALL, gen_vv, gen_helper_vfcvtl_d_s)\n-TRANS(vfcvth_d_s, ALL, gen_vv, gen_helper_vfcvth_d_s)\n-TRANS(vfcvt_h_s, ALL, gen_vvv, gen_helper_vfcvt_h_s)\n-TRANS(vfcvt_s_d, ALL, gen_vvv, gen_helper_vfcvt_s_d)\n-\n-TRANS(vfrintrne_s, ALL, gen_vv, gen_helper_vfrintrne_s)\n-TRANS(vfrintrne_d, ALL, gen_vv, gen_helper_vfrintrne_d)\n-TRANS(vfrintrz_s, ALL, gen_vv, gen_helper_vfrintrz_s)\n-TRANS(vfrintrz_d, ALL, gen_vv, gen_helper_vfrintrz_d)\n-TRANS(vfrintrp_s, ALL, gen_vv, gen_helper_vfrintrp_s)\n-TRANS(vfrintrp_d, ALL, gen_vv, gen_helper_vfrintrp_d)\n-TRANS(vfrintrm_s, ALL, gen_vv, gen_helper_vfrintrm_s)\n-TRANS(vfrintrm_d, ALL, gen_vv, gen_helper_vfrintrm_d)\n-TRANS(vfrint_s, ALL, gen_vv, gen_helper_vfrint_s)\n-TRANS(vfrint_d, ALL, gen_vv, gen_helper_vfrint_d)\n-\n-TRANS(vftintrne_w_s, ALL, gen_vv, gen_helper_vftintrne_w_s)\n-TRANS(vftintrne_l_d, ALL, gen_vv, gen_helper_vftintrne_l_d)\n-TRANS(vftintrz_w_s, ALL, gen_vv, gen_helper_vftintrz_w_s)\n-TRANS(vftintrz_l_d, ALL, gen_vv, gen_helper_vftintrz_l_d)\n-TRANS(vftintrp_w_s, ALL, gen_vv, gen_helper_vftintrp_w_s)\n-TRANS(vftintrp_l_d, ALL, gen_vv, gen_helper_vftintrp_l_d)\n-TRANS(vftintrm_w_s, ALL, gen_vv, gen_helper_vftintrm_w_s)\n-TRANS(vftintrm_l_d, ALL, gen_vv, gen_helper_vftintrm_l_d)\n-TRANS(vftint_w_s, ALL, gen_vv, gen_helper_vftint_w_s)\n-TRANS(vftint_l_d, ALL, gen_vv, gen_helper_vftint_l_d)\n-TRANS(vftintrz_wu_s, ALL, gen_vv, gen_helper_vftintrz_wu_s)\n-TRANS(vftintrz_lu_d, ALL, gen_vv, gen_helper_vftintrz_lu_d)\n-TRANS(vftint_wu_s, ALL, gen_vv, gen_helper_vftint_wu_s)\n-TRANS(vftint_lu_d, ALL, gen_vv, gen_helper_vftint_lu_d)\n-TRANS(vftintrne_w_d, ALL, gen_vvv, gen_helper_vftintrne_w_d)\n-TRANS(vftintrz_w_d, ALL, gen_vvv, gen_helper_vftintrz_w_d)\n-TRANS(vftintrp_w_d, ALL, gen_vvv, gen_helper_vftintrp_w_d)\n-TRANS(vftintrm_w_d, ALL, gen_vvv, gen_helper_vftintrm_w_d)\n-TRANS(vftint_w_d, ALL, gen_vvv, gen_helper_vftint_w_d)\n-TRANS(vftintrnel_l_s, ALL, gen_vv, gen_helper_vftintrnel_l_s)\n-TRANS(vftintrneh_l_s, ALL, gen_vv, gen_helper_vftintrneh_l_s)\n-TRANS(vftintrzl_l_s, ALL, gen_vv, gen_helper_vftintrzl_l_s)\n-TRANS(vftintrzh_l_s, ALL, gen_vv, gen_helper_vftintrzh_l_s)\n-TRANS(vftintrpl_l_s, ALL, gen_vv, gen_helper_vftintrpl_l_s)\n-TRANS(vftintrph_l_s, ALL, gen_vv, gen_helper_vftintrph_l_s)\n-TRANS(vftintrml_l_s, ALL, gen_vv, gen_helper_vftintrml_l_s)\n-TRANS(vftintrmh_l_s, ALL, gen_vv, gen_helper_vftintrmh_l_s)\n-TRANS(vftintl_l_s, ALL, gen_vv, gen_helper_vftintl_l_s)\n-TRANS(vftinth_l_s, ALL, gen_vv, gen_helper_vftinth_l_s)\n-\n-TRANS(vffint_s_w, ALL, gen_vv, gen_helper_vffint_s_w)\n-TRANS(vffint_d_l, ALL, gen_vv, gen_helper_vffint_d_l)\n-TRANS(vffint_s_wu, ALL, gen_vv, gen_helper_vffint_s_wu)\n-TRANS(vffint_d_lu, ALL, gen_vv, gen_helper_vffint_d_lu)\n-TRANS(vffintl_d_w, ALL, gen_vv, gen_helper_vffintl_d_w)\n-TRANS(vffinth_d_w, ALL, gen_vv, gen_helper_vffinth_d_w)\n-TRANS(vffint_s_l, ALL, gen_vvv, gen_helper_vffint_s_l)\n+TRANS(vbitrevi_b, LSX, gvec_vv_i, MO_8, do_vbitrevi)\n+TRANS(vbitrevi_h, LSX, gvec_vv_i, MO_16, do_vbitrevi)\n+TRANS(vbitrevi_w, LSX, gvec_vv_i, MO_32, do_vbitrevi)\n+TRANS(vbitrevi_d, LSX, gvec_vv_i, MO_64, do_vbitrevi)\n+\n+TRANS(vfrstp_b, LSX, gen_vvv, gen_helper_vfrstp_b)\n+TRANS(vfrstp_h, LSX, gen_vvv, gen_helper_vfrstp_h)\n+TRANS(vfrstpi_b, LSX, gen_vv_i, gen_helper_vfrstpi_b)\n+TRANS(vfrstpi_h, LSX, gen_vv_i, gen_helper_vfrstpi_h)\n+\n+TRANS(vfadd_s, LSX, gen_vvv, gen_helper_vfadd_s)\n+TRANS(vfadd_d, LSX, gen_vvv, gen_helper_vfadd_d)\n+TRANS(vfsub_s, LSX, gen_vvv, gen_helper_vfsub_s)\n+TRANS(vfsub_d, LSX, gen_vvv, gen_helper_vfsub_d)\n+TRANS(vfmul_s, LSX, gen_vvv, gen_helper_vfmul_s)\n+TRANS(vfmul_d, LSX, gen_vvv, gen_helper_vfmul_d)\n+TRANS(vfdiv_s, LSX, gen_vvv, gen_helper_vfdiv_s)\n+TRANS(vfdiv_d, LSX, gen_vvv, gen_helper_vfdiv_d)\n+\n+TRANS(vfmadd_s, LSX, gen_vvvv, gen_helper_vfmadd_s)\n+TRANS(vfmadd_d, LSX, gen_vvvv, gen_helper_vfmadd_d)\n+TRANS(vfmsub_s, LSX, gen_vvvv, gen_helper_vfmsub_s)\n+TRANS(vfmsub_d, LSX, gen_vvvv, gen_helper_vfmsub_d)\n+TRANS(vfnmadd_s, LSX, gen_vvvv, gen_helper_vfnmadd_s)\n+TRANS(vfnmadd_d, LSX, gen_vvvv, gen_helper_vfnmadd_d)\n+TRANS(vfnmsub_s, LSX, gen_vvvv, gen_helper_vfnmsub_s)\n+TRANS(vfnmsub_d, LSX, gen_vvvv, gen_helper_vfnmsub_d)\n+\n+TRANS(vfmax_s, LSX, gen_vvv, gen_helper_vfmax_s)\n+TRANS(vfmax_d, LSX, gen_vvv, gen_helper_vfmax_d)\n+TRANS(vfmin_s, LSX, gen_vvv, gen_helper_vfmin_s)\n+TRANS(vfmin_d, LSX, gen_vvv, gen_helper_vfmin_d)\n+\n+TRANS(vfmaxa_s, LSX, gen_vvv, gen_helper_vfmaxa_s)\n+TRANS(vfmaxa_d, LSX, gen_vvv, gen_helper_vfmaxa_d)\n+TRANS(vfmina_s, LSX, gen_vvv, gen_helper_vfmina_s)\n+TRANS(vfmina_d, LSX, gen_vvv, gen_helper_vfmina_d)\n+\n+TRANS(vflogb_s, LSX, gen_vv, gen_helper_vflogb_s)\n+TRANS(vflogb_d, LSX, gen_vv, gen_helper_vflogb_d)\n+\n+TRANS(vfclass_s, LSX, gen_vv, gen_helper_vfclass_s)\n+TRANS(vfclass_d, LSX, gen_vv, gen_helper_vfclass_d)\n+\n+TRANS(vfsqrt_s, LSX, gen_vv, gen_helper_vfsqrt_s)\n+TRANS(vfsqrt_d, LSX, gen_vv, gen_helper_vfsqrt_d)\n+TRANS(vfrecip_s, LSX, gen_vv, gen_helper_vfrecip_s)\n+TRANS(vfrecip_d, LSX, gen_vv, gen_helper_vfrecip_d)\n+TRANS(vfrsqrt_s, LSX, gen_vv, gen_helper_vfrsqrt_s)\n+TRANS(vfrsqrt_d, LSX, gen_vv, gen_helper_vfrsqrt_d)\n+\n+TRANS(vfcvtl_s_h, LSX, gen_vv, gen_helper_vfcvtl_s_h)\n+TRANS(vfcvth_s_h, LSX, gen_vv, gen_helper_vfcvth_s_h)\n+TRANS(vfcvtl_d_s, LSX, gen_vv, gen_helper_vfcvtl_d_s)\n+TRANS(vfcvth_d_s, LSX, gen_vv, gen_helper_vfcvth_d_s)\n+TRANS(vfcvt_h_s, LSX, gen_vvv, gen_helper_vfcvt_h_s)\n+TRANS(vfcvt_s_d, LSX, gen_vvv, gen_helper_vfcvt_s_d)\n+\n+TRANS(vfrintrne_s, LSX, gen_vv, gen_helper_vfrintrne_s)\n+TRANS(vfrintrne_d, LSX, gen_vv, gen_helper_vfrintrne_d)\n+TRANS(vfrintrz_s, LSX, gen_vv, gen_helper_vfrintrz_s)\n+TRANS(vfrintrz_d, LSX, gen_vv, gen_helper_vfrintrz_d)\n+TRANS(vfrintrp_s, LSX, gen_vv, gen_helper_vfrintrp_s)\n+TRANS(vfrintrp_d, LSX, gen_vv, gen_helper_vfrintrp_d)\n+TRANS(vfrintrm_s, LSX, gen_vv, gen_helper_vfrintrm_s)\n+TRANS(vfrintrm_d, LSX, gen_vv, gen_helper_vfrintrm_d)\n+TRANS(vfrint_s, LSX, gen_vv, gen_helper_vfrint_s)\n+TRANS(vfrint_d, LSX, gen_vv, gen_helper_vfrint_d)\n+\n+TRANS(vftintrne_w_s, LSX, gen_vv, gen_helper_vftintrne_w_s)\n+TRANS(vftintrne_l_d, LSX, gen_vv, gen_helper_vftintrne_l_d)\n+TRANS(vftintrz_w_s, LSX, gen_vv, gen_helper_vftintrz_w_s)\n+TRANS(vftintrz_l_d, LSX, gen_vv, gen_helper_vftintrz_l_d)\n+TRANS(vftintrp_w_s, LSX, gen_vv, gen_helper_vftintrp_w_s)\n+TRANS(vftintrp_l_d, LSX, gen_vv, gen_helper_vftintrp_l_d)\n+TRANS(vftintrm_w_s, LSX, gen_vv, gen_helper_vftintrm_w_s)\n+TRANS(vftintrm_l_d, LSX, gen_vv, gen_helper_vftintrm_l_d)\n+TRANS(vftint_w_s, LSX, gen_vv, gen_helper_vftint_w_s)\n+TRANS(vftint_l_d, LSX, gen_vv, gen_helper_vftint_l_d)\n+TRANS(vftintrz_wu_s, LSX, gen_vv, gen_helper_vftintrz_wu_s)\n+TRANS(vftintrz_lu_d, LSX, gen_vv, gen_helper_vftintrz_lu_d)\n+TRANS(vftint_wu_s, LSX, gen_vv, gen_helper_vftint_wu_s)\n+TRANS(vftint_lu_d, LSX, gen_vv, gen_helper_vftint_lu_d)\n+TRANS(vftintrne_w_d, LSX, gen_vvv, gen_helper_vftintrne_w_d)\n+TRANS(vftintrz_w_d, LSX, gen_vvv, gen_helper_vftintrz_w_d)\n+TRANS(vftintrp_w_d, LSX, gen_vvv, gen_helper_vftintrp_w_d)\n+TRANS(vftintrm_w_d, LSX, gen_vvv, gen_helper_vftintrm_w_d)\n+TRANS(vftint_w_d, LSX, gen_vvv, gen_helper_vftint_w_d)\n+TRANS(vftintrnel_l_s, LSX, gen_vv, gen_helper_vftintrnel_l_s)\n+TRANS(vftintrneh_l_s, LSX, gen_vv, gen_helper_vftintrneh_l_s)\n+TRANS(vftintrzl_l_s, LSX, gen_vv, gen_helper_vftintrzl_l_s)\n+TRANS(vftintrzh_l_s, LSX, gen_vv, gen_helper_vftintrzh_l_s)\n+TRANS(vftintrpl_l_s, LSX, gen_vv, gen_helper_vftintrpl_l_s)\n+TRANS(vftintrph_l_s, LSX, gen_vv, gen_helper_vftintrph_l_s)\n+TRANS(vftintrml_l_s, LSX, gen_vv, gen_helper_vftintrml_l_s)\n+TRANS(vftintrmh_l_s, LSX, gen_vv, gen_helper_vftintrmh_l_s)\n+TRANS(vftintl_l_s, LSX, gen_vv, gen_helper_vftintl_l_s)\n+TRANS(vftinth_l_s, LSX, gen_vv, gen_helper_vftinth_l_s)\n+\n+TRANS(vffint_s_w, LSX, gen_vv, gen_helper_vffint_s_w)\n+TRANS(vffint_d_l, LSX, gen_vv, gen_helper_vffint_d_l)\n+TRANS(vffint_s_wu, LSX, gen_vv, gen_helper_vffint_s_wu)\n+TRANS(vffint_d_lu, LSX, gen_vv, gen_helper_vffint_d_lu)\n+TRANS(vffintl_d_w, LSX, gen_vv, gen_helper_vffintl_d_w)\n+TRANS(vffinth_d_w, LSX, gen_vv, gen_helper_vffinth_d_w)\n+TRANS(vffint_s_l, LSX, gen_vvv, gen_helper_vffint_s_l)\n \n static bool do_cmp(DisasContext *ctx, arg_vvv *a, MemOp mop, TCGCond cond)\n {\n@@ -3823,48 +3844,48 @@ static bool do_## NAME ##_u(DisasContext *ctx, arg_vv_i *a, MemOp mop) \\\n DO_CMPI_U(vslei)\n DO_CMPI_U(vslti)\n \n-TRANS(vseq_b, ALL, do_cmp, MO_8, TCG_COND_EQ)\n-TRANS(vseq_h, ALL, do_cmp, MO_16, TCG_COND_EQ)\n-TRANS(vseq_w, ALL, do_cmp, MO_32, TCG_COND_EQ)\n-TRANS(vseq_d, ALL, do_cmp, MO_64, TCG_COND_EQ)\n-TRANS(vseqi_b, ALL, do_vseqi_s, MO_8)\n-TRANS(vseqi_h, ALL, do_vseqi_s, MO_16)\n-TRANS(vseqi_w, ALL, do_vseqi_s, MO_32)\n-TRANS(vseqi_d, ALL, do_vseqi_s, MO_64)\n-\n-TRANS(vsle_b, ALL, do_cmp, MO_8, TCG_COND_LE)\n-TRANS(vsle_h, ALL, do_cmp, MO_16, TCG_COND_LE)\n-TRANS(vsle_w, ALL, do_cmp, MO_32, TCG_COND_LE)\n-TRANS(vsle_d, ALL, do_cmp, MO_64, TCG_COND_LE)\n-TRANS(vslei_b, ALL, do_vslei_s, MO_8)\n-TRANS(vslei_h, ALL, do_vslei_s, MO_16)\n-TRANS(vslei_w, ALL, do_vslei_s, MO_32)\n-TRANS(vslei_d, ALL, do_vslei_s, MO_64)\n-TRANS(vsle_bu, ALL, do_cmp, MO_8, TCG_COND_LEU)\n-TRANS(vsle_hu, ALL, do_cmp, MO_16, TCG_COND_LEU)\n-TRANS(vsle_wu, ALL, do_cmp, MO_32, TCG_COND_LEU)\n-TRANS(vsle_du, ALL, do_cmp, MO_64, TCG_COND_LEU)\n-TRANS(vslei_bu, ALL, do_vslei_u, MO_8)\n-TRANS(vslei_hu, ALL, do_vslei_u, MO_16)\n-TRANS(vslei_wu, ALL, do_vslei_u, MO_32)\n-TRANS(vslei_du, ALL, do_vslei_u, MO_64)\n-\n-TRANS(vslt_b, ALL, do_cmp, MO_8, TCG_COND_LT)\n-TRANS(vslt_h, ALL, do_cmp, MO_16, TCG_COND_LT)\n-TRANS(vslt_w, ALL, do_cmp, MO_32, TCG_COND_LT)\n-TRANS(vslt_d, ALL, do_cmp, MO_64, TCG_COND_LT)\n-TRANS(vslti_b, ALL, do_vslti_s, MO_8)\n-TRANS(vslti_h, ALL, do_vslti_s, MO_16)\n-TRANS(vslti_w, ALL, do_vslti_s, MO_32)\n-TRANS(vslti_d, ALL, do_vslti_s, MO_64)\n-TRANS(vslt_bu, ALL, do_cmp, MO_8, TCG_COND_LTU)\n-TRANS(vslt_hu, ALL, do_cmp, MO_16, TCG_COND_LTU)\n-TRANS(vslt_wu, ALL, do_cmp, MO_32, TCG_COND_LTU)\n-TRANS(vslt_du, ALL, do_cmp, MO_64, TCG_COND_LTU)\n-TRANS(vslti_bu, ALL, do_vslti_u, MO_8)\n-TRANS(vslti_hu, ALL, do_vslti_u, MO_16)\n-TRANS(vslti_wu, ALL, do_vslti_u, MO_32)\n-TRANS(vslti_du, ALL, do_vslti_u, MO_64)\n+TRANS(vseq_b, LSX, do_cmp, MO_8, TCG_COND_EQ)\n+TRANS(vseq_h, LSX, do_cmp, MO_16, TCG_COND_EQ)\n+TRANS(vseq_w, LSX, do_cmp, MO_32, TCG_COND_EQ)\n+TRANS(vseq_d, LSX, do_cmp, MO_64, TCG_COND_EQ)\n+TRANS(vseqi_b, LSX, do_vseqi_s, MO_8)\n+TRANS(vseqi_h, LSX, do_vseqi_s, MO_16)\n+TRANS(vseqi_w, LSX, do_vseqi_s, MO_32)\n+TRANS(vseqi_d, LSX, do_vseqi_s, MO_64)\n+\n+TRANS(vsle_b, LSX, do_cmp, MO_8, TCG_COND_LE)\n+TRANS(vsle_h, LSX, do_cmp, MO_16, TCG_COND_LE)\n+TRANS(vsle_w, LSX, do_cmp, MO_32, TCG_COND_LE)\n+TRANS(vsle_d, LSX, do_cmp, MO_64, TCG_COND_LE)\n+TRANS(vslei_b, LSX, do_vslei_s, MO_8)\n+TRANS(vslei_h, LSX, do_vslei_s, MO_16)\n+TRANS(vslei_w, LSX, do_vslei_s, MO_32)\n+TRANS(vslei_d, LSX, do_vslei_s, MO_64)\n+TRANS(vsle_bu, LSX, do_cmp, MO_8, TCG_COND_LEU)\n+TRANS(vsle_hu, LSX, do_cmp, MO_16, TCG_COND_LEU)\n+TRANS(vsle_wu, LSX, do_cmp, MO_32, TCG_COND_LEU)\n+TRANS(vsle_du, LSX, do_cmp, MO_64, TCG_COND_LEU)\n+TRANS(vslei_bu, LSX, do_vslei_u, MO_8)\n+TRANS(vslei_hu, LSX, do_vslei_u, MO_16)\n+TRANS(vslei_wu, LSX, do_vslei_u, MO_32)\n+TRANS(vslei_du, LSX, do_vslei_u, MO_64)\n+\n+TRANS(vslt_b, LSX, do_cmp, MO_8, TCG_COND_LT)\n+TRANS(vslt_h, LSX, do_cmp, MO_16, TCG_COND_LT)\n+TRANS(vslt_w, LSX, do_cmp, MO_32, TCG_COND_LT)\n+TRANS(vslt_d, LSX, do_cmp, MO_64, TCG_COND_LT)\n+TRANS(vslti_b, LSX, do_vslti_s, MO_8)\n+TRANS(vslti_h, LSX, do_vslti_s, MO_16)\n+TRANS(vslti_w, LSX, do_vslti_s, MO_32)\n+TRANS(vslti_d, LSX, do_vslti_s, MO_64)\n+TRANS(vslt_bu, LSX, do_cmp, MO_8, TCG_COND_LTU)\n+TRANS(vslt_hu, LSX, do_cmp, MO_16, TCG_COND_LTU)\n+TRANS(vslt_wu, LSX, do_cmp, MO_32, TCG_COND_LTU)\n+TRANS(vslt_du, LSX, do_cmp, MO_64, TCG_COND_LTU)\n+TRANS(vslti_bu, LSX, do_vslti_u, MO_8)\n+TRANS(vslti_hu, LSX, do_vslti_u, MO_16)\n+TRANS(vslti_wu, LSX, do_vslti_u, MO_32)\n+TRANS(vslti_du, LSX, do_vslti_u, MO_64)\n \n static bool trans_vfcmp_cond_s(DisasContext *ctx, arg_vvv_fcond *a)\n {\n@@ -3874,6 +3895,10 @@ static bool trans_vfcmp_cond_s(DisasContext *ctx, arg_vvv_fcond *a)\n TCGv_i32 vj = tcg_constant_i32(a->vj);\n TCGv_i32 vk = tcg_constant_i32(a->vk);\n \n+ if (!avail_LSX(ctx)) {\n+ return false;\n+ }\n+\n CHECK_SXE;\n \n fn = (a->fcond & 1 ? gen_helper_vfcmp_s_s : gen_helper_vfcmp_c_s);\n@@ -3891,6 +3916,12 @@ static bool trans_vfcmp_cond_d(DisasContext *ctx, arg_vvv_fcond *a)\n TCGv_i32 vj = tcg_constant_i32(a->vj);\n TCGv_i32 vk = tcg_constant_i32(a->vk);\n \n+ if (!avail_LSX(ctx)) {\n+ return false;\n+ }\n+\n+ CHECK_SXE;\n+\n fn = (a->fcond & 1 ? gen_helper_vfcmp_s_d : gen_helper_vfcmp_c_d);\n flags = get_fcmp_flags(a->fcond >> 1);\n fn(cpu_env, vd, vj, vk, tcg_constant_i32(flags));\n@@ -3900,6 +3931,10 @@ static bool trans_vfcmp_cond_d(DisasContext *ctx, arg_vvv_fcond *a)\n \n static bool trans_vbitsel_v(DisasContext *ctx, arg_vvvv *a)\n {\n+ if (!avail_LSX(ctx)) {\n+ return false;\n+ }\n+\n CHECK_SXE;\n \n tcg_gen_gvec_bitsel(MO_64, vec_full_offset(a->vd), vec_full_offset(a->va),\n@@ -3922,6 +3957,10 @@ static bool trans_vbitseli_b(DisasContext *ctx, arg_vv_i *a)\n .load_dest = true\n };\n \n+ if (!avail_LSX(ctx)) {\n+ return false;\n+ }\n+\n CHECK_SXE;\n \n tcg_gen_gvec_2i(vec_full_offset(a->vd), vec_full_offset(a->vj),\n@@ -3941,6 +3980,10 @@ static bool trans_## NAME (DisasContext *ctx, arg_cv *a) \\\n get_vreg64(ah, a->vj, 1); \\\n get_vreg64(al, a->vj, 0); \\\n \\\n+ if (!avail_LSX(ctx)) { \\\n+ return false; \\\n+ } \\\n+ \\\n CHECK_SXE; \\\n tcg_gen_or_i64(t1, al, ah); \\\n tcg_gen_setcondi_i64(COND, t1, t1, 0); \\\n@@ -3952,18 +3995,23 @@ static bool trans_## NAME (DisasContext *ctx, arg_cv *a) \\\n VSET(vseteqz_v, TCG_COND_EQ)\n VSET(vsetnez_v, TCG_COND_NE)\n \n-TRANS(vsetanyeqz_b, ALL, gen_cv, gen_helper_vsetanyeqz_b)\n-TRANS(vsetanyeqz_h, ALL, gen_cv, gen_helper_vsetanyeqz_h)\n-TRANS(vsetanyeqz_w, ALL, gen_cv, gen_helper_vsetanyeqz_w)\n-TRANS(vsetanyeqz_d, ALL, gen_cv, gen_helper_vsetanyeqz_d)\n-TRANS(vsetallnez_b, ALL, gen_cv, gen_helper_vsetallnez_b)\n-TRANS(vsetallnez_h, ALL, gen_cv, gen_helper_vsetallnez_h)\n-TRANS(vsetallnez_w, ALL, gen_cv, gen_helper_vsetallnez_w)\n-TRANS(vsetallnez_d, ALL, gen_cv, gen_helper_vsetallnez_d)\n+TRANS(vsetanyeqz_b, LSX, gen_cv, gen_helper_vsetanyeqz_b)\n+TRANS(vsetanyeqz_h, LSX, gen_cv, gen_helper_vsetanyeqz_h)\n+TRANS(vsetanyeqz_w, LSX, gen_cv, gen_helper_vsetanyeqz_w)\n+TRANS(vsetanyeqz_d, LSX, gen_cv, gen_helper_vsetanyeqz_d)\n+TRANS(vsetallnez_b, LSX, gen_cv, gen_helper_vsetallnez_b)\n+TRANS(vsetallnez_h, LSX, gen_cv, gen_helper_vsetallnez_h)\n+TRANS(vsetallnez_w, LSX, gen_cv, gen_helper_vsetallnez_w)\n+TRANS(vsetallnez_d, LSX, gen_cv, gen_helper_vsetallnez_d)\n \n static bool trans_vinsgr2vr_b(DisasContext *ctx, arg_vr_i *a)\n {\n TCGv src = gpr_src(ctx, a->rj, EXT_NONE);\n+\n+ if (!avail_LSX(ctx)) {\n+ return false;\n+ }\n+\n CHECK_SXE;\n tcg_gen_st8_i64(src, cpu_env,\n offsetof(CPULoongArchState, fpr[a->vd].vreg.B(a->imm)));\n@@ -3973,6 +4021,11 @@ static bool trans_vinsgr2vr_b(DisasContext *ctx, arg_vr_i *a)\n static bool trans_vinsgr2vr_h(DisasContext *ctx, arg_vr_i *a)\n {\n TCGv src = gpr_src(ctx, a->rj, EXT_NONE);\n+\n+ if (!avail_LSX(ctx)) {\n+ return false;\n+ }\n+\n CHECK_SXE;\n tcg_gen_st16_i64(src, cpu_env,\n offsetof(CPULoongArchState, fpr[a->vd].vreg.H(a->imm)));\n@@ -3982,6 +4035,11 @@ static bool trans_vinsgr2vr_h(DisasContext *ctx, arg_vr_i *a)\n static bool trans_vinsgr2vr_w(DisasContext *ctx, arg_vr_i *a)\n {\n TCGv src = gpr_src(ctx, a->rj, EXT_NONE);\n+\n+ if (!avail_LSX(ctx)) {\n+ return false;\n+ }\n+\n CHECK_SXE;\n tcg_gen_st32_i64(src, cpu_env,\n offsetof(CPULoongArchState, fpr[a->vd].vreg.W(a->imm)));\n@@ -3991,6 +4049,11 @@ static bool trans_vinsgr2vr_w(DisasContext *ctx, arg_vr_i *a)\n static bool trans_vinsgr2vr_d(DisasContext *ctx, arg_vr_i *a)\n {\n TCGv src = gpr_src(ctx, a->rj, EXT_NONE);\n+\n+ if (!avail_LSX(ctx)) {\n+ return false;\n+ }\n+\n CHECK_SXE;\n tcg_gen_st_i64(src, cpu_env,\n offsetof(CPULoongArchState, fpr[a->vd].vreg.D(a->imm)));\n@@ -4000,6 +4063,11 @@ static bool trans_vinsgr2vr_d(DisasContext *ctx, arg_vr_i *a)\n static bool trans_vpickve2gr_b(DisasContext *ctx, arg_rv_i *a)\n {\n TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);\n+\n+ if (!avail_LSX(ctx)) {\n+ return false;\n+ }\n+\n CHECK_SXE;\n tcg_gen_ld8s_i64(dst, cpu_env,\n offsetof(CPULoongArchState, fpr[a->vj].vreg.B(a->imm)));\n@@ -4009,6 +4077,11 @@ static bool trans_vpickve2gr_b(DisasContext *ctx, arg_rv_i *a)\n static bool trans_vpickve2gr_h(DisasContext *ctx, arg_rv_i *a)\n {\n TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);\n+\n+ if (!avail_LSX(ctx)) {\n+ return false;\n+ }\n+\n CHECK_SXE;\n tcg_gen_ld16s_i64(dst, cpu_env,\n offsetof(CPULoongArchState, fpr[a->vj].vreg.H(a->imm)));\n@@ -4018,6 +4091,11 @@ static bool trans_vpickve2gr_h(DisasContext *ctx, arg_rv_i *a)\n static bool trans_vpickve2gr_w(DisasContext *ctx, arg_rv_i *a)\n {\n TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);\n+\n+ if (!avail_LSX(ctx)) {\n+ return false;\n+ }\n+\n CHECK_SXE;\n tcg_gen_ld32s_i64(dst, cpu_env,\n offsetof(CPULoongArchState, fpr[a->vj].vreg.W(a->imm)));\n@@ -4027,6 +4105,11 @@ static bool trans_vpickve2gr_w(DisasContext *ctx, arg_rv_i *a)\n static bool trans_vpickve2gr_d(DisasContext *ctx, arg_rv_i *a)\n {\n TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);\n+\n+ if (!avail_LSX(ctx)) {\n+ return false;\n+ }\n+\n CHECK_SXE;\n tcg_gen_ld_i64(dst, cpu_env,\n offsetof(CPULoongArchState, fpr[a->vj].vreg.D(a->imm)));\n@@ -4036,6 +4119,11 @@ static bool trans_vpickve2gr_d(DisasContext *ctx, arg_rv_i *a)\n static bool trans_vpickve2gr_bu(DisasContext *ctx, arg_rv_i *a)\n {\n TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);\n+\n+ if (!avail_LSX(ctx)) {\n+ return false;\n+ }\n+\n CHECK_SXE;\n tcg_gen_ld8u_i64(dst, cpu_env,\n offsetof(CPULoongArchState, fpr[a->vj].vreg.B(a->imm)));\n@@ -4045,6 +4133,11 @@ static bool trans_vpickve2gr_bu(DisasContext *ctx, arg_rv_i *a)\n static bool trans_vpickve2gr_hu(DisasContext *ctx, arg_rv_i *a)\n {\n TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);\n+\n+ if (!avail_LSX(ctx)) {\n+ return false;\n+ }\n+\n CHECK_SXE;\n tcg_gen_ld16u_i64(dst, cpu_env,\n offsetof(CPULoongArchState, fpr[a->vj].vreg.H(a->imm)));\n@@ -4054,6 +4147,11 @@ static bool trans_vpickve2gr_hu(DisasContext *ctx, arg_rv_i *a)\n static bool trans_vpickve2gr_wu(DisasContext *ctx, arg_rv_i *a)\n {\n TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);\n+\n+ if (!avail_LSX(ctx)) {\n+ return false;\n+ }\n+\n CHECK_SXE;\n tcg_gen_ld32u_i64(dst, cpu_env,\n offsetof(CPULoongArchState, fpr[a->vj].vreg.W(a->imm)));\n@@ -4063,6 +4161,11 @@ static bool trans_vpickve2gr_wu(DisasContext *ctx, arg_rv_i *a)\n static bool trans_vpickve2gr_du(DisasContext *ctx, arg_rv_i *a)\n {\n TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE);\n+\n+ if (!avail_LSX(ctx)) {\n+ return false;\n+ }\n+\n CHECK_SXE;\n tcg_gen_ld_i64(dst, cpu_env,\n offsetof(CPULoongArchState, fpr[a->vj].vreg.D(a->imm)));\n@@ -4072,6 +4175,11 @@ static bool trans_vpickve2gr_du(DisasContext *ctx, arg_rv_i *a)\n static bool gvec_dup(DisasContext *ctx, arg_vr *a, MemOp mop)\n {\n TCGv src = gpr_src(ctx, a->rj, EXT_NONE);\n+\n+ if (!avail_LSX(ctx)) {\n+ return false;\n+ }\n+\n CHECK_SXE;\n \n tcg_gen_gvec_dup_i64(mop, vec_full_offset(a->vd),\n@@ -4079,13 +4187,17 @@ static bool gvec_dup(DisasContext *ctx, arg_vr *a, MemOp mop)\n return true;\n }\n \n-TRANS(vreplgr2vr_b, ALL, gvec_dup, MO_8)\n-TRANS(vreplgr2vr_h, ALL, gvec_dup, MO_16)\n-TRANS(vreplgr2vr_w, ALL, gvec_dup, MO_32)\n-TRANS(vreplgr2vr_d, ALL, gvec_dup, MO_64)\n+TRANS(vreplgr2vr_b, LSX, gvec_dup, MO_8)\n+TRANS(vreplgr2vr_h, LSX, gvec_dup, MO_16)\n+TRANS(vreplgr2vr_w, LSX, gvec_dup, MO_32)\n+TRANS(vreplgr2vr_d, LSX, gvec_dup, MO_64)\n \n static bool trans_vreplvei_b(DisasContext *ctx, arg_vv_i *a)\n {\n+ if (!avail_LSX(ctx)) {\n+ return false;\n+ }\n+\n CHECK_SXE;\n tcg_gen_gvec_dup_mem(MO_8,vec_full_offset(a->vd),\n offsetof(CPULoongArchState,\n@@ -4096,6 +4208,10 @@ static bool trans_vreplvei_b(DisasContext *ctx, arg_vv_i *a)\n \n static bool trans_vreplvei_h(DisasContext *ctx, arg_vv_i *a)\n {\n+ if (!avail_LSX(ctx)) {\n+ return false;\n+ }\n+\n CHECK_SXE;\n tcg_gen_gvec_dup_mem(MO_16, vec_full_offset(a->vd),\n offsetof(CPULoongArchState,\n@@ -4105,6 +4221,10 @@ static bool trans_vreplvei_h(DisasContext *ctx, arg_vv_i *a)\n }\n static bool trans_vreplvei_w(DisasContext *ctx, arg_vv_i *a)\n {\n+ if (!avail_LSX(ctx)) {\n+ return false;\n+ }\n+\n CHECK_SXE;\n tcg_gen_gvec_dup_mem(MO_32, vec_full_offset(a->vd),\n offsetof(CPULoongArchState,\n@@ -4114,6 +4234,10 @@ static bool trans_vreplvei_w(DisasContext *ctx, arg_vv_i *a)\n }\n static bool trans_vreplvei_d(DisasContext *ctx, arg_vv_i *a)\n {\n+ if (!avail_LSX(ctx)) {\n+ return false;\n+ }\n+\n CHECK_SXE;\n tcg_gen_gvec_dup_mem(MO_64, vec_full_offset(a->vd),\n offsetof(CPULoongArchState,\n@@ -4129,6 +4253,10 @@ static bool gen_vreplve(DisasContext *ctx, arg_vvr *a, int vece, int bit,\n TCGv_ptr t1 = tcg_temp_new_ptr();\n TCGv_i64 t2 = tcg_temp_new_i64();\n \n+ if (!avail_LSX(ctx)) {\n+ return false;\n+ }\n+\n CHECK_SXE;\n \n tcg_gen_andi_i64(t0, gpr_src(ctx, a->rk, EXT_NONE), (LSX_LEN/bit) -1);\n@@ -4145,16 +4273,20 @@ static bool gen_vreplve(DisasContext *ctx, arg_vvr *a, int vece, int bit,\n return true;\n }\n \n-TRANS(vreplve_b, ALL, gen_vreplve, MO_8, 8, tcg_gen_ld8u_i64)\n-TRANS(vreplve_h, ALL, gen_vreplve, MO_16, 16, tcg_gen_ld16u_i64)\n-TRANS(vreplve_w, ALL, gen_vreplve, MO_32, 32, tcg_gen_ld32u_i64)\n-TRANS(vreplve_d, ALL, gen_vreplve, MO_64, 64, tcg_gen_ld_i64)\n+TRANS(vreplve_b, LSX, gen_vreplve, MO_8, 8, tcg_gen_ld8u_i64)\n+TRANS(vreplve_h, LSX, gen_vreplve, MO_16, 16, tcg_gen_ld16u_i64)\n+TRANS(vreplve_w, LSX, gen_vreplve, MO_32, 32, tcg_gen_ld32u_i64)\n+TRANS(vreplve_d, LSX, gen_vreplve, MO_64, 64, tcg_gen_ld_i64)\n \n static bool trans_vbsll_v(DisasContext *ctx, arg_vv_i *a)\n {\n int ofs;\n TCGv_i64 desthigh, destlow, high, low;\n \n+ if (!avail_LSX(ctx)) {\n+ return false;\n+ }\n+\n CHECK_SXE;\n \n desthigh = tcg_temp_new_i64();\n@@ -4185,6 +4317,10 @@ static bool trans_vbsrl_v(DisasContext *ctx, arg_vv_i *a)\n TCGv_i64 desthigh, destlow, high, low;\n int ofs;\n \n+ if (!avail_LSX(ctx)) {\n+ return false;\n+ }\n+\n CHECK_SXE;\n \n desthigh = tcg_temp_new_i64();\n@@ -4210,48 +4346,48 @@ static bool trans_vbsrl_v(DisasContext *ctx, arg_vv_i *a)\n return true;\n }\n \n-TRANS(vpackev_b, ALL, gen_vvv, gen_helper_vpackev_b)\n-TRANS(vpackev_h, ALL, gen_vvv, gen_helper_vpackev_h)\n-TRANS(vpackev_w, ALL, gen_vvv, gen_helper_vpackev_w)\n-TRANS(vpackev_d, ALL, gen_vvv, gen_helper_vpackev_d)\n-TRANS(vpackod_b, ALL, gen_vvv, gen_helper_vpackod_b)\n-TRANS(vpackod_h, ALL, gen_vvv, gen_helper_vpackod_h)\n-TRANS(vpackod_w, ALL, gen_vvv, gen_helper_vpackod_w)\n-TRANS(vpackod_d, ALL, gen_vvv, gen_helper_vpackod_d)\n-\n-TRANS(vpickev_b, ALL, gen_vvv, gen_helper_vpickev_b)\n-TRANS(vpickev_h, ALL, gen_vvv, gen_helper_vpickev_h)\n-TRANS(vpickev_w, ALL, gen_vvv, gen_helper_vpickev_w)\n-TRANS(vpickev_d, ALL, gen_vvv, gen_helper_vpickev_d)\n-TRANS(vpickod_b, ALL, gen_vvv, gen_helper_vpickod_b)\n-TRANS(vpickod_h, ALL, gen_vvv, gen_helper_vpickod_h)\n-TRANS(vpickod_w, ALL, gen_vvv, gen_helper_vpickod_w)\n-TRANS(vpickod_d, ALL, gen_vvv, gen_helper_vpickod_d)\n-\n-TRANS(vilvl_b, ALL, gen_vvv, gen_helper_vilvl_b)\n-TRANS(vilvl_h, ALL, gen_vvv, gen_helper_vilvl_h)\n-TRANS(vilvl_w, ALL, gen_vvv, gen_helper_vilvl_w)\n-TRANS(vilvl_d, ALL, gen_vvv, gen_helper_vilvl_d)\n-TRANS(vilvh_b, ALL, gen_vvv, gen_helper_vilvh_b)\n-TRANS(vilvh_h, ALL, gen_vvv, gen_helper_vilvh_h)\n-TRANS(vilvh_w, ALL, gen_vvv, gen_helper_vilvh_w)\n-TRANS(vilvh_d, ALL, gen_vvv, gen_helper_vilvh_d)\n-\n-TRANS(vshuf_b, ALL, gen_vvvv, gen_helper_vshuf_b)\n-TRANS(vshuf_h, ALL, gen_vvv, gen_helper_vshuf_h)\n-TRANS(vshuf_w, ALL, gen_vvv, gen_helper_vshuf_w)\n-TRANS(vshuf_d, ALL, gen_vvv, gen_helper_vshuf_d)\n-TRANS(vshuf4i_b, ALL, gen_vv_i, gen_helper_vshuf4i_b)\n-TRANS(vshuf4i_h, ALL, gen_vv_i, gen_helper_vshuf4i_h)\n-TRANS(vshuf4i_w, ALL, gen_vv_i, gen_helper_vshuf4i_w)\n-TRANS(vshuf4i_d, ALL, gen_vv_i, gen_helper_vshuf4i_d)\n-\n-TRANS(vpermi_w, ALL, gen_vv_i, gen_helper_vpermi_w)\n-\n-TRANS(vextrins_b, ALL, gen_vv_i, gen_helper_vextrins_b)\n-TRANS(vextrins_h, ALL, gen_vv_i, gen_helper_vextrins_h)\n-TRANS(vextrins_w, ALL, gen_vv_i, gen_helper_vextrins_w)\n-TRANS(vextrins_d, ALL, gen_vv_i, gen_helper_vextrins_d)\n+TRANS(vpackev_b, LSX, gen_vvv, gen_helper_vpackev_b)\n+TRANS(vpackev_h, LSX, gen_vvv, gen_helper_vpackev_h)\n+TRANS(vpackev_w, LSX, gen_vvv, gen_helper_vpackev_w)\n+TRANS(vpackev_d, LSX, gen_vvv, gen_helper_vpackev_d)\n+TRANS(vpackod_b, LSX, gen_vvv, gen_helper_vpackod_b)\n+TRANS(vpackod_h, LSX, gen_vvv, gen_helper_vpackod_h)\n+TRANS(vpackod_w, LSX, gen_vvv, gen_helper_vpackod_w)\n+TRANS(vpackod_d, LSX, gen_vvv, gen_helper_vpackod_d)\n+\n+TRANS(vpickev_b, LSX, gen_vvv, gen_helper_vpickev_b)\n+TRANS(vpickev_h, LSX, gen_vvv, gen_helper_vpickev_h)\n+TRANS(vpickev_w, LSX, gen_vvv, gen_helper_vpickev_w)\n+TRANS(vpickev_d, LSX, gen_vvv, gen_helper_vpickev_d)\n+TRANS(vpickod_b, LSX, gen_vvv, gen_helper_vpickod_b)\n+TRANS(vpickod_h, LSX, gen_vvv, gen_helper_vpickod_h)\n+TRANS(vpickod_w, LSX, gen_vvv, gen_helper_vpickod_w)\n+TRANS(vpickod_d, LSX, gen_vvv, gen_helper_vpickod_d)\n+\n+TRANS(vilvl_b, LSX, gen_vvv, gen_helper_vilvl_b)\n+TRANS(vilvl_h, LSX, gen_vvv, gen_helper_vilvl_h)\n+TRANS(vilvl_w, LSX, gen_vvv, gen_helper_vilvl_w)\n+TRANS(vilvl_d, LSX, gen_vvv, gen_helper_vilvl_d)\n+TRANS(vilvh_b, LSX, gen_vvv, gen_helper_vilvh_b)\n+TRANS(vilvh_h, LSX, gen_vvv, gen_helper_vilvh_h)\n+TRANS(vilvh_w, LSX, gen_vvv, gen_helper_vilvh_w)\n+TRANS(vilvh_d, LSX, gen_vvv, gen_helper_vilvh_d)\n+\n+TRANS(vshuf_b, LSX, gen_vvvv, gen_helper_vshuf_b)\n+TRANS(vshuf_h, LSX, gen_vvv, gen_helper_vshuf_h)\n+TRANS(vshuf_w, LSX, gen_vvv, gen_helper_vshuf_w)\n+TRANS(vshuf_d, LSX, gen_vvv, gen_helper_vshuf_d)\n+TRANS(vshuf4i_b, LSX, gen_vv_i, gen_helper_vshuf4i_b)\n+TRANS(vshuf4i_h, LSX, gen_vv_i, gen_helper_vshuf4i_h)\n+TRANS(vshuf4i_w, LSX, gen_vv_i, gen_helper_vshuf4i_w)\n+TRANS(vshuf4i_d, LSX, gen_vv_i, gen_helper_vshuf4i_d)\n+\n+TRANS(vpermi_w, LSX, gen_vv_i, gen_helper_vpermi_w)\n+\n+TRANS(vextrins_b, LSX, gen_vv_i, gen_helper_vextrins_b)\n+TRANS(vextrins_h, LSX, gen_vv_i, gen_helper_vextrins_h)\n+TRANS(vextrins_w, LSX, gen_vv_i, gen_helper_vextrins_w)\n+TRANS(vextrins_d, LSX, gen_vv_i, gen_helper_vextrins_d)\n \n static bool trans_vld(DisasContext *ctx, arg_vr_i *a)\n {\n@@ -4259,6 +4395,10 @@ static bool trans_vld(DisasContext *ctx, arg_vr_i *a)\n TCGv_i64 rl, rh;\n TCGv_i128 val;\n \n+ if (!avail_LSX(ctx)) {\n+ return false;\n+ }\n+\n CHECK_SXE;\n \n addr = gpr_src(ctx, a->rj, EXT_NONE);\n@@ -4282,6 +4422,10 @@ static bool trans_vst(DisasContext *ctx, arg_vr_i *a)\n TCGv_i128 val;\n TCGv_i64 ah, al;\n \n+ if (!avail_LSX(ctx)) {\n+ return false;\n+ }\n+\n CHECK_SXE;\n \n addr = gpr_src(ctx, a->rj, EXT_NONE);\n@@ -4305,6 +4449,10 @@ static bool trans_vldx(DisasContext *ctx, arg_vrr *a)\n TCGv_i64 rl, rh;\n TCGv_i128 val;\n \n+ if (!avail_LSX(ctx)) {\n+ return false;\n+ }\n+\n CHECK_SXE;\n \n src1 = gpr_src(ctx, a->rj, EXT_NONE);\n@@ -4328,6 +4476,10 @@ static bool trans_vstx(DisasContext *ctx, arg_vrr *a)\n TCGv_i64 ah, al;\n TCGv_i128 val;\n \n+ if (!avail_LSX(ctx)) {\n+ return false;\n+ }\n+\n CHECK_SXE;\n \n src1 = gpr_src(ctx, a->rj, EXT_NONE);\n@@ -4351,6 +4503,10 @@ static bool trans_## NAME (DisasContext *ctx, arg_vr_i *a) \\\n TCGv addr; \\\n TCGv_i64 val; \\\n \\\n+ if (!avail_LSX(ctx)) { \\\n+ return false; \\\n+ } \\\n+ \\\n CHECK_SXE; \\\n \\\n addr = gpr_src(ctx, a->rj, EXT_NONE); \\\n@@ -4375,6 +4531,10 @@ static bool trans_## NAME (DisasContext *ctx, arg_vr_ii *a) \\\n TCGv addr; \\\n TCGv_i64 val; \\\n \\\n+ if (!avail_LSX(ctx)) { \\\n+ return false; \\\n+ } \\\n+ \\\n CHECK_SXE; \\\n \\\n addr = gpr_src(ctx, a->rj, EXT_NONE); \\\ndiff --git a/target/loongarch/translate.h b/target/loongarch/translate.h\nindex faf4ce87f9..db46e9aa0f 100644\n--- a/target/loongarch/translate.h\n+++ b/target/loongarch/translate.h\n@@ -22,6 +22,8 @@\n #define avail_FP_DP(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, FP_DP))\n #define avail_LSPW(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSPW))\n #define avail_LAM(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LAM))\n+#define avail_LSX(C) (FIELD_EX32((C)->cpucfg2, CPUCFG2, LSX))\n+\n \n /*\n * If an operation is being performed on less than TARGET_LONG_BITS,\n", "prefixes": [ "PULL", "26/31" ] }