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GET /api/patches/1825222/?format=api
{ "id": 1825222, "url": "http://patchwork.ozlabs.org/api/patches/1825222/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20230824092409.1492470-21-gaosong@loongson.cn/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20230824092409.1492470-21-gaosong@loongson.cn>", "list_archive_url": null, "date": "2023-08-24T09:23:58", "name": "[PULL,20/31] target/loongarch: Add avail_64 to check la64-only instructions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "611c636cae45ae3e739379dc0da0c415c6895e83", "submitter": { "id": 82024, "url": "http://patchwork.ozlabs.org/api/people/82024/?format=api", "name": "gaosong", "email": "gaosong@loongson.cn" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20230824092409.1492470-21-gaosong@loongson.cn/mbox/", "series": [ { "id": 370173, "url": "http://patchwork.ozlabs.org/api/series/370173/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=370173", "date": "2023-08-24T09:23:41", "name": "[PULL,01/31] target/loongarch: Log I/O write accesses to CSR registers", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/370173/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1825222/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1825222/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)", "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4RWd4F2d4kz1yfF\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 24 Aug 2023 19:26:05 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1qZ6an-0005PX-9O; Thu, 24 Aug 2023 05:25:29 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <gaosong@loongson.cn>)\n id 1qZ6aH-0004CE-BP\n for qemu-devel@nongnu.org; Thu, 24 Aug 2023 05:24:59 -0400", "from mail.loongson.cn ([114.242.206.163])\n by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from <gaosong@loongson.cn>) id 1qZ6a9-0003iU-Q2\n for qemu-devel@nongnu.org; Thu, 24 Aug 2023 05:24:54 -0400", "from loongson.cn (unknown [10.2.5.185])\n by gateway (Coremail) with SMTP id _____8Cx5_HFIedkfXkbAA--.56039S3;\n Thu, 24 Aug 2023 17:24:21 +0800 (CST)", "from localhost.localdomain (unknown [10.2.5.185])\n by localhost.localdomain (Coremail) with SMTP id\n AQAAf8DxJ826IedkJjhiAA--.40637S22;\n Thu, 24 Aug 2023 17:24:20 +0800 (CST)" ], "From": "Song Gao <gaosong@loongson.cn>", "To": "qemu-devel@nongnu.org", "Cc": "stefanha@redhat.com, richard.henderson@linaro.org, Jiajie Chen <c@jia.je>", "Subject": "[PULL 20/31] target/loongarch: Add avail_64 to check la64-only\n instructions", "Date": "Thu, 24 Aug 2023 17:23:58 +0800", "Message-Id": "<20230824092409.1492470-21-gaosong@loongson.cn>", "X-Mailer": "git-send-email 2.39.1", "In-Reply-To": "<20230824092409.1492470-1-gaosong@loongson.cn>", "References": "<20230824092409.1492470-1-gaosong@loongson.cn>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-CM-TRANSID": "AQAAf8DxJ826IedkJjhiAA--.40637S22", "X-CM-SenderInfo": "5jdr20tqj6z05rqj20fqof0/", "X-Coremail-Antispam": "1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7\n ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx\n nUUI43ZEXa7xR_UUUUUUUUU==", "Received-SPF": "pass client-ip=114.242.206.163;\n envelope-from=gaosong@loongson.cn;\n helo=mail.loongson.cn", "X-Spam_score_int": "-18", "X-Spam_score": "-1.9", "X-Spam_bar": "-", "X-Spam_report": "(-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "The la32 instructions listed in Table 2 at\nhttps://loongson.github.io/LoongArch-Documentation/LoongArch-Vol1-EN.html#overview-of-basic-integer-instructions\n\nCo-authored-by: Jiajie Chen <c@jia.je>\nSigned-off-by: Song Gao <gaosong@loongson.cn>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nMessage-ID: <20230822032724.1353391-9-gaosong@loongson.cn>\nMessage-Id: <20230822071959.35620-3-philmd@linaro.org>\n---\n target/loongarch/insn_trans/trans_arith.c.inc | 42 ++++++----\n .../loongarch/insn_trans/trans_atomic.c.inc | 76 +++++++++----------\n target/loongarch/insn_trans/trans_bit.c.inc | 28 +++----\n .../loongarch/insn_trans/trans_branch.c.inc | 4 +-\n target/loongarch/insn_trans/trans_extra.c.inc | 24 ++++--\n target/loongarch/insn_trans/trans_fmov.c.inc | 4 +-\n .../loongarch/insn_trans/trans_memory.c.inc | 68 ++++++++---------\n target/loongarch/insn_trans/trans_shift.c.inc | 24 +++---\n target/loongarch/translate.c | 2 +\n target/loongarch/translate.h | 3 +\n 10 files changed, 152 insertions(+), 123 deletions(-)", "diff": "diff --git a/target/loongarch/insn_trans/trans_arith.c.inc b/target/loongarch/insn_trans/trans_arith.c.inc\nindex d7f69a7553..2be057e932 100644\n--- a/target/loongarch/insn_trans/trans_arith.c.inc\n+++ b/target/loongarch/insn_trans/trans_arith.c.inc\n@@ -199,6 +199,10 @@ static bool trans_lu32i_d(DisasContext *ctx, arg_lu32i_d *a)\n TCGv src1 = gpr_src(ctx, a->rd, EXT_NONE);\n TCGv src2 = tcg_constant_tl(a->imm);\n \n+ if (!avail_64(ctx)) {\n+ return false;\n+ }\n+\n tcg_gen_deposit_tl(dest, src1, src2, 32, 32);\n gen_set_gpr(a->rd, dest, EXT_NONE);\n \n@@ -211,6 +215,10 @@ static bool trans_lu52i_d(DisasContext *ctx, arg_lu52i_d *a)\n TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);\n TCGv src2 = tcg_constant_tl(a->imm);\n \n+ if (!avail_64(ctx)) {\n+ return false;\n+ }\n+\n tcg_gen_deposit_tl(dest, src1, src2, 52, 12);\n gen_set_gpr(a->rd, dest, EXT_NONE);\n \n@@ -242,6 +250,10 @@ static bool trans_addu16i_d(DisasContext *ctx, arg_addu16i_d *a)\n TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);\n TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);\n \n+ if (!avail_64(ctx)) {\n+ return false;\n+ }\n+\n tcg_gen_addi_tl(dest, src1, a->imm << 16);\n gen_set_gpr(a->rd, dest, EXT_NONE);\n \n@@ -249,9 +261,9 @@ static bool trans_addu16i_d(DisasContext *ctx, arg_addu16i_d *a)\n }\n \n TRANS(add_w, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_SIGN, tcg_gen_add_tl)\n-TRANS(add_d, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_add_tl)\n+TRANS(add_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_add_tl)\n TRANS(sub_w, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_SIGN, tcg_gen_sub_tl)\n-TRANS(sub_d, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_sub_tl)\n+TRANS(sub_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_sub_tl)\n TRANS(and, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_and_tl)\n TRANS(or, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_or_tl)\n TRANS(xor, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_xor_tl)\n@@ -261,32 +273,32 @@ TRANS(orn, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_orc_tl)\n TRANS(slt, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_slt)\n TRANS(sltu, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sltu)\n TRANS(mul_w, ALL, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_SIGN, tcg_gen_mul_tl)\n-TRANS(mul_d, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_mul_tl)\n+TRANS(mul_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_mul_tl)\n TRANS(mulh_w, ALL, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_NONE, gen_mulh_w)\n TRANS(mulh_wu, ALL, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_NONE, gen_mulh_w)\n-TRANS(mulh_d, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_mulh_d)\n-TRANS(mulh_du, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_mulh_du)\n-TRANS(mulw_d_w, ALL, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_NONE, tcg_gen_mul_tl)\n-TRANS(mulw_d_wu, ALL, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_NONE, tcg_gen_mul_tl)\n+TRANS(mulh_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_mulh_d)\n+TRANS(mulh_du, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_mulh_du)\n+TRANS(mulw_d_w, 64, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_NONE, tcg_gen_mul_tl)\n+TRANS(mulw_d_wu, 64, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_NONE, tcg_gen_mul_tl)\n TRANS(div_w, ALL, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_SIGN, gen_div_w)\n TRANS(mod_w, ALL, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_SIGN, gen_rem_w)\n TRANS(div_wu, ALL, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_SIGN, gen_div_du)\n TRANS(mod_wu, ALL, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_SIGN, gen_rem_du)\n-TRANS(div_d, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_div_d)\n-TRANS(mod_d, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rem_d)\n-TRANS(div_du, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_div_du)\n-TRANS(mod_du, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rem_du)\n+TRANS(div_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_div_d)\n+TRANS(mod_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rem_d)\n+TRANS(div_du, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_div_du)\n+TRANS(mod_du, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rem_du)\n TRANS(slti, ALL, gen_rri_v, EXT_NONE, EXT_NONE, gen_slt)\n TRANS(sltui, ALL, gen_rri_v, EXT_NONE, EXT_NONE, gen_sltu)\n TRANS(addi_w, ALL, gen_rri_c, EXT_NONE, EXT_SIGN, tcg_gen_addi_tl)\n-TRANS(addi_d, ALL, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_addi_tl)\n+TRANS(addi_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_addi_tl)\n TRANS(alsl_w, ALL, gen_rrr_sa, EXT_NONE, EXT_SIGN, gen_alsl)\n-TRANS(alsl_wu, ALL, gen_rrr_sa, EXT_NONE, EXT_ZERO, gen_alsl)\n-TRANS(alsl_d, ALL, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_alsl)\n+TRANS(alsl_wu, 64, gen_rrr_sa, EXT_NONE, EXT_ZERO, gen_alsl)\n+TRANS(alsl_d, 64, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_alsl)\n TRANS(pcaddi, ALL, gen_pc, gen_pcaddi)\n TRANS(pcalau12i, ALL, gen_pc, gen_pcalau12i)\n TRANS(pcaddu12i, ALL, gen_pc, gen_pcaddu12i)\n-TRANS(pcaddu18i, ALL, gen_pc, gen_pcaddu18i)\n+TRANS(pcaddu18i, 64, gen_pc, gen_pcaddu18i)\n TRANS(andi, ALL, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_andi_tl)\n TRANS(ori, ALL, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_ori_tl)\n TRANS(xori, ALL, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_xori_tl)\ndiff --git a/target/loongarch/insn_trans/trans_atomic.c.inc b/target/loongarch/insn_trans/trans_atomic.c.inc\nindex 0a02f0dbf3..194818d74d 100644\n--- a/target/loongarch/insn_trans/trans_atomic.c.inc\n+++ b/target/loongarch/insn_trans/trans_atomic.c.inc\n@@ -71,41 +71,41 @@ static bool gen_am(DisasContext *ctx, arg_rrr *a,\n \n TRANS(ll_w, ALL, gen_ll, MO_TESL)\n TRANS(sc_w, ALL, gen_sc, MO_TESL)\n-TRANS(ll_d, ALL, gen_ll, MO_TEUQ)\n-TRANS(sc_d, ALL, gen_sc, MO_TEUQ)\n-TRANS(amswap_w, ALL, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL)\n-TRANS(amswap_d, ALL, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ)\n-TRANS(amadd_w, ALL, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL)\n-TRANS(amadd_d, ALL, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ)\n-TRANS(amand_w, ALL, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL)\n-TRANS(amand_d, ALL, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ)\n-TRANS(amor_w, ALL, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL)\n-TRANS(amor_d, ALL, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ)\n-TRANS(amxor_w, ALL, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL)\n-TRANS(amxor_d, ALL, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ)\n-TRANS(ammax_w, ALL, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL)\n-TRANS(ammax_d, ALL, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ)\n-TRANS(ammin_w, ALL, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL)\n-TRANS(ammin_d, ALL, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ)\n-TRANS(ammax_wu, ALL, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL)\n-TRANS(ammax_du, ALL, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ)\n-TRANS(ammin_wu, ALL, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL)\n-TRANS(ammin_du, ALL, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ)\n-TRANS(amswap_db_w, ALL, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL)\n-TRANS(amswap_db_d, ALL, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ)\n-TRANS(amadd_db_w, ALL, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL)\n-TRANS(amadd_db_d, ALL, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ)\n-TRANS(amand_db_w, ALL, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL)\n-TRANS(amand_db_d, ALL, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ)\n-TRANS(amor_db_w, ALL, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL)\n-TRANS(amor_db_d, ALL, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ)\n-TRANS(amxor_db_w, ALL, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL)\n-TRANS(amxor_db_d, ALL, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ)\n-TRANS(ammax_db_w, ALL, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL)\n-TRANS(ammax_db_d, ALL, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ)\n-TRANS(ammin_db_w, ALL, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL)\n-TRANS(ammin_db_d, ALL, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ)\n-TRANS(ammax_db_wu, ALL, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL)\n-TRANS(ammax_db_du, ALL, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ)\n-TRANS(ammin_db_wu, ALL, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL)\n-TRANS(ammin_db_du, ALL, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ)\n+TRANS(ll_d, 64, gen_ll, MO_TEUQ)\n+TRANS(sc_d, 64, gen_sc, MO_TEUQ)\n+TRANS(amswap_w, 64, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL)\n+TRANS(amswap_d, 64, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ)\n+TRANS(amadd_w, 64, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL)\n+TRANS(amadd_d, 64, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ)\n+TRANS(amand_w, 64, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL)\n+TRANS(amand_d, 64, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ)\n+TRANS(amor_w, 64, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL)\n+TRANS(amor_d, 64, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ)\n+TRANS(amxor_w, 64, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL)\n+TRANS(amxor_d, 64, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ)\n+TRANS(ammax_w, 64, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL)\n+TRANS(ammax_d, 64, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ)\n+TRANS(ammin_w, 64, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL)\n+TRANS(ammin_d, 64, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ)\n+TRANS(ammax_wu, 64, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL)\n+TRANS(ammax_du, 64, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ)\n+TRANS(ammin_wu, 64, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL)\n+TRANS(ammin_du, 64, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ)\n+TRANS(amswap_db_w, 64, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL)\n+TRANS(amswap_db_d, 64, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ)\n+TRANS(amadd_db_w, 64, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL)\n+TRANS(amadd_db_d, 64, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ)\n+TRANS(amand_db_w, 64, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL)\n+TRANS(amand_db_d, 64, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ)\n+TRANS(amor_db_w, 64, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL)\n+TRANS(amor_db_d, 64, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ)\n+TRANS(amxor_db_w, 64, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL)\n+TRANS(amxor_db_d, 64, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ)\n+TRANS(ammax_db_w, 64, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL)\n+TRANS(ammax_db_d, 64, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ)\n+TRANS(ammin_db_w, 64, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL)\n+TRANS(ammin_db_d, 64, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ)\n+TRANS(ammax_db_wu, 64, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL)\n+TRANS(ammax_db_du, 64, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ)\n+TRANS(ammin_db_wu, 64, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL)\n+TRANS(ammin_db_du, 64, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ)\ndiff --git a/target/loongarch/insn_trans/trans_bit.c.inc b/target/loongarch/insn_trans/trans_bit.c.inc\nindex d2a7ac28f7..ee5fa003ce 100644\n--- a/target/loongarch/insn_trans/trans_bit.c.inc\n+++ b/target/loongarch/insn_trans/trans_bit.c.inc\n@@ -184,25 +184,25 @@ TRANS(clo_w, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_clo_w)\n TRANS(clz_w, ALL, gen_rr, EXT_ZERO, EXT_NONE, gen_clz_w)\n TRANS(cto_w, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_cto_w)\n TRANS(ctz_w, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_ctz_w)\n-TRANS(clo_d, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_clo_d)\n-TRANS(clz_d, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_clz_d)\n-TRANS(cto_d, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_cto_d)\n-TRANS(ctz_d, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_ctz_d)\n+TRANS(clo_d, 64, gen_rr, EXT_NONE, EXT_NONE, gen_clo_d)\n+TRANS(clz_d, 64, gen_rr, EXT_NONE, EXT_NONE, gen_clz_d)\n+TRANS(cto_d, 64, gen_rr, EXT_NONE, EXT_NONE, gen_cto_d)\n+TRANS(ctz_d, 64, gen_rr, EXT_NONE, EXT_NONE, gen_ctz_d)\n TRANS(revb_2h, ALL, gen_rr, EXT_NONE, EXT_SIGN, gen_revb_2h)\n-TRANS(revb_4h, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_revb_4h)\n-TRANS(revb_2w, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_revb_2w)\n-TRANS(revb_d, ALL, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_bswap64_i64)\n-TRANS(revh_2w, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_revh_2w)\n-TRANS(revh_d, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_revh_d)\n+TRANS(revb_4h, 64, gen_rr, EXT_NONE, EXT_NONE, gen_revb_4h)\n+TRANS(revb_2w, 64, gen_rr, EXT_NONE, EXT_NONE, gen_revb_2w)\n+TRANS(revb_d, 64, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_bswap64_i64)\n+TRANS(revh_2w, 64, gen_rr, EXT_NONE, EXT_NONE, gen_revh_2w)\n+TRANS(revh_d, 64, gen_rr, EXT_NONE, EXT_NONE, gen_revh_d)\n TRANS(bitrev_4b, ALL, gen_rr, EXT_ZERO, EXT_SIGN, gen_helper_bitswap)\n-TRANS(bitrev_8b, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_helper_bitswap)\n+TRANS(bitrev_8b, 64, gen_rr, EXT_NONE, EXT_NONE, gen_helper_bitswap)\n TRANS(bitrev_w, ALL, gen_rr, EXT_NONE, EXT_SIGN, gen_helper_bitrev_w)\n-TRANS(bitrev_d, ALL, gen_rr, EXT_NONE, EXT_NONE, gen_helper_bitrev_d)\n+TRANS(bitrev_d, 64, gen_rr, EXT_NONE, EXT_NONE, gen_helper_bitrev_d)\n TRANS(maskeqz, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_maskeqz)\n TRANS(masknez, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_masknez)\n TRANS(bytepick_w, ALL, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_w)\n-TRANS(bytepick_d, ALL, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_d)\n+TRANS(bytepick_d, 64, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_d)\n TRANS(bstrins_w, ALL, gen_bstrins, EXT_SIGN)\n-TRANS(bstrins_d, ALL, gen_bstrins, EXT_NONE)\n+TRANS(bstrins_d, 64, gen_bstrins, EXT_NONE)\n TRANS(bstrpick_w, ALL, gen_bstrpick, EXT_SIGN)\n-TRANS(bstrpick_d, ALL, gen_bstrpick, EXT_NONE)\n+TRANS(bstrpick_d, 64, gen_bstrpick, EXT_NONE)\ndiff --git a/target/loongarch/insn_trans/trans_branch.c.inc b/target/loongarch/insn_trans/trans_branch.c.inc\nindex 50f7eb640a..a4fd2092e5 100644\n--- a/target/loongarch/insn_trans/trans_branch.c.inc\n+++ b/target/loongarch/insn_trans/trans_branch.c.inc\n@@ -80,5 +80,5 @@ TRANS(bltu, ALL, gen_rr_bc, TCG_COND_LTU)\n TRANS(bgeu, ALL, gen_rr_bc, TCG_COND_GEU)\n TRANS(beqz, ALL, gen_rz_bc, TCG_COND_EQ)\n TRANS(bnez, ALL, gen_rz_bc, TCG_COND_NE)\n-TRANS(bceqz, ALL, gen_cz_bc, TCG_COND_EQ)\n-TRANS(bcnez, ALL, gen_cz_bc, TCG_COND_NE)\n+TRANS(bceqz, 64, gen_cz_bc, TCG_COND_EQ)\n+TRANS(bcnez, 64, gen_cz_bc, TCG_COND_NE)\ndiff --git a/target/loongarch/insn_trans/trans_extra.c.inc b/target/loongarch/insn_trans/trans_extra.c.inc\nindex b354ca0f86..dd5d02e88c 100644\n--- a/target/loongarch/insn_trans/trans_extra.c.inc\n+++ b/target/loongarch/insn_trans/trans_extra.c.inc\n@@ -20,6 +20,10 @@ static bool trans_asrtle_d(DisasContext *ctx, arg_asrtle_d * a)\n TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);\n TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);\n \n+ if (!avail_64(ctx)) {\n+ return false;\n+ }\n+\n gen_helper_asrtle_d(cpu_env, src1, src2);\n return true;\n }\n@@ -29,6 +33,10 @@ static bool trans_asrtgt_d(DisasContext *ctx, arg_asrtgt_d * a)\n TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);\n TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);\n \n+ if (!avail_64(ctx)) {\n+ return false;\n+ }\n+\n gen_helper_asrtgt_d(cpu_env, src1, src2);\n return true;\n }\n@@ -89,11 +97,11 @@ static bool gen_crc(DisasContext *ctx, arg_rrr *a,\n return true;\n }\n \n-TRANS(crc_w_b_w, ALL, gen_crc, gen_helper_crc32, tcg_constant_tl(1))\n-TRANS(crc_w_h_w, ALL, gen_crc, gen_helper_crc32, tcg_constant_tl(2))\n-TRANS(crc_w_w_w, ALL, gen_crc, gen_helper_crc32, tcg_constant_tl(4))\n-TRANS(crc_w_d_w, ALL, gen_crc, gen_helper_crc32, tcg_constant_tl(8))\n-TRANS(crcc_w_b_w, ALL, gen_crc, gen_helper_crc32c, tcg_constant_tl(1))\n-TRANS(crcc_w_h_w, ALL, gen_crc, gen_helper_crc32c, tcg_constant_tl(2))\n-TRANS(crcc_w_w_w, ALL, gen_crc, gen_helper_crc32c, tcg_constant_tl(4))\n-TRANS(crcc_w_d_w, ALL, gen_crc, gen_helper_crc32c, tcg_constant_tl(8))\n+TRANS(crc_w_b_w, 64, gen_crc, gen_helper_crc32, tcg_constant_tl(1))\n+TRANS(crc_w_h_w, 64, gen_crc, gen_helper_crc32, tcg_constant_tl(2))\n+TRANS(crc_w_w_w, 64, gen_crc, gen_helper_crc32, tcg_constant_tl(4))\n+TRANS(crc_w_d_w, 64, gen_crc, gen_helper_crc32, tcg_constant_tl(8))\n+TRANS(crcc_w_b_w, 64, gen_crc, gen_helper_crc32c, tcg_constant_tl(1))\n+TRANS(crcc_w_h_w, 64, gen_crc, gen_helper_crc32c, tcg_constant_tl(2))\n+TRANS(crcc_w_w_w, 64, gen_crc, gen_helper_crc32c, tcg_constant_tl(4))\n+TRANS(crcc_w_d_w, 64, gen_crc, gen_helper_crc32c, tcg_constant_tl(8))\ndiff --git a/target/loongarch/insn_trans/trans_fmov.c.inc b/target/loongarch/insn_trans/trans_fmov.c.inc\nindex aa7fea67b5..385bbb7929 100644\n--- a/target/loongarch/insn_trans/trans_fmov.c.inc\n+++ b/target/loongarch/insn_trans/trans_fmov.c.inc\n@@ -181,8 +181,8 @@ static bool trans_movcf2gr(DisasContext *ctx, arg_movcf2gr *a)\n TRANS(fmov_s, ALL, gen_f2f, tcg_gen_mov_tl, true)\n TRANS(fmov_d, ALL, gen_f2f, tcg_gen_mov_tl, false)\n TRANS(movgr2fr_w, ALL, gen_r2f, gen_movgr2fr_w)\n-TRANS(movgr2fr_d, ALL, gen_r2f, tcg_gen_mov_tl)\n+TRANS(movgr2fr_d, 64, gen_r2f, tcg_gen_mov_tl)\n TRANS(movgr2frh_w, ALL, gen_r2f, gen_movgr2frh_w)\n TRANS(movfr2gr_s, ALL, gen_f2r, tcg_gen_ext32s_tl)\n-TRANS(movfr2gr_d, ALL, gen_f2r, tcg_gen_mov_tl)\n+TRANS(movfr2gr_d, 64, gen_f2r, tcg_gen_mov_tl)\n TRANS(movfrh2gr_s, ALL, gen_f2r, gen_movfrh2gr_s)\ndiff --git a/target/loongarch/insn_trans/trans_memory.c.inc b/target/loongarch/insn_trans/trans_memory.c.inc\nindex ad6a4b006d..d9d062235a 100644\n--- a/target/loongarch/insn_trans/trans_memory.c.inc\n+++ b/target/loongarch/insn_trans/trans_memory.c.inc\n@@ -148,42 +148,42 @@ static bool gen_stptr(DisasContext *ctx, arg_rr_i *a, MemOp mop)\n TRANS(ld_b, ALL, gen_load, MO_SB)\n TRANS(ld_h, ALL, gen_load, MO_TESW)\n TRANS(ld_w, ALL, gen_load, MO_TESL)\n-TRANS(ld_d, ALL, gen_load, MO_TEUQ)\n+TRANS(ld_d, 64, gen_load, MO_TEUQ)\n TRANS(st_b, ALL, gen_store, MO_UB)\n TRANS(st_h, ALL, gen_store, MO_TEUW)\n TRANS(st_w, ALL, gen_store, MO_TEUL)\n-TRANS(st_d, ALL, gen_store, MO_TEUQ)\n+TRANS(st_d, 64, gen_store, MO_TEUQ)\n TRANS(ld_bu, ALL, gen_load, MO_UB)\n TRANS(ld_hu, ALL, gen_load, MO_TEUW)\n-TRANS(ld_wu, ALL, gen_load, MO_TEUL)\n-TRANS(ldx_b, ALL, gen_loadx, MO_SB)\n-TRANS(ldx_h, ALL, gen_loadx, MO_TESW)\n-TRANS(ldx_w, ALL, gen_loadx, MO_TESL)\n-TRANS(ldx_d, ALL, gen_loadx, MO_TEUQ)\n-TRANS(stx_b, ALL, gen_storex, MO_UB)\n-TRANS(stx_h, ALL, gen_storex, MO_TEUW)\n-TRANS(stx_w, ALL, gen_storex, MO_TEUL)\n-TRANS(stx_d, ALL, gen_storex, MO_TEUQ)\n-TRANS(ldx_bu, ALL, gen_loadx, MO_UB)\n-TRANS(ldx_hu, ALL, gen_loadx, MO_TEUW)\n-TRANS(ldx_wu, ALL, gen_loadx, MO_TEUL)\n-TRANS(ldptr_w, ALL, gen_ldptr, MO_TESL)\n-TRANS(stptr_w, ALL, gen_stptr, MO_TEUL)\n-TRANS(ldptr_d, ALL, gen_ldptr, MO_TEUQ)\n-TRANS(stptr_d, ALL, gen_stptr, MO_TEUQ)\n-TRANS(ldgt_b, ALL, gen_load_gt, MO_SB)\n-TRANS(ldgt_h, ALL, gen_load_gt, MO_TESW)\n-TRANS(ldgt_w, ALL, gen_load_gt, MO_TESL)\n-TRANS(ldgt_d, ALL, gen_load_gt, MO_TEUQ)\n-TRANS(ldle_b, ALL, gen_load_le, MO_SB)\n-TRANS(ldle_h, ALL, gen_load_le, MO_TESW)\n-TRANS(ldle_w, ALL, gen_load_le, MO_TESL)\n-TRANS(ldle_d, ALL, gen_load_le, MO_TEUQ)\n-TRANS(stgt_b, ALL, gen_store_gt, MO_UB)\n-TRANS(stgt_h, ALL, gen_store_gt, MO_TEUW)\n-TRANS(stgt_w, ALL, gen_store_gt, MO_TEUL)\n-TRANS(stgt_d, ALL, gen_store_gt, MO_TEUQ)\n-TRANS(stle_b, ALL, gen_store_le, MO_UB)\n-TRANS(stle_h, ALL, gen_store_le, MO_TEUW)\n-TRANS(stle_w, ALL, gen_store_le, MO_TEUL)\n-TRANS(stle_d, ALL, gen_store_le, MO_TEUQ)\n+TRANS(ld_wu, 64, gen_load, MO_TEUL)\n+TRANS(ldx_b, 64, gen_loadx, MO_SB)\n+TRANS(ldx_h, 64, gen_loadx, MO_TESW)\n+TRANS(ldx_w, 64, gen_loadx, MO_TESL)\n+TRANS(ldx_d, 64, gen_loadx, MO_TEUQ)\n+TRANS(stx_b, 64, gen_storex, MO_UB)\n+TRANS(stx_h, 64, gen_storex, MO_TEUW)\n+TRANS(stx_w, 64, gen_storex, MO_TEUL)\n+TRANS(stx_d, 64, gen_storex, MO_TEUQ)\n+TRANS(ldx_bu, 64, gen_loadx, MO_UB)\n+TRANS(ldx_hu, 64, gen_loadx, MO_TEUW)\n+TRANS(ldx_wu, 64, gen_loadx, MO_TEUL)\n+TRANS(ldptr_w, 64, gen_ldptr, MO_TESL)\n+TRANS(stptr_w, 64, gen_stptr, MO_TEUL)\n+TRANS(ldptr_d, 64, gen_ldptr, MO_TEUQ)\n+TRANS(stptr_d, 64, gen_stptr, MO_TEUQ)\n+TRANS(ldgt_b, 64, gen_load_gt, MO_SB)\n+TRANS(ldgt_h, 64, gen_load_gt, MO_TESW)\n+TRANS(ldgt_w, 64, gen_load_gt, MO_TESL)\n+TRANS(ldgt_d, 64, gen_load_gt, MO_TEUQ)\n+TRANS(ldle_b, 64, gen_load_le, MO_SB)\n+TRANS(ldle_h, 64, gen_load_le, MO_TESW)\n+TRANS(ldle_w, 64, gen_load_le, MO_TESL)\n+TRANS(ldle_d, 64, gen_load_le, MO_TEUQ)\n+TRANS(stgt_b, 64, gen_store_gt, MO_UB)\n+TRANS(stgt_h, 64, gen_store_gt, MO_TEUW)\n+TRANS(stgt_w, 64, gen_store_gt, MO_TEUL)\n+TRANS(stgt_d, 64, gen_store_gt, MO_TEUQ)\n+TRANS(stle_b, 64, gen_store_le, MO_UB)\n+TRANS(stle_h, 64, gen_store_le, MO_TEUW)\n+TRANS(stle_w, 64, gen_store_le, MO_TEUL)\n+TRANS(stle_d, 64, gen_store_le, MO_TEUQ)\ndiff --git a/target/loongarch/insn_trans/trans_shift.c.inc b/target/loongarch/insn_trans/trans_shift.c.inc\nindex 849759b94b..2f4bd6ff28 100644\n--- a/target/loongarch/insn_trans/trans_shift.c.inc\n+++ b/target/loongarch/insn_trans/trans_shift.c.inc\n@@ -72,6 +72,10 @@ static bool trans_srai_w(DisasContext *ctx, arg_srai_w *a)\n TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);\n TCGv src1 = gpr_src(ctx, a->rj, EXT_ZERO);\n \n+ if (!avail_64(ctx)) {\n+ return false;\n+ }\n+\n tcg_gen_sextract_tl(dest, src1, a->imm, 32 - a->imm);\n gen_set_gpr(a->rd, dest, EXT_NONE);\n \n@@ -81,15 +85,15 @@ static bool trans_srai_w(DisasContext *ctx, arg_srai_w *a)\n TRANS(sll_w, ALL, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_sll_w)\n TRANS(srl_w, ALL, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_srl_w)\n TRANS(sra_w, ALL, gen_rrr, EXT_SIGN, EXT_NONE, EXT_SIGN, gen_sra_w)\n-TRANS(sll_d, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sll_d)\n-TRANS(srl_d, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_srl_d)\n-TRANS(sra_d, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sra_d)\n-TRANS(rotr_w, ALL, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_rotr_w)\n-TRANS(rotr_d, ALL, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rotr_d)\n+TRANS(sll_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sll_d)\n+TRANS(srl_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_srl_d)\n+TRANS(sra_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sra_d)\n+TRANS(rotr_w, 64, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_rotr_w)\n+TRANS(rotr_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rotr_d)\n TRANS(slli_w, ALL, gen_rri_c, EXT_NONE, EXT_SIGN, tcg_gen_shli_tl)\n-TRANS(slli_d, ALL, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shli_tl)\n+TRANS(slli_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shli_tl)\n TRANS(srli_w, ALL, gen_rri_c, EXT_ZERO, EXT_SIGN, tcg_gen_shri_tl)\n-TRANS(srli_d, ALL, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shri_tl)\n-TRANS(srai_d, ALL, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_sari_tl)\n-TRANS(rotri_w, ALL, gen_rri_v, EXT_NONE, EXT_NONE, gen_rotr_w)\n-TRANS(rotri_d, ALL, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_rotri_tl)\n+TRANS(srli_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shri_tl)\n+TRANS(srai_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_sari_tl)\n+TRANS(rotri_w, 64, gen_rri_v, EXT_NONE, EXT_NONE, gen_rotr_w)\n+TRANS(rotri_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_rotri_tl)\ndiff --git a/target/loongarch/translate.c b/target/loongarch/translate.c\nindex de7c1c5d1f..6967e12fc3 100644\n--- a/target/loongarch/translate.c\n+++ b/target/loongarch/translate.c\n@@ -127,6 +127,8 @@ static void loongarch_tr_init_disas_context(DisasContextBase *dcbase,\n ctx->va32 = (ctx->base.tb->flags & HW_FLAGS_VA32) != 0;\n \n ctx->zero = tcg_constant_tl(0);\n+\n+ ctx->cpucfg1 = env->cpucfg[1];\n }\n \n static void loongarch_tr_tb_start(DisasContextBase *dcbase, CPUState *cs)\ndiff --git a/target/loongarch/translate.h b/target/loongarch/translate.h\nindex 3c5c746f30..1342446242 100644\n--- a/target/loongarch/translate.h\n+++ b/target/loongarch/translate.h\n@@ -15,6 +15,8 @@\n { return avail_##AVAIL(ctx) && FUNC(ctx, a, __VA_ARGS__); }\n \n #define avail_ALL(C) true\n+#define avail_64(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, ARCH) == \\\n+ CPUCFG1_ARCH_LA64)\n \n /*\n * If an operation is being performed on less than TARGET_LONG_BITS,\n@@ -37,6 +39,7 @@ typedef struct DisasContext {\n TCGv zero;\n bool la64; /* LoongArch64 mode */\n bool va32; /* 32-bit virtual address */\n+ uint32_t cpucfg1;\n } DisasContext;\n \n void generate_exception(DisasContext *ctx, int excp);\n", "prefixes": [ "PULL", "20/31" ] }