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GET /api/patches/1825216/?format=api
{ "id": 1825216, "url": "http://patchwork.ozlabs.org/api/patches/1825216/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20230824092409.1492470-9-gaosong@loongson.cn/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20230824092409.1492470-9-gaosong@loongson.cn>", "list_archive_url": null, "date": "2023-08-24T09:23:46", "name": "[PULL,08/31] target/loongarch: Add GDB support for loongarch32 mode", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d90311ed208320b8914d7b53acb7295178bb273e", "submitter": { "id": 82024, "url": "http://patchwork.ozlabs.org/api/people/82024/?format=api", "name": "gaosong", "email": "gaosong@loongson.cn" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20230824092409.1492470-9-gaosong@loongson.cn/mbox/", "series": [ { "id": 370173, "url": "http://patchwork.ozlabs.org/api/series/370173/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=370173", "date": "2023-08-24T09:23:41", "name": "[PULL,01/31] target/loongarch: Log I/O write accesses to CSR registers", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/370173/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1825216/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1825216/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)", "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4RWd3y4xKXz1yfF\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 24 Aug 2023 19:25:50 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1qZ6Zu-0003k9-LH; Thu, 24 Aug 2023 05:24:34 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <gaosong@loongson.cn>)\n id 1qZ6Zs-0003aG-9T\n for qemu-devel@nongnu.org; Thu, 24 Aug 2023 05:24:32 -0400", "from mail.loongson.cn ([114.242.206.163])\n by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from <gaosong@loongson.cn>) id 1qZ6Zm-0003SE-GU\n for qemu-devel@nongnu.org; Thu, 24 Aug 2023 05:24:31 -0400", "from loongson.cn (unknown [10.2.5.185])\n by gateway (Coremail) with SMTP id _____8Axjuu_IedkR3kbAA--.53765S3;\n Thu, 24 Aug 2023 17:24:15 +0800 (CST)", "from localhost.localdomain (unknown [10.2.5.185])\n by localhost.localdomain (Coremail) with SMTP id\n AQAAf8DxJ826IedkJjhiAA--.40637S10;\n Thu, 24 Aug 2023 17:24:15 +0800 (CST)" ], "From": "Song Gao <gaosong@loongson.cn>", "To": "qemu-devel@nongnu.org", "Cc": "stefanha@redhat.com, richard.henderson@linaro.org, Jiajie Chen <c@jia.je>,\n\t=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org>", "Subject": "[PULL 08/31] target/loongarch: Add GDB support for loongarch32 mode", "Date": "Thu, 24 Aug 2023 17:23:46 +0800", "Message-Id": "<20230824092409.1492470-9-gaosong@loongson.cn>", "X-Mailer": "git-send-email 2.39.1", "In-Reply-To": "<20230824092409.1492470-1-gaosong@loongson.cn>", "References": "<20230824092409.1492470-1-gaosong@loongson.cn>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-CM-TRANSID": "AQAAf8DxJ826IedkJjhiAA--.40637S10", "X-CM-SenderInfo": "5jdr20tqj6z05rqj20fqof0/", "X-Coremail-Antispam": "1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7\n ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx\n nUUI43ZEXa7xR_UUUUUUUUU==", "Received-SPF": "pass client-ip=114.242.206.163;\n envelope-from=gaosong@loongson.cn;\n helo=mail.loongson.cn", "X-Spam_score_int": "-18", "X-Spam_score": "-1.9", "X-Spam_bar": "-", "X-Spam_report": "(-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Jiajie Chen <c@jia.je>\n\nGPRs and PC are 32-bit wide in loongarch32 mode.\n\nSigned-off-by: Jiajie Chen <c@jia.je>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nSigned-off-by: Song Gao <gaosong@loongson.cn>\nMessage-ID: <20230817093121.1053890-4-gaosong@loongson.cn>\n[PMD: Rebased, set gdb_num_core_regs]\nSigned-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\nMessage-Id: <20230821125959.28666-9-philmd@linaro.org>\n---\n configs/targets/loongarch64-softmmu.mak | 2 +-\n gdb-xml/loongarch-base32.xml | 45 +++++++++++++++++++++++++\n target/loongarch/cpu.c | 10 ++++++\n target/loongarch/gdbstub.c | 32 ++++++++++++++----\n 4 files changed, 81 insertions(+), 8 deletions(-)\n create mode 100644 gdb-xml/loongarch-base32.xml", "diff": "diff --git a/configs/targets/loongarch64-softmmu.mak b/configs/targets/loongarch64-softmmu.mak\nindex 9abc99056f..f23780fdd8 100644\n--- a/configs/targets/loongarch64-softmmu.mak\n+++ b/configs/targets/loongarch64-softmmu.mak\n@@ -1,5 +1,5 @@\n TARGET_ARCH=loongarch64\n TARGET_BASE_ARCH=loongarch\n TARGET_SUPPORTS_MTTCG=y\n-TARGET_XML_FILES= gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu.xml\n+TARGET_XML_FILES= gdb-xml/loongarch-base32.xml gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu.xml\n TARGET_NEED_FDT=y\ndiff --git a/gdb-xml/loongarch-base32.xml b/gdb-xml/loongarch-base32.xml\nnew file mode 100644\nindex 0000000000..af47bbd3da\n--- /dev/null\n+++ b/gdb-xml/loongarch-base32.xml\n@@ -0,0 +1,45 @@\n+<?xml version=\"1.0\"?>\n+<!-- Copyright (C) 2022 Free Software Foundation, Inc.\n+\n+ Copying and distribution of this file, with or without modification,\n+ are permitted in any medium without royalty provided the copyright\n+ notice and this notice are preserved. -->\n+\n+<!DOCTYPE feature SYSTEM \"gdb-target.dtd\">\n+<feature name=\"org.gnu.gdb.loongarch.base\">\n+ <reg name=\"r0\" bitsize=\"32\" type=\"uint32\" group=\"general\"/>\n+ <reg name=\"r1\" bitsize=\"32\" type=\"code_ptr\" group=\"general\"/>\n+ <reg name=\"r2\" bitsize=\"32\" type=\"data_ptr\" group=\"general\"/>\n+ <reg name=\"r3\" bitsize=\"32\" type=\"data_ptr\" group=\"general\"/>\n+ <reg name=\"r4\" bitsize=\"32\" type=\"uint32\" group=\"general\"/>\n+ <reg name=\"r5\" bitsize=\"32\" type=\"uint32\" group=\"general\"/>\n+ <reg name=\"r6\" bitsize=\"32\" type=\"uint32\" group=\"general\"/>\n+ <reg name=\"r7\" bitsize=\"32\" type=\"uint32\" group=\"general\"/>\n+ <reg name=\"r8\" bitsize=\"32\" type=\"uint32\" group=\"general\"/>\n+ <reg name=\"r9\" bitsize=\"32\" type=\"uint32\" group=\"general\"/>\n+ <reg name=\"r10\" bitsize=\"32\" type=\"uint32\" group=\"general\"/>\n+ <reg name=\"r11\" bitsize=\"32\" type=\"uint32\" group=\"general\"/>\n+ <reg name=\"r12\" bitsize=\"32\" type=\"uint32\" group=\"general\"/>\n+ <reg name=\"r13\" bitsize=\"32\" type=\"uint32\" group=\"general\"/>\n+ <reg name=\"r14\" bitsize=\"32\" type=\"uint32\" group=\"general\"/>\n+ <reg name=\"r15\" bitsize=\"32\" type=\"uint32\" group=\"general\"/>\n+ <reg name=\"r16\" bitsize=\"32\" type=\"uint32\" group=\"general\"/>\n+ <reg name=\"r17\" bitsize=\"32\" type=\"uint32\" group=\"general\"/>\n+ <reg name=\"r18\" bitsize=\"32\" type=\"uint32\" group=\"general\"/>\n+ <reg name=\"r19\" bitsize=\"32\" type=\"uint32\" group=\"general\"/>\n+ <reg name=\"r20\" bitsize=\"32\" type=\"uint32\" group=\"general\"/>\n+ <reg name=\"r21\" bitsize=\"32\" type=\"uint32\" group=\"general\"/>\n+ <reg name=\"r22\" bitsize=\"32\" type=\"data_ptr\" group=\"general\"/>\n+ <reg name=\"r23\" bitsize=\"32\" type=\"uint32\" group=\"general\"/>\n+ <reg name=\"r24\" bitsize=\"32\" type=\"uint32\" group=\"general\"/>\n+ <reg name=\"r25\" bitsize=\"32\" type=\"uint32\" group=\"general\"/>\n+ <reg name=\"r26\" bitsize=\"32\" type=\"uint32\" group=\"general\"/>\n+ <reg name=\"r27\" bitsize=\"32\" type=\"uint32\" group=\"general\"/>\n+ <reg name=\"r28\" bitsize=\"32\" type=\"uint32\" group=\"general\"/>\n+ <reg name=\"r29\" bitsize=\"32\" type=\"uint32\" group=\"general\"/>\n+ <reg name=\"r30\" bitsize=\"32\" type=\"uint32\" group=\"general\"/>\n+ <reg name=\"r31\" bitsize=\"32\" type=\"uint32\" group=\"general\"/>\n+ <reg name=\"orig_a0\" bitsize=\"32\" type=\"uint32\" group=\"general\"/>\n+ <reg name=\"pc\" bitsize=\"32\" type=\"code_ptr\" group=\"general\"/>\n+ <reg name=\"badv\" bitsize=\"32\" type=\"code_ptr\" group=\"general\"/>\n+</feature>\ndiff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c\nindex 556419f159..822f2a72e5 100644\n--- a/target/loongarch/cpu.c\n+++ b/target/loongarch/cpu.c\n@@ -726,8 +726,18 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)\n #endif\n }\n \n+static gchar *loongarch32_gdb_arch_name(CPUState *cs)\n+{\n+ return g_strdup(\"loongarch32\");\n+}\n+\n static void loongarch32_cpu_class_init(ObjectClass *c, void *data)\n {\n+ CPUClass *cc = CPU_CLASS(c);\n+\n+ cc->gdb_num_core_regs = 35;\n+ cc->gdb_core_xml_file = \"loongarch-base32.xml\";\n+ cc->gdb_arch_name = loongarch32_gdb_arch_name;\n }\n \n static gchar *loongarch64_gdb_arch_name(CPUState *cs)\ndiff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c\nindex 0752fff924..a462e25737 100644\n--- a/target/loongarch/gdbstub.c\n+++ b/target/loongarch/gdbstub.c\n@@ -34,16 +34,25 @@ int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)\n {\n LoongArchCPU *cpu = LOONGARCH_CPU(cs);\n CPULoongArchState *env = &cpu->env;\n+ uint64_t val;\n \n if (0 <= n && n < 32) {\n- return gdb_get_regl(mem_buf, env->gpr[n]);\n+ val = env->gpr[n];\n } else if (n == 32) {\n /* orig_a0 */\n- return gdb_get_regl(mem_buf, 0);\n+ val = 0;\n } else if (n == 33) {\n- return gdb_get_regl(mem_buf, env->pc);\n+ val = env->pc;\n } else if (n == 34) {\n- return gdb_get_regl(mem_buf, env->CSR_BADV);\n+ val = env->CSR_BADV;\n+ }\n+\n+ if (0 <= n && n <= 34) {\n+ if (is_la64(env)) {\n+ return gdb_get_reg64(mem_buf, val);\n+ } else {\n+ return gdb_get_reg32(mem_buf, val);\n+ }\n }\n return 0;\n }\n@@ -52,15 +61,24 @@ int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)\n {\n LoongArchCPU *cpu = LOONGARCH_CPU(cs);\n CPULoongArchState *env = &cpu->env;\n- target_ulong tmp = ldtul_p(mem_buf);\n+ target_ulong tmp;\n+ int read_length;\n int length = 0;\n \n+ if (is_la64(env)) {\n+ tmp = ldq_p(mem_buf);\n+ read_length = 8;\n+ } else {\n+ tmp = ldl_p(mem_buf);\n+ read_length = 4;\n+ }\n+\n if (0 <= n && n < 32) {\n env->gpr[n] = tmp;\n- length = sizeof(target_ulong);\n+ length = read_length;\n } else if (n == 33) {\n env->pc = tmp;\n- length = sizeof(target_ulong);\n+ length = read_length;\n }\n return length;\n }\n", "prefixes": [ "PULL", "08/31" ] }