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GET /api/patches/1825210/?format=api
{ "id": 1825210, "url": "http://patchwork.ozlabs.org/api/patches/1825210/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20230824092409.1492470-13-gaosong@loongson.cn/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20230824092409.1492470-13-gaosong@loongson.cn>", "list_archive_url": null, "date": "2023-08-24T09:23:50", "name": "[PULL,12/31] target/loongarch: Add LA64 & VA32 to DisasContext", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5e1d1abdafd9b8ae2fdbbc08a746a39ea0356ecf", "submitter": { "id": 82024, "url": "http://patchwork.ozlabs.org/api/people/82024/?format=api", "name": "gaosong", "email": "gaosong@loongson.cn" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20230824092409.1492470-13-gaosong@loongson.cn/mbox/", "series": [ { "id": 370173, "url": "http://patchwork.ozlabs.org/api/series/370173/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=370173", "date": "2023-08-24T09:23:41", "name": "[PULL,01/31] target/loongarch: Log I/O write accesses to CSR registers", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/370173/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1825210/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1825210/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)", "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4RWd3X2fdfz1yfF\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 24 Aug 2023 19:25:28 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1qZ6ag-0004gE-GC; Thu, 24 Aug 2023 05:25:22 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <gaosong@loongson.cn>)\n id 1qZ6Zz-0003z4-F3\n for qemu-devel@nongnu.org; Thu, 24 Aug 2023 05:24:39 -0400", "from mail.loongson.cn ([114.242.206.163])\n by eggs.gnu.org with esmtp (Exim 4.90_1)\n (envelope-from <gaosong@loongson.cn>) id 1qZ6Zw-0003SU-Lo\n for qemu-devel@nongnu.org; Thu, 24 Aug 2023 05:24:39 -0400", "from loongson.cn (unknown [10.2.5.185])\n by gateway (Coremail) with SMTP id _____8AxTevBIedkWXkbAA--.50817S3;\n Thu, 24 Aug 2023 17:24:17 +0800 (CST)", "from localhost.localdomain (unknown [10.2.5.185])\n by localhost.localdomain (Coremail) with SMTP id\n AQAAf8DxJ826IedkJjhiAA--.40637S14;\n Thu, 24 Aug 2023 17:24:17 +0800 (CST)" ], "From": "Song Gao <gaosong@loongson.cn>", "To": "qemu-devel@nongnu.org", "Cc": "stefanha@redhat.com, richard.henderson@linaro.org, Jiajie Chen <c@jia.je>", "Subject": "[PULL 12/31] target/loongarch: Add LA64 & VA32 to DisasContext", "Date": "Thu, 24 Aug 2023 17:23:50 +0800", "Message-Id": "<20230824092409.1492470-13-gaosong@loongson.cn>", "X-Mailer": "git-send-email 2.39.1", "In-Reply-To": "<20230824092409.1492470-1-gaosong@loongson.cn>", "References": "<20230824092409.1492470-1-gaosong@loongson.cn>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-CM-TRANSID": "AQAAf8DxJ826IedkJjhiAA--.40637S14", "X-CM-SenderInfo": "5jdr20tqj6z05rqj20fqof0/", "X-Coremail-Antispam": "1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7\n ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx\n nUUI43ZEXa7xR_UUUUUUUUU==", "Received-SPF": "pass client-ip=114.242.206.163;\n envelope-from=gaosong@loongson.cn;\n helo=mail.loongson.cn", "X-Spam_score_int": "-18", "X-Spam_score": "-1.9", "X-Spam_bar": "-", "X-Spam_report": "(-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "From: Jiajie Chen <c@jia.je>\n\nAdd LA64 and VA32(32-bit Virtual Address) to DisasContext to allow the\ntranslator to reject doubleword instructions in LA32 mode for example.\n\nSigned-off-by: Jiajie Chen <c@jia.je>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nSigned-off-by: Song Gao <gaosong@loongson.cn>\nMessage-ID: <20230822032724.1353391-5-gaosong@loongson.cn>\nMessage-Id: <20230822071405.35386-5-philmd@linaro.org>\n---\n target/loongarch/cpu.h | 13 +++++++++++++\n target/loongarch/translate.c | 3 +++\n target/loongarch/translate.h | 2 ++\n 3 files changed, 18 insertions(+)", "diff": "diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h\nindex b8af491041..72109095e4 100644\n--- a/target/loongarch/cpu.h\n+++ b/target/loongarch/cpu.h\n@@ -432,6 +432,17 @@ static inline bool is_la64(CPULoongArchState *env)\n return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) == CPUCFG1_ARCH_LA64;\n }\n \n+static inline bool is_va32(CPULoongArchState *env)\n+{\n+ /* VA32 if !LA64 or VA32L[1-3] */\n+ bool va32 = !is_la64(env);\n+ uint64_t plv = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV);\n+ if (plv >= 1 && (FIELD_EX64(env->CSR_MISC, CSR_MISC, VA32) & (1 << plv))) {\n+ va32 = true;\n+ }\n+ return va32;\n+}\n+\n /*\n * LoongArch CPUs hardware flags.\n */\n@@ -439,6 +450,7 @@ static inline bool is_la64(CPULoongArchState *env)\n #define HW_FLAGS_CRMD_PG R_CSR_CRMD_PG_MASK /* 0x10 */\n #define HW_FLAGS_EUEN_FPE 0x04\n #define HW_FLAGS_EUEN_SXE 0x08\n+#define HW_FLAGS_VA32 0x20\n \n static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc,\n uint64_t *cs_base, uint32_t *flags)\n@@ -448,6 +460,7 @@ static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc,\n *flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK);\n *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE;\n *flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE;\n+ *flags |= is_va32(env) * HW_FLAGS_VA32;\n }\n \n void loongarch_cpu_list(void);\ndiff --git a/target/loongarch/translate.c b/target/loongarch/translate.c\nindex 3146a2d4ac..ac847745df 100644\n--- a/target/loongarch/translate.c\n+++ b/target/loongarch/translate.c\n@@ -119,6 +119,9 @@ static void loongarch_tr_init_disas_context(DisasContextBase *dcbase,\n ctx->vl = LSX_LEN;\n }\n \n+ ctx->la64 = is_la64(env);\n+ ctx->va32 = (ctx->base.tb->flags & HW_FLAGS_VA32) != 0;\n+\n ctx->zero = tcg_constant_tl(0);\n }\n \ndiff --git a/target/loongarch/translate.h b/target/loongarch/translate.h\nindex 7f60090580..b6fa5df82d 100644\n--- a/target/loongarch/translate.h\n+++ b/target/loongarch/translate.h\n@@ -33,6 +33,8 @@ typedef struct DisasContext {\n uint16_t plv;\n int vl; /* Vector length */\n TCGv zero;\n+ bool la64; /* LoongArch64 mode */\n+ bool va32; /* 32-bit virtual address */\n } DisasContext;\n \n void generate_exception(DisasContext *ctx, int excp);\n", "prefixes": [ "PULL", "12/31" ] }