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GET /api/patches/1821140/?format=api
{ "id": 1821140, "url": "http://patchwork.ozlabs.org/api/patches/1821140/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20230814215457.4075025-4-bhupesh.sharma@linaro.org/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20230814215457.4075025-4-bhupesh.sharma@linaro.org>", "list_archive_url": null, "date": "2023-08-14T21:54:43", "name": "[03/17] dt-bindings: clock: Import SM6115 and SM8250 related clock header files from Linux", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "6db5ef212cb063b7eb2c5b8d91e5078075e52e6e", "submitter": { "id": 81316, "url": "http://patchwork.ozlabs.org/api/people/81316/?format=api", "name": "Bhupesh Sharma", "email": "bhupesh.sharma@linaro.org" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20230814215457.4075025-4-bhupesh.sharma@linaro.org/mbox/", "series": [ { "id": 368803, "url": "http://patchwork.ozlabs.org/api/series/368803/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=368803", "date": "2023-08-14T21:54:40", "name": "Enable UFS on DragonBoard845c", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/368803/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1821140/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1821140/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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All rights reserved.\n+ */\n+\n+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM6115_H\n+#define _DT_BINDINGS_CLK_QCOM_GCC_SM6115_H\n+\n+/* GCC clocks */\n+#define GPLL0\t\t\t\t\t\t\t0\n+#define GPLL0_OUT_AUX2\t\t\t\t\t\t1\n+#define GPLL0_OUT_MAIN\t\t\t\t\t\t2\n+#define GPLL10\t\t\t\t\t\t\t3\n+#define GPLL10_OUT_MAIN\t\t\t\t\t\t4\n+#define GPLL11\t\t\t\t\t\t\t5\n+#define GPLL11_OUT_MAIN\t\t\t\t\t\t6\n+#define GPLL3\t\t\t\t\t\t\t7\n+#define GPLL4\t\t\t\t\t\t\t8\n+#define GPLL4_OUT_MAIN\t\t\t\t\t\t9\n+#define GPLL6\t\t\t\t\t\t\t10\n+#define GPLL6_OUT_MAIN\t\t\t\t\t\t11\n+#define GPLL7\t\t\t\t\t\t\t12\n+#define GPLL7_OUT_MAIN\t\t\t\t\t\t13\n+#define GPLL8\t\t\t\t\t\t\t14\n+#define GPLL8_OUT_MAIN\t\t\t\t\t\t15\n+#define GPLL9\t\t\t\t\t\t\t16\n+#define GPLL9_OUT_MAIN\t\t\t\t\t\t17\n+#define GCC_CAMSS_CSI0PHYTIMER_CLK\t\t\t\t18\n+#define GCC_CAMSS_CSI0PHYTIMER_CLK_SRC\t\t\t\t19\n+#define GCC_CAMSS_CSI1PHYTIMER_CLK\t\t\t\t20\n+#define GCC_CAMSS_CSI1PHYTIMER_CLK_SRC\t\t\t\t21\n+#define GCC_CAMSS_CSI2PHYTIMER_CLK\t\t\t\t22\n+#define GCC_CAMSS_CSI2PHYTIMER_CLK_SRC\t\t\t\t23\n+#define GCC_CAMSS_MCLK0_CLK\t\t\t\t\t24\n+#define GCC_CAMSS_MCLK0_CLK_SRC\t\t\t\t\t25\n+#define GCC_CAMSS_MCLK1_CLK\t\t\t\t\t26\n+#define GCC_CAMSS_MCLK1_CLK_SRC\t\t\t\t\t27\n+#define GCC_CAMSS_MCLK2_CLK\t\t\t\t\t28\n+#define GCC_CAMSS_MCLK2_CLK_SRC\t\t\t\t\t29\n+#define GCC_CAMSS_MCLK3_CLK\t\t\t\t\t30\n+#define GCC_CAMSS_MCLK3_CLK_SRC\t\t\t\t\t31\n+#define GCC_CAMSS_NRT_AXI_CLK\t\t\t\t\t32\n+#define GCC_CAMSS_OPE_AHB_CLK\t\t\t\t\t33\n+#define GCC_CAMSS_OPE_AHB_CLK_SRC\t\t\t\t34\n+#define GCC_CAMSS_OPE_CLK\t\t\t\t\t35\n+#define GCC_CAMSS_OPE_CLK_SRC\t\t\t\t\t36\n+#define GCC_CAMSS_RT_AXI_CLK\t\t\t\t\t37\n+#define GCC_CAMSS_TFE_0_CLK\t\t\t\t\t38\n+#define GCC_CAMSS_TFE_0_CLK_SRC\t\t\t\t\t39\n+#define GCC_CAMSS_TFE_0_CPHY_RX_CLK\t\t\t\t40\n+#define GCC_CAMSS_TFE_0_CSID_CLK\t\t\t\t41\n+#define GCC_CAMSS_TFE_0_CSID_CLK_SRC\t\t\t\t42\n+#define GCC_CAMSS_TFE_1_CLK\t\t\t\t\t43\n+#define GCC_CAMSS_TFE_1_CLK_SRC\t\t\t\t\t44\n+#define GCC_CAMSS_TFE_1_CPHY_RX_CLK\t\t\t\t45\n+#define GCC_CAMSS_TFE_1_CSID_CLK\t\t\t\t46\n+#define GCC_CAMSS_TFE_1_CSID_CLK_SRC\t\t\t\t47\n+#define GCC_CAMSS_TFE_2_CLK\t\t\t\t\t48\n+#define GCC_CAMSS_TFE_2_CLK_SRC\t\t\t\t\t49\n+#define GCC_CAMSS_TFE_2_CPHY_RX_CLK\t\t\t\t50\n+#define GCC_CAMSS_TFE_2_CSID_CLK\t\t\t\t51\n+#define GCC_CAMSS_TFE_2_CSID_CLK_SRC\t\t\t\t52\n+#define GCC_CAMSS_TFE_CPHY_RX_CLK_SRC\t\t\t\t53\n+#define GCC_CAMSS_TOP_AHB_CLK\t\t\t\t\t54\n+#define GCC_CAMSS_TOP_AHB_CLK_SRC\t\t\t\t55\n+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK\t\t\t\t56\n+#define GCC_CPUSS_AHB_CLK\t\t\t\t\t57\n+#define GCC_CPUSS_GNOC_CLK\t\t\t\t\t60\n+#define GCC_DISP_AHB_CLK\t\t\t\t\t61\n+#define GCC_DISP_GPLL0_DIV_CLK_SRC\t\t\t\t62\n+#define GCC_DISP_HF_AXI_CLK\t\t\t\t\t63\n+#define GCC_DISP_THROTTLE_CORE_CLK\t\t\t\t64\n+#define GCC_DISP_XO_CLK\t\t\t\t\t\t65\n+#define GCC_GP1_CLK\t\t\t\t\t\t66\n+#define GCC_GP1_CLK_SRC\t\t\t\t\t\t67\n+#define GCC_GP2_CLK\t\t\t\t\t\t68\n+#define GCC_GP2_CLK_SRC\t\t\t\t\t\t69\n+#define GCC_GP3_CLK\t\t\t\t\t\t70\n+#define GCC_GP3_CLK_SRC\t\t\t\t\t\t71\n+#define GCC_GPU_CFG_AHB_CLK\t\t\t\t\t72\n+#define GCC_GPU_GPLL0_CLK_SRC\t\t\t\t\t73\n+#define GCC_GPU_GPLL0_DIV_CLK_SRC\t\t\t\t74\n+#define GCC_GPU_IREF_CLK\t\t\t\t\t75\n+#define GCC_GPU_MEMNOC_GFX_CLK\t\t\t\t\t76\n+#define GCC_GPU_SNOC_DVM_GFX_CLK\t\t\t\t77\n+#define GCC_GPU_THROTTLE_CORE_CLK\t\t\t\t78\n+#define GCC_GPU_THROTTLE_XO_CLK\t\t\t\t\t79\n+#define GCC_PDM2_CLK\t\t\t\t\t\t80\n+#define GCC_PDM2_CLK_SRC\t\t\t\t\t81\n+#define GCC_PDM_AHB_CLK\t\t\t\t\t\t82\n+#define GCC_PDM_XO4_CLK\t\t\t\t\t\t83\n+#define GCC_PRNG_AHB_CLK\t\t\t\t\t84\n+#define GCC_QMIP_CAMERA_NRT_AHB_CLK\t\t\t\t85\n+#define GCC_QMIP_CAMERA_RT_AHB_CLK\t\t\t\t86\n+#define GCC_QMIP_DISP_AHB_CLK\t\t\t\t\t87\n+#define GCC_QMIP_GPU_CFG_AHB_CLK\t\t\t\t88\n+#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK\t\t\t\t89\n+#define GCC_QUPV3_WRAP0_CORE_2X_CLK\t\t\t\t90\n+#define GCC_QUPV3_WRAP0_CORE_CLK\t\t\t\t91\n+#define GCC_QUPV3_WRAP0_S0_CLK\t\t\t\t\t92\n+#define GCC_QUPV3_WRAP0_S0_CLK_SRC\t\t\t\t93\n+#define GCC_QUPV3_WRAP0_S1_CLK\t\t\t\t\t94\n+#define GCC_QUPV3_WRAP0_S1_CLK_SRC\t\t\t\t95\n+#define GCC_QUPV3_WRAP0_S2_CLK\t\t\t\t\t96\n+#define GCC_QUPV3_WRAP0_S2_CLK_SRC\t\t\t\t97\n+#define GCC_QUPV3_WRAP0_S3_CLK\t\t\t\t\t98\n+#define GCC_QUPV3_WRAP0_S3_CLK_SRC\t\t\t\t99\n+#define GCC_QUPV3_WRAP0_S4_CLK\t\t\t\t\t100\n+#define GCC_QUPV3_WRAP0_S4_CLK_SRC\t\t\t\t101\n+#define GCC_QUPV3_WRAP0_S5_CLK\t\t\t\t\t102\n+#define GCC_QUPV3_WRAP0_S5_CLK_SRC\t\t\t\t103\n+#define GCC_QUPV3_WRAP_0_M_AHB_CLK\t\t\t\t104\n+#define GCC_QUPV3_WRAP_0_S_AHB_CLK\t\t\t\t105\n+#define GCC_SDCC1_AHB_CLK\t\t\t\t\t106\n+#define GCC_SDCC1_APPS_CLK\t\t\t\t\t107\n+#define GCC_SDCC1_APPS_CLK_SRC\t\t\t\t\t108\n+#define GCC_SDCC1_ICE_CORE_CLK\t\t\t\t\t109\n+#define GCC_SDCC1_ICE_CORE_CLK_SRC\t\t\t\t110\n+#define GCC_SDCC2_AHB_CLK\t\t\t\t\t111\n+#define GCC_SDCC2_APPS_CLK\t\t\t\t\t112\n+#define GCC_SDCC2_APPS_CLK_SRC\t\t\t\t\t113\n+#define GCC_SYS_NOC_CPUSS_AHB_CLK\t\t\t\t114\n+#define GCC_SYS_NOC_UFS_PHY_AXI_CLK\t\t\t\t115\n+#define GCC_SYS_NOC_USB3_PRIM_AXI_CLK\t\t\t\t116\n+#define GCC_UFS_PHY_AHB_CLK\t\t\t\t\t117\n+#define GCC_UFS_PHY_AXI_CLK\t\t\t\t\t118\n+#define GCC_UFS_PHY_AXI_CLK_SRC\t\t\t\t\t119\n+#define GCC_UFS_PHY_ICE_CORE_CLK\t\t\t\t120\n+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC\t\t\t\t121\n+#define GCC_UFS_PHY_PHY_AUX_CLK\t\t\t\t\t122\n+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC\t\t\t\t123\n+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK\t\t\t\t124\n+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK\t\t\t\t125\n+#define GCC_UFS_PHY_UNIPRO_CORE_CLK\t\t\t\t126\n+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC\t\t\t\t127\n+#define GCC_USB30_PRIM_MASTER_CLK\t\t\t\t128\n+#define GCC_USB30_PRIM_MASTER_CLK_SRC\t\t\t\t129\n+#define GCC_USB30_PRIM_MOCK_UTMI_CLK\t\t\t\t130\n+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC\t\t\t131\n+#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC\t\t132\n+#define GCC_USB30_PRIM_SLEEP_CLK\t\t\t\t133\n+#define GCC_USB3_PRIM_CLKREF_CLK\t\t\t\t134\n+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC\t\t\t\t135\n+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK\t\t\t\t136\n+#define GCC_USB3_PRIM_PHY_PIPE_CLK\t\t\t\t137\n+#define GCC_VCODEC0_AXI_CLK\t\t\t\t\t138\n+#define GCC_VENUS_AHB_CLK\t\t\t\t\t139\n+#define GCC_VENUS_CTL_AXI_CLK\t\t\t\t\t140\n+#define GCC_VIDEO_AHB_CLK\t\t\t\t\t141\n+#define GCC_VIDEO_AXI0_CLK\t\t\t\t\t142\n+#define GCC_VIDEO_THROTTLE_CORE_CLK\t\t\t\t143\n+#define GCC_VIDEO_VCODEC0_SYS_CLK\t\t\t\t144\n+#define GCC_VIDEO_VENUS_CLK_SRC\t\t\t\t\t145\n+#define GCC_VIDEO_VENUS_CTL_CLK\t\t\t\t\t146\n+#define GCC_VIDEO_XO_CLK\t\t\t\t\t147\n+#define GCC_AHB2PHY_CSI_CLK\t\t\t\t\t148\n+#define GCC_AHB2PHY_USB_CLK\t\t\t\t\t149\n+#define GCC_BIMC_GPU_AXI_CLK\t\t\t\t\t150\n+#define GCC_BOOT_ROM_AHB_CLK\t\t\t\t\t151\n+#define GCC_CAM_THROTTLE_NRT_CLK\t\t\t\t152\n+#define GCC_CAM_THROTTLE_RT_CLK\t\t\t\t\t153\n+#define GCC_CAMERA_AHB_CLK\t\t\t\t\t154\n+#define GCC_CAMERA_XO_CLK\t\t\t\t\t155\n+#define GCC_CAMSS_AXI_CLK\t\t\t\t\t156\n+#define GCC_CAMSS_AXI_CLK_SRC\t\t\t\t\t157\n+#define GCC_CAMSS_CAMNOC_ATB_CLK\t\t\t\t158\n+#define GCC_CAMSS_CAMNOC_NTS_XO_CLK\t\t\t\t159\n+#define GCC_CAMSS_CCI_0_CLK\t\t\t\t\t160\n+#define GCC_CAMSS_CCI_CLK_SRC\t\t\t\t\t161\n+#define GCC_CAMSS_CPHY_0_CLK\t\t\t\t\t162\n+#define GCC_CAMSS_CPHY_1_CLK\t\t\t\t\t163\n+#define GCC_CAMSS_CPHY_2_CLK\t\t\t\t\t164\n+#define GCC_UFS_CLKREF_CLK\t\t\t\t\t165\n+#define GCC_DISP_GPLL0_CLK_SRC\t\t\t\t\t166\n+\n+/* GCC resets */\n+#define GCC_QUSB2PHY_PRIM_BCR\t\t\t\t\t0\n+#define GCC_QUSB2PHY_SEC_BCR\t\t\t\t\t1\n+#define GCC_SDCC1_BCR\t\t\t\t\t\t2\n+#define GCC_UFS_PHY_BCR\t\t\t\t\t\t3\n+#define GCC_USB30_PRIM_BCR\t\t\t\t\t4\n+#define GCC_USB_PHY_CFG_AHB2PHY_BCR\t\t\t\t5\n+#define GCC_VCODEC0_BCR\t\t\t\t\t\t6\n+#define GCC_VENUS_BCR\t\t\t\t\t\t7\n+#define GCC_VIDEO_INTERFACE_BCR\t\t\t\t\t8\n+#define GCC_USB3PHY_PHY_PRIM_SP0_BCR\t\t\t\t9\n+#define GCC_USB3_PHY_PRIM_SP0_BCR\t\t\t\t10\n+#define GCC_SDCC2_BCR\t\t\t\t\t\t11\n+\n+/* Indexes for GDSCs */\n+#define GCC_CAMSS_TOP_GDSC\t\t\t0\n+#define GCC_UFS_PHY_GDSC\t\t\t1\n+#define GCC_USB30_PRIM_GDSC\t\t\t2\n+#define GCC_VCODEC0_GDSC\t\t\t3\n+#define GCC_VENUS_GDSC\t\t\t\t4\n+#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC\t\t5\n+#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC\t\t6\n+#define HLOS1_VOTE_MM_SNOC_MMU_TBU_RT_GDSC\t7\n+#define HLOS1_VOTE_MM_SNOC_MMU_TBU_NRT_GDSC\t8\n+\n+#endif\ndiff --git a/include/dt-bindings/clock/qcom,gcc-sm8250.h b/include/dt-bindings/clock/qcom,gcc-sm8250.h\nnew file mode 100644\nindex 0000000000..7b7abe327e\n--- /dev/null\n+++ b/include/dt-bindings/clock/qcom,gcc-sm8250.h\n@@ -0,0 +1,271 @@\n+/* SPDX-License-Identifier: GPL-2.0-only */\n+/*\n+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.\n+ */\n+\n+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8250_H\n+#define _DT_BINDINGS_CLK_QCOM_GCC_SM8250_H\n+\n+/* GCC clocks */\n+#define GPLL0\t\t\t\t\t\t\t0\n+#define GPLL0_OUT_EVEN\t\t\t\t\t\t1\n+#define GPLL4\t\t\t\t\t\t\t2\n+#define GPLL9\t\t\t\t\t\t\t3\n+#define GCC_AGGRE_NOC_PCIE_TBU_CLK\t\t\t\t4\n+#define GCC_AGGRE_UFS_CARD_AXI_CLK\t\t\t\t5\n+#define GCC_AGGRE_UFS_PHY_AXI_CLK\t\t\t\t6\n+#define GCC_AGGRE_USB3_PRIM_AXI_CLK\t\t\t\t7\n+#define GCC_AGGRE_USB3_SEC_AXI_CLK\t\t\t\t8\n+#define GCC_BOOT_ROM_AHB_CLK\t\t\t\t\t9\n+#define GCC_CAMERA_AHB_CLK\t\t\t\t\t10\n+#define GCC_CAMERA_HF_AXI_CLK\t\t\t\t\t11\n+#define GCC_CAMERA_SF_AXI_CLK\t\t\t\t\t12\n+#define GCC_CAMERA_XO_CLK\t\t\t\t\t13\n+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK\t\t\t\t14\n+#define GCC_CFG_NOC_USB3_SEC_AXI_CLK\t\t\t\t15\n+#define GCC_CPUSS_AHB_CLK\t\t\t\t\t16\n+#define GCC_CPUSS_AHB_CLK_SRC\t\t\t\t\t17\n+#define GCC_CPUSS_AHB_POSTDIV_CLK_SRC\t\t\t\t18\n+#define GCC_CPUSS_DVM_BUS_CLK\t\t\t\t\t19\n+#define GCC_CPUSS_RBCPR_CLK\t\t\t\t\t20\n+#define GCC_DDRSS_GPU_AXI_CLK\t\t\t\t\t21\n+#define GCC_DDRSS_PCIE_SF_TBU_CLK\t\t\t\t22\n+#define GCC_DISP_AHB_CLK\t\t\t\t\t23\n+#define GCC_DISP_HF_AXI_CLK\t\t\t\t\t24\n+#define GCC_DISP_SF_AXI_CLK\t\t\t\t\t25\n+#define GCC_DISP_XO_CLK\t\t\t\t\t\t26\n+#define GCC_GP1_CLK\t\t\t\t\t\t27\n+#define GCC_GP1_CLK_SRC\t\t\t\t\t\t28\n+#define GCC_GP2_CLK\t\t\t\t\t\t29\n+#define GCC_GP2_CLK_SRC\t\t\t\t\t\t30\n+#define GCC_GP3_CLK\t\t\t\t\t\t31\n+#define GCC_GP3_CLK_SRC\t\t\t\t\t\t32\n+#define GCC_GPU_CFG_AHB_CLK\t\t\t\t\t33\n+#define GCC_GPU_GPLL0_CLK_SRC\t\t\t\t\t34\n+#define GCC_GPU_GPLL0_DIV_CLK_SRC\t\t\t\t35\n+#define GCC_GPU_IREF_EN\t\t\t\t\t\t36\n+#define GCC_GPU_MEMNOC_GFX_CLK\t\t\t\t\t37\n+#define GCC_GPU_SNOC_DVM_GFX_CLK\t\t\t\t38\n+#define GCC_NPU_AXI_CLK\t\t\t\t\t\t39\n+#define GCC_NPU_BWMON_AXI_CLK\t\t\t\t\t40\n+#define GCC_NPU_BWMON_CFG_AHB_CLK\t\t\t\t41\n+#define GCC_NPU_CFG_AHB_CLK\t\t\t\t\t42\n+#define GCC_NPU_DMA_CLK\t\t\t\t\t\t43\n+#define GCC_NPU_GPLL0_CLK_SRC\t\t\t\t\t44\n+#define GCC_NPU_GPLL0_DIV_CLK_SRC\t\t\t\t45\n+#define GCC_PCIE0_PHY_REFGEN_CLK\t\t\t\t46\n+#define GCC_PCIE1_PHY_REFGEN_CLK\t\t\t\t47\n+#define GCC_PCIE2_PHY_REFGEN_CLK\t\t\t\t48\n+#define GCC_PCIE_0_AUX_CLK\t\t\t\t\t49\n+#define GCC_PCIE_0_AUX_CLK_SRC\t\t\t\t\t50\n+#define GCC_PCIE_0_CFG_AHB_CLK\t\t\t\t\t51\n+#define GCC_PCIE_0_MSTR_AXI_CLK\t\t\t\t\t52\n+#define GCC_PCIE_0_PIPE_CLK\t\t\t\t\t53\n+#define GCC_PCIE_0_SLV_AXI_CLK\t\t\t\t\t54\n+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK\t\t\t\t55\n+#define GCC_PCIE_1_AUX_CLK\t\t\t\t\t56\n+#define GCC_PCIE_1_AUX_CLK_SRC\t\t\t\t\t57\n+#define GCC_PCIE_1_CFG_AHB_CLK\t\t\t\t\t58\n+#define GCC_PCIE_1_MSTR_AXI_CLK\t\t\t\t\t59\n+#define GCC_PCIE_1_PIPE_CLK\t\t\t\t\t60\n+#define GCC_PCIE_1_SLV_AXI_CLK\t\t\t\t\t61\n+#define GCC_PCIE_1_SLV_Q2A_AXI_CLK\t\t\t\t62\n+#define GCC_PCIE_2_AUX_CLK\t\t\t\t\t63\n+#define GCC_PCIE_2_AUX_CLK_SRC\t\t\t\t\t64\n+#define GCC_PCIE_2_CFG_AHB_CLK\t\t\t\t\t65\n+#define GCC_PCIE_2_MSTR_AXI_CLK\t\t\t\t\t66\n+#define GCC_PCIE_2_PIPE_CLK\t\t\t\t\t67\n+#define GCC_PCIE_2_SLV_AXI_CLK\t\t\t\t\t68\n+#define GCC_PCIE_2_SLV_Q2A_AXI_CLK\t\t\t\t69\n+#define GCC_PCIE_MDM_CLKREF_EN\t\t\t\t\t70\n+#define GCC_PCIE_PHY_AUX_CLK\t\t\t\t\t71\n+#define GCC_PCIE_PHY_REFGEN_CLK_SRC\t\t\t\t72\n+#define GCC_PCIE_WIFI_CLKREF_EN\t\t\t\t\t73\n+#define GCC_PCIE_WIGIG_CLKREF_EN\t\t\t\t74\n+#define GCC_PDM2_CLK\t\t\t\t\t\t75\n+#define GCC_PDM2_CLK_SRC\t\t\t\t\t76\n+#define GCC_PDM_AHB_CLK\t\t\t\t\t\t77\n+#define GCC_PDM_XO4_CLK\t\t\t\t\t\t78\n+#define GCC_PRNG_AHB_CLK\t\t\t\t\t79\n+#define GCC_QMIP_CAMERA_NRT_AHB_CLK\t\t\t\t80\n+#define GCC_QMIP_CAMERA_RT_AHB_CLK\t\t\t\t81\n+#define GCC_QMIP_DISP_AHB_CLK\t\t\t\t\t82\n+#define GCC_QMIP_VIDEO_CVP_AHB_CLK\t\t\t\t83\n+#define GCC_QMIP_VIDEO_VCODEC_AHB_CLK\t\t\t\t84\n+#define GCC_QUPV3_WRAP0_CORE_2X_CLK\t\t\t\t85\n+#define GCC_QUPV3_WRAP0_CORE_CLK\t\t\t\t86\n+#define GCC_QUPV3_WRAP0_S0_CLK\t\t\t\t\t87\n+#define GCC_QUPV3_WRAP0_S0_CLK_SRC\t\t\t\t88\n+#define GCC_QUPV3_WRAP0_S1_CLK\t\t\t\t\t89\n+#define GCC_QUPV3_WRAP0_S1_CLK_SRC\t\t\t\t90\n+#define GCC_QUPV3_WRAP0_S2_CLK\t\t\t\t\t91\n+#define GCC_QUPV3_WRAP0_S2_CLK_SRC\t\t\t\t92\n+#define GCC_QUPV3_WRAP0_S3_CLK\t\t\t\t\t93\n+#define GCC_QUPV3_WRAP0_S3_CLK_SRC\t\t\t\t94\n+#define GCC_QUPV3_WRAP0_S4_CLK\t\t\t\t\t95\n+#define GCC_QUPV3_WRAP0_S4_CLK_SRC\t\t\t\t96\n+#define GCC_QUPV3_WRAP0_S5_CLK\t\t\t\t\t97\n+#define GCC_QUPV3_WRAP0_S5_CLK_SRC\t\t\t\t98\n+#define GCC_QUPV3_WRAP0_S6_CLK\t\t\t\t\t99\n+#define GCC_QUPV3_WRAP0_S6_CLK_SRC\t\t\t\t100\n+#define GCC_QUPV3_WRAP0_S7_CLK\t\t\t\t\t101\n+#define GCC_QUPV3_WRAP0_S7_CLK_SRC\t\t\t\t102\n+#define GCC_QUPV3_WRAP1_CORE_2X_CLK\t\t\t\t103\n+#define GCC_QUPV3_WRAP1_CORE_CLK\t\t\t\t104\n+#define GCC_QUPV3_WRAP1_S0_CLK\t\t\t\t\t105\n+#define GCC_QUPV3_WRAP1_S0_CLK_SRC\t\t\t\t106\n+#define GCC_QUPV3_WRAP1_S1_CLK\t\t\t\t\t107\n+#define GCC_QUPV3_WRAP1_S1_CLK_SRC\t\t\t\t108\n+#define GCC_QUPV3_WRAP1_S2_CLK\t\t\t\t\t109\n+#define GCC_QUPV3_WRAP1_S2_CLK_SRC\t\t\t\t110\n+#define GCC_QUPV3_WRAP1_S3_CLK\t\t\t\t\t111\n+#define GCC_QUPV3_WRAP1_S3_CLK_SRC\t\t\t\t112\n+#define GCC_QUPV3_WRAP1_S4_CLK\t\t\t\t\t113\n+#define GCC_QUPV3_WRAP1_S4_CLK_SRC\t\t\t\t114\n+#define GCC_QUPV3_WRAP1_S5_CLK\t\t\t\t\t115\n+#define GCC_QUPV3_WRAP1_S5_CLK_SRC\t\t\t\t116\n+#define GCC_QUPV3_WRAP2_CORE_2X_CLK\t\t\t\t117\n+#define GCC_QUPV3_WRAP2_CORE_CLK\t\t\t\t118\n+#define GCC_QUPV3_WRAP2_S0_CLK\t\t\t\t\t119\n+#define GCC_QUPV3_WRAP2_S0_CLK_SRC\t\t\t\t120\n+#define GCC_QUPV3_WRAP2_S1_CLK\t\t\t\t\t121\n+#define GCC_QUPV3_WRAP2_S1_CLK_SRC\t\t\t\t122\n+#define GCC_QUPV3_WRAP2_S2_CLK\t\t\t\t\t123\n+#define GCC_QUPV3_WRAP2_S2_CLK_SRC\t\t\t\t124\n+#define GCC_QUPV3_WRAP2_S3_CLK\t\t\t\t\t125\n+#define GCC_QUPV3_WRAP2_S3_CLK_SRC\t\t\t\t126\n+#define GCC_QUPV3_WRAP2_S4_CLK\t\t\t\t\t127\n+#define GCC_QUPV3_WRAP2_S4_CLK_SRC\t\t\t\t128\n+#define GCC_QUPV3_WRAP2_S5_CLK\t\t\t\t\t129\n+#define GCC_QUPV3_WRAP2_S5_CLK_SRC\t\t\t\t130\n+#define GCC_QUPV3_WRAP_0_M_AHB_CLK\t\t\t\t131\n+#define GCC_QUPV3_WRAP_0_S_AHB_CLK\t\t\t\t132\n+#define GCC_QUPV3_WRAP_1_M_AHB_CLK\t\t\t\t133\n+#define GCC_QUPV3_WRAP_1_S_AHB_CLK\t\t\t\t134\n+#define GCC_QUPV3_WRAP_2_M_AHB_CLK\t\t\t\t135\n+#define GCC_QUPV3_WRAP_2_S_AHB_CLK\t\t\t\t136\n+#define GCC_SDCC2_AHB_CLK\t\t\t\t\t137\n+#define GCC_SDCC2_APPS_CLK\t\t\t\t\t138\n+#define GCC_SDCC2_APPS_CLK_SRC\t\t\t\t\t139\n+#define GCC_SDCC4_AHB_CLK\t\t\t\t\t140\n+#define GCC_SDCC4_APPS_CLK\t\t\t\t\t141\n+#define GCC_SDCC4_APPS_CLK_SRC\t\t\t\t\t142\n+#define GCC_SYS_NOC_CPUSS_AHB_CLK\t\t\t\t143\n+#define GCC_TSIF_AHB_CLK\t\t\t\t\t144\n+#define GCC_TSIF_INACTIVITY_TIMERS_CLK\t\t\t\t145\n+#define GCC_TSIF_REF_CLK\t\t\t\t\t146\n+#define GCC_TSIF_REF_CLK_SRC\t\t\t\t\t147\n+#define GCC_UFS_1X_CLKREF_EN\t\t\t\t\t148\n+#define GCC_UFS_CARD_AHB_CLK\t\t\t\t\t149\n+#define GCC_UFS_CARD_AXI_CLK\t\t\t\t\t150\n+#define GCC_UFS_CARD_AXI_CLK_SRC\t\t\t\t151\n+#define GCC_UFS_CARD_ICE_CORE_CLK\t\t\t\t152\n+#define GCC_UFS_CARD_ICE_CORE_CLK_SRC\t\t\t\t153\n+#define GCC_UFS_CARD_PHY_AUX_CLK\t\t\t\t154\n+#define GCC_UFS_CARD_PHY_AUX_CLK_SRC\t\t\t\t155\n+#define GCC_UFS_CARD_RX_SYMBOL_0_CLK\t\t\t\t156\n+#define GCC_UFS_CARD_RX_SYMBOL_1_CLK\t\t\t\t157\n+#define GCC_UFS_CARD_TX_SYMBOL_0_CLK\t\t\t\t158\n+#define GCC_UFS_CARD_UNIPRO_CORE_CLK\t\t\t\t159\n+#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC\t\t\t160\n+#define GCC_UFS_PHY_AHB_CLK\t\t\t\t\t161\n+#define GCC_UFS_PHY_AXI_CLK\t\t\t\t\t162\n+#define GCC_UFS_PHY_AXI_CLK_SRC\t\t\t\t\t163\n+#define GCC_UFS_PHY_ICE_CORE_CLK\t\t\t\t164\n+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC\t\t\t\t165\n+#define GCC_UFS_PHY_PHY_AUX_CLK\t\t\t\t\t166\n+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC\t\t\t\t167\n+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK\t\t\t\t168\n+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK\t\t\t\t169\n+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK\t\t\t\t170\n+#define GCC_UFS_PHY_UNIPRO_CORE_CLK\t\t\t\t171\n+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC\t\t\t\t172\n+#define GCC_USB30_PRIM_MASTER_CLK\t\t\t\t173\n+#define GCC_USB30_PRIM_MASTER_CLK_SRC\t\t\t\t174\n+#define GCC_USB30_PRIM_MOCK_UTMI_CLK\t\t\t\t175\n+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC\t\t\t176\n+#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC\t\t177\n+#define GCC_USB30_PRIM_SLEEP_CLK\t\t\t\t178\n+#define GCC_USB30_SEC_MASTER_CLK\t\t\t\t179\n+#define GCC_USB30_SEC_MASTER_CLK_SRC\t\t\t\t180\n+#define GCC_USB30_SEC_MOCK_UTMI_CLK\t\t\t\t181\n+#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC\t\t\t\t182\n+#define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC\t\t\t183\n+#define GCC_USB30_SEC_SLEEP_CLK\t\t\t\t\t184\n+#define GCC_USB3_PRIM_PHY_AUX_CLK\t\t\t\t185\n+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC\t\t\t\t186\n+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK\t\t\t\t187\n+#define GCC_USB3_PRIM_PHY_PIPE_CLK\t\t\t\t188\n+#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC\t\t\t\t189\n+#define GCC_USB3_SEC_CLKREF_EN\t\t\t\t\t190\n+#define GCC_USB3_SEC_PHY_AUX_CLK\t\t\t\t191\n+#define GCC_USB3_SEC_PHY_AUX_CLK_SRC\t\t\t\t192\n+#define GCC_USB3_SEC_PHY_COM_AUX_CLK\t\t\t\t193\n+#define GCC_USB3_SEC_PHY_PIPE_CLK\t\t\t\t194\n+#define GCC_USB3_SEC_PHY_PIPE_CLK_SRC\t\t\t\t195\n+#define GCC_VIDEO_AHB_CLK\t\t\t\t\t196\n+#define GCC_VIDEO_AXI0_CLK\t\t\t\t\t197\n+#define GCC_VIDEO_AXI1_CLK\t\t\t\t\t198\n+#define GCC_VIDEO_XO_CLK\t\t\t\t\t199\n+\n+/* GCC resets */\n+#define GCC_GPU_BCR\t\t\t\t\t\t0\n+#define GCC_MMSS_BCR\t\t\t\t\t\t1\n+#define GCC_NPU_BWMON_BCR\t\t\t\t\t2\n+#define GCC_NPU_BCR\t\t\t\t\t\t3\n+#define GCC_PCIE_0_BCR\t\t\t\t\t\t4\n+#define GCC_PCIE_0_LINK_DOWN_BCR\t\t\t\t5\n+#define GCC_PCIE_0_NOCSR_COM_PHY_BCR\t\t\t\t6\n+#define GCC_PCIE_0_PHY_BCR\t\t\t\t\t7\n+#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR\t\t\t8\n+#define GCC_PCIE_1_BCR\t\t\t\t\t\t9\n+#define GCC_PCIE_1_LINK_DOWN_BCR\t\t\t\t10\n+#define GCC_PCIE_1_NOCSR_COM_PHY_BCR\t\t\t\t11\n+#define GCC_PCIE_1_PHY_BCR\t\t\t\t\t12\n+#define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR\t\t\t13\n+#define GCC_PCIE_2_BCR\t\t\t\t\t\t14\n+#define GCC_PCIE_2_LINK_DOWN_BCR\t\t\t\t15\n+#define GCC_PCIE_2_NOCSR_COM_PHY_BCR\t\t\t\t16\n+#define GCC_PCIE_2_PHY_BCR\t\t\t\t\t17\n+#define GCC_PCIE_2_PHY_NOCSR_COM_PHY_BCR\t\t\t18\n+#define GCC_PCIE_PHY_BCR\t\t\t\t\t19\n+#define GCC_PCIE_PHY_CFG_AHB_BCR\t\t\t\t20\n+#define GCC_PCIE_PHY_COM_BCR\t\t\t\t\t21\n+#define GCC_PDM_BCR\t\t\t\t\t\t22\n+#define GCC_PRNG_BCR\t\t\t\t\t\t23\n+#define GCC_QUPV3_WRAPPER_0_BCR\t\t\t\t\t24\n+#define GCC_QUPV3_WRAPPER_1_BCR\t\t\t\t\t25\n+#define GCC_QUPV3_WRAPPER_2_BCR\t\t\t\t\t26\n+#define GCC_QUSB2PHY_PRIM_BCR\t\t\t\t\t27\n+#define GCC_QUSB2PHY_SEC_BCR\t\t\t\t\t28\n+#define GCC_SDCC2_BCR\t\t\t\t\t\t29\n+#define GCC_SDCC4_BCR\t\t\t\t\t\t30\n+#define GCC_TSIF_BCR\t\t\t\t\t\t31\n+#define GCC_UFS_CARD_BCR\t\t\t\t\t32\n+#define GCC_UFS_PHY_BCR\t\t\t\t\t\t33\n+#define GCC_USB30_PRIM_BCR\t\t\t\t\t34\n+#define GCC_USB30_SEC_BCR\t\t\t\t\t35\n+#define GCC_USB3_DP_PHY_PRIM_BCR\t\t\t\t36\n+#define GCC_USB3_DP_PHY_SEC_BCR\t\t\t\t\t37\n+#define GCC_USB3_PHY_PRIM_BCR\t\t\t\t\t38\n+#define GCC_USB3_PHY_SEC_BCR\t\t\t\t\t39\n+#define GCC_USB3PHY_PHY_PRIM_BCR\t\t\t\t40\n+#define GCC_USB3PHY_PHY_SEC_BCR\t\t\t\t\t41\n+#define GCC_USB_PHY_CFG_AHB2PHY_BCR\t\t\t\t42\n+#define GCC_VIDEO_AXI0_CLK_ARES\t\t\t\t\t43\n+#define GCC_VIDEO_AXI1_CLK_ARES\t\t\t\t\t44\n+\n+/* GCC power domains */\n+#define PCIE_0_GDSC\t\t\t\t\t\t0\n+#define PCIE_1_GDSC\t\t\t\t\t\t1\n+#define PCIE_2_GDSC\t\t\t\t\t\t2\n+#define UFS_CARD_GDSC\t\t\t\t\t\t3\n+#define UFS_PHY_GDSC\t\t\t\t\t\t4\n+#define USB30_PRIM_GDSC\t\t\t\t\t\t5\n+#define USB30_SEC_GDSC\t\t\t\t\t\t6\n+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC\t\t\t7\n+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC\t\t\t8\n+#define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC\t\t\t9\n+#define HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC\t\t\t10\n+\n+#endif\n", "prefixes": [ "03/17" ] }