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{
    "id": 1821139,
    "url": "http://patchwork.ozlabs.org/api/patches/1821139/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20230814215457.4075025-3-bhupesh.sharma@linaro.org/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20230814215457.4075025-3-bhupesh.sharma@linaro.org>",
    "list_archive_url": null,
    "date": "2023-08-14T21:54:42",
    "name": "[02/17] phy: qcom: Import QMP phy related header files from Linux",
    "commit_ref": null,
    "pull_url": null,
    "state": "changes-requested",
    "archived": false,
    "hash": "23c29789b343dda3a9b877eac93f90669299588a",
    "submitter": {
        "id": 81316,
        "url": "http://patchwork.ozlabs.org/api/people/81316/?format=api",
        "name": "Bhupesh Sharma",
        "email": "bhupesh.sharma@linaro.org"
    },
    "delegate": {
        "id": 3651,
        "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api",
        "username": "trini",
        "first_name": "Tom",
        "last_name": "Rini",
        "email": "trini@ti.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20230814215457.4075025-3-bhupesh.sharma@linaro.org/mbox/",
    "series": [
        {
            "id": 368803,
            "url": "http://patchwork.ozlabs.org/api/series/368803/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=368803",
            "date": "2023-08-14T21:54:40",
            "name": "Enable UFS on DragonBoard845c",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/368803/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/1821139/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/1821139/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Bhupesh Sharma <bhupesh.sharma@linaro.org>",
        "To": "u-boot@lists.denx.de",
        "Cc": "sjg@chromium.org, trini@konsulko.com, bhupesh.sharma@linaro.org,\n bhupesh.linux@gmail.com, marek.vasut+renesas@mailbox.org,\n sumit.garg@linaro.org, rfried.dev@gmail.com, patrice.chotard@foss.st.com,\n jbx6244@gmail.com, kever.yang@rock-chips.com, eugen.hristev@collabora.com",
        "Subject": "[PATCH 02/17] phy: qcom: Import QMP phy related header files from\n Linux",
        "Date": "Tue, 15 Aug 2023 03:24:42 +0530",
        "Message-Id": "<20230814215457.4075025-3-bhupesh.sharma@linaro.org>",
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    "content": "Import Qualcomm QMP phy related header files from Linux.\n\nSigned-off-by: Bhupesh Sharma <bhupesh.sharma@linaro.org>\n---\n drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v2.h    |  25 ++\n drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v3.h    |  21 ++\n drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v4.h    |  31 +++\n drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v5.h    |  32 +++\n drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v6.h    |  31 +++\n drivers/phy/qcom/phy-qcom-qmp-pcs-v2.h        |  43 ++++\n drivers/phy/qcom/phy-qcom-qmp-pcs-v3.h        | 145 +++++++++++\n drivers/phy/qcom/phy-qcom-qmp-pcs-v4.h        | 135 ++++++++++\n .../phy/qcom/phy-qcom-qmp-qserdes-com-v3.h    | 111 +++++++++\n .../phy/qcom/phy-qcom-qmp-qserdes-com-v4.h    | 123 +++++++++\n drivers/phy/qcom/phy-qcom-qmp-qserdes-com.h   | 140 +++++++++++\n drivers/phy/qcom/phy-qcom-qmp-qserdes-pll.h   |  66 +++++\n .../qcom/phy-qcom-qmp-qserdes-txrx-ufs-v6.h   |  30 +++\n .../phy/qcom/phy-qcom-qmp-qserdes-txrx-v3.h   |  68 +++++\n .../phy/qcom/phy-qcom-qmp-qserdes-txrx-v4.h   | 233 ++++++++++++++++++\n drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx.h  | 205 +++++++++++++++\n 16 files changed, 1439 insertions(+)\n create mode 100644 drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v2.h\n create mode 100644 drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v3.h\n create mode 100644 drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v4.h\n create mode 100644 drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v5.h\n create mode 100644 drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v6.h\n create mode 100644 drivers/phy/qcom/phy-qcom-qmp-pcs-v2.h\n create mode 100644 drivers/phy/qcom/phy-qcom-qmp-pcs-v3.h\n create mode 100644 drivers/phy/qcom/phy-qcom-qmp-pcs-v4.h\n create mode 100644 drivers/phy/qcom/phy-qcom-qmp-qserdes-com-v3.h\n create mode 100644 drivers/phy/qcom/phy-qcom-qmp-qserdes-com-v4.h\n create mode 100644 drivers/phy/qcom/phy-qcom-qmp-qserdes-com.h\n create mode 100644 drivers/phy/qcom/phy-qcom-qmp-qserdes-pll.h\n create mode 100644 drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-ufs-v6.h\n create mode 100644 drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v3.h\n create mode 100644 drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v4.h\n create mode 100644 drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx.h",
    "diff": "diff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v2.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v2.h\nnew file mode 100644\nindex 0000000000..a0803a8783\n--- /dev/null\n+++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v2.h\n@@ -0,0 +1,25 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.\n+ */\n+\n+#ifndef QCOM_PHY_QMP_PCS_UFS_V2_H_\n+#define QCOM_PHY_QMP_PCS_UFS_V2_H_\n+\n+#define QPHY_V2_PCS_UFS_PHY_START\t\t\t0x000\n+#define QPHY_V2_PCS_UFS_POWER_DOWN_CONTROL\t\t0x004\n+\n+#define QPHY_V2_PCS_UFS_TX_LARGE_AMP_DRV_LVL\t\t0x034\n+#define QPHY_V2_PCS_UFS_TX_LARGE_AMP_POST_EMP_LVL\t0x038\n+#define QPHY_V2_PCS_UFS_TX_SMALL_AMP_DRV_LVL\t\t0x03c\n+#define QPHY_V2_PCS_UFS_TX_SMALL_AMP_POST_EMP_LVL\t0x040\n+\n+#define QPHY_V2_PCS_UFS_RX_MIN_STALL_NOCONFIG_TIME_CAP\t0x0cc\n+#define QPHY_V2_PCS_UFS_RX_SYM_RESYNC_CTRL\t\t\t0x13c\n+#define QPHY_V2_PCS_UFS_RX_MIN_HIBERN8_TIME\t\t\t0x140\n+#define QPHY_V2_PCS_UFS_RX_SIGDET_CTRL2\t\t\t0x148\n+#define QPHY_V2_PCS_UFS_RX_PWM_GEAR_BAND\t\t\t0x154\n+\n+#define QPHY_V2_PCS_UFS_READY_STATUS\t\t\t0x168\n+\n+#endif\ndiff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v3.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v3.h\nnew file mode 100644\nindex 0000000000..adea13c3a9\n--- /dev/null\n+++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v3.h\n@@ -0,0 +1,21 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.\n+ */\n+\n+#ifndef QCOM_PHY_QMP_PCS_UFS_V3_H_\n+#define QCOM_PHY_QMP_PCS_UFS_V3_H_\n+\n+#define QPHY_V3_PCS_UFS_PHY_START\t\t\t0x000\n+#define QPHY_V3_PCS_UFS_POWER_DOWN_CONTROL\t\t0x004\n+#define QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL\t\t0x02c\n+#define QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL\t\t0x034\n+#define QPHY_V3_PCS_UFS_RX_SYM_RESYNC_CTRL\t\t0x134\n+#define QPHY_V3_PCS_UFS_RX_MIN_HIBERN8_TIME\t\t0x138\n+#define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL1\t\t\t0x13c\n+#define QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2\t\t\t0x140\n+#define QPHY_V3_PCS_UFS_READY_STATUS\t\t\t0x160\n+#define QPHY_V3_PCS_UFS_TX_MID_TERM_CTRL1\t\t0x1bc\n+#define QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1\t\t0x1c4\n+\n+#endif\ndiff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v4.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v4.h\nnew file mode 100644\nindex 0000000000..a1c7d3d171\n--- /dev/null\n+++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v4.h\n@@ -0,0 +1,31 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.\n+ */\n+\n+#ifndef QCOM_PHY_QMP_PCS_UFS_V4_H_\n+#define QCOM_PHY_QMP_PCS_UFS_V4_H_\n+\n+/* Only for QMP V4 PHY - UFS PCS registers */\n+#define QPHY_V4_PCS_UFS_PHY_START\t\t\t0x000\n+#define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL\t\t0x004\n+#define QPHY_V4_PCS_UFS_SW_RESET\t\t\t0x008\n+#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB\t0x00c\n+#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB\t0x010\n+#define QPHY_V4_PCS_UFS_PLL_CNTL\t\t\t0x02c\n+#define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL\t\t0x030\n+#define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL\t\t0x038\n+#define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL\t\t0x060\n+#define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY\t\t0x074\n+#define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY\t\t0x0b4\n+#define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL\t\t0x124\n+#define QPHY_V4_PCS_UFS_LINECFG_DISABLE\t\t\t0x148\n+#define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME\t\t0x150\n+#define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2\t\t\t0x158\n+#define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND\t\t0x160\n+#define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND\t\t\t0x168\n+#define QPHY_V4_PCS_UFS_READY_STATUS\t\t\t0x180\n+#define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1\t\t0x1d8\n+#define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1\t\t0x1e0\n+\n+#endif\ndiff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v5.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v5.h\nnew file mode 100644\nindex 0000000000..07959964fc\n--- /dev/null\n+++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v5.h\n@@ -0,0 +1,32 @@\n+/* Only for QMP V5 PHY - UFS PCS registers */\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.\n+ */\n+\n+#ifndef QCOM_PHY_QMP_PCS_UFS_V5_H_\n+#define QCOM_PHY_QMP_PCS_UFS_V5_H_\n+\n+/* Only for QMP V5 PHY - UFS PCS registers */\n+#define QPHY_V5_PCS_UFS_PHY_START\t\t\t0x000\n+#define QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL\t\t0x004\n+#define QPHY_V5_PCS_UFS_SW_RESET\t\t\t0x008\n+#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB\t0x00c\n+#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB\t0x010\n+#define QPHY_V5_PCS_UFS_PLL_CNTL\t\t\t0x02c\n+#define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL\t\t0x030\n+#define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL\t\t0x038\n+#define QPHY_V5_PCS_UFS_BIST_FIXED_PAT_CTRL\t\t0x060\n+#define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY\t\t0x074\n+#define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY\t\t0x0b4\n+#define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL\t\t0x124\n+#define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME\t\t0x150\n+#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1\t\t\t0x154\n+#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2\t\t\t0x158\n+#define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND\t\t0x160\n+#define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND\t\t\t0x168\n+#define QPHY_V5_PCS_UFS_READY_STATUS\t\t\t0x180\n+#define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1\t\t0x1d8\n+#define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1\t\t0x1e0\n+\n+#endif\ndiff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v6.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v6.h\nnew file mode 100644\nindex 0000000000..c23d5e41e2\n--- /dev/null\n+++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-ufs-v6.h\n@@ -0,0 +1,31 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) 2023, Linaro Limited\n+ */\n+\n+#ifndef QCOM_PHY_QMP_PCS_UFS_V6_H_\n+#define QCOM_PHY_QMP_PCS_UFS_V6_H_\n+\n+/* Only for QMP V6 PHY - UFS PCS registers */\n+#define QPHY_V6_PCS_UFS_PHY_START\t\t\t0x000\n+#define QPHY_V6_PCS_UFS_POWER_DOWN_CONTROL\t\t0x004\n+#define QPHY_V6_PCS_UFS_SW_RESET\t\t\t0x008\n+#define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB\t0x00c\n+#define QPHY_V6_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB\t0x010\n+#define QPHY_V6_PCS_UFS_PLL_CNTL\t\t\t0x02c\n+#define QPHY_V6_PCS_UFS_TX_LARGE_AMP_DRV_LVL\t\t0x030\n+#define QPHY_V6_PCS_UFS_TX_SMALL_AMP_DRV_LVL\t\t0x038\n+#define QPHY_V6_PCS_UFS_BIST_FIXED_PAT_CTRL\t\t0x060\n+#define QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY\t\t0x074\n+#define QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY\t\t0x0bc\n+#define QPHY_V6_PCS_UFS_DEBUG_BUS_CLKSEL\t\t0x158\n+#define QPHY_V6_PCS_UFS_LINECFG_DISABLE\t\t\t0x17c\n+#define QPHY_V6_PCS_UFS_RX_MIN_HIBERN8_TIME\t\t0x184\n+#define QPHY_V6_PCS_UFS_RX_SIGDET_CTRL2\t\t\t0x18c\n+#define QPHY_V6_PCS_UFS_TX_PWM_GEAR_BAND\t\t0x178\n+#define QPHY_V6_PCS_UFS_TX_HS_GEAR_BAND\t\t\t0x174\n+#define QPHY_V6_PCS_UFS_READY_STATUS\t\t\t0x1a8\n+#define QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1\t\t0x1f4\n+#define QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1\t\t0x1fc\n+\n+#endif\ndiff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-v2.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-v2.h\nnew file mode 100644\nindex 0000000000..bf36399d00\n--- /dev/null\n+++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-v2.h\n@@ -0,0 +1,43 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.\n+ */\n+\n+#ifndef QCOM_PHY_QMP_PCS_V2_H_\n+#define QCOM_PHY_QMP_PCS_V2_H_\n+\n+/* Only for QMP V2 PHY - PCS registers */\n+#define QPHY_V2_PCS_SW_RESET\t\t\t\t0x000\n+#define QPHY_V2_PCS_POWER_DOWN_CONTROL\t\t\t0x004\n+#define QPHY_V2_PCS_START_CONTROL\t\t\t0x008\n+#define QPHY_V2_PCS_TXDEEMPH_M6DB_V0\t\t\t0x024\n+#define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0\t\t\t0x028\n+#define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE\t\t0x054\n+#define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL\t\t\t0x058\n+#define QPHY_V2_PCS_POWER_STATE_CONFIG1\t\t\t0x060\n+#define QPHY_V2_PCS_POWER_STATE_CONFIG2\t\t\t0x064\n+#define QPHY_V2_PCS_POWER_STATE_CONFIG4\t\t\t0x06c\n+#define QPHY_V2_PCS_LOCK_DETECT_CONFIG1\t\t\t0x080\n+#define QPHY_V2_PCS_LOCK_DETECT_CONFIG2\t\t\t0x084\n+#define QPHY_V2_PCS_LOCK_DETECT_CONFIG3\t\t\t0x088\n+#define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK\t\t0x0a0\n+#define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK\t\t0x0a4\n+#define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME\t\t0x0a8\n+#define QPHY_V2_PCS_FLL_CNTRL1\t\t\t\t0x0c0\n+#define QPHY_V2_PCS_FLL_CNTRL2\t\t\t\t0x0c4\n+#define QPHY_V2_PCS_FLL_CNT_VAL_L\t\t\t0x0c8\n+#define QPHY_V2_PCS_FLL_CNT_VAL_H_TOL\t\t\t0x0cc\n+#define QPHY_V2_PCS_FLL_MAN_CODE\t\t\t0x0d0\n+#define QPHY_V2_PCS_AUTONOMOUS_MODE_CTRL\t\t0x0d4\n+#define QPHY_V2_PCS_LFPS_RXTERM_IRQ_CLEAR\t\t0x0d8\n+#define QPHY_V2_PCS_LFPS_RXTERM_IRQ_STATUS\t\t0x178\n+#define QPHY_V2_PCS_USB_PCS_STATUS\t\t\t0x17c /* USB */\n+#define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB\t0x1a8\n+#define QPHY_V2_PCS_OSC_DTCT_ACTIONS\t\t\t0x1ac\n+#define QPHY_V2_PCS_RX_SIGDET_LVL\t\t\t0x1d8\n+#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB\t0x1dc\n+#define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB\t0x1e0\n+\n+#define QPHY_V2_PCS_PCI_PCS_STATUS\t\t\t0x174 /* PCI */\n+\n+#endif\ndiff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-v3.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-v3.h\nnew file mode 100644\nindex 0000000000..10dbbb0062\n--- /dev/null\n+++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-v3.h\n@@ -0,0 +1,145 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.\n+ */\n+\n+#ifndef QCOM_PHY_QMP_PCS_V3_H_\n+#define QCOM_PHY_QMP_PCS_V3_H_\n+\n+/* Only for QMP V3 PHY - PCS registers */\n+#define QPHY_V3_PCS_SW_RESET\t\t\t\t0x000\n+#define QPHY_V3_PCS_POWER_DOWN_CONTROL\t\t\t0x004\n+#define QPHY_V3_PCS_START_CONTROL\t\t\t0x008\n+#define QPHY_V3_PCS_TXMGN_V0\t\t\t\t0x00c\n+#define QPHY_V3_PCS_TXMGN_V1\t\t\t\t0x010\n+#define QPHY_V3_PCS_TXMGN_V2\t\t\t\t0x014\n+#define QPHY_V3_PCS_TXMGN_V3\t\t\t\t0x018\n+#define QPHY_V3_PCS_TXMGN_V4\t\t\t\t0x01c\n+#define QPHY_V3_PCS_TXMGN_LS\t\t\t\t0x020\n+#define QPHY_V3_PCS_TXDEEMPH_M6DB_V0\t\t\t0x024\n+#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0\t\t\t0x028\n+#define QPHY_V3_PCS_TXDEEMPH_M6DB_V1\t\t\t0x02c\n+#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1\t\t\t0x030\n+#define QPHY_V3_PCS_TXDEEMPH_M6DB_V2\t\t\t0x034\n+#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2\t\t\t0x038\n+#define QPHY_V3_PCS_TXDEEMPH_M6DB_V3\t\t\t0x03c\n+#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3\t\t\t0x040\n+#define QPHY_V3_PCS_TXDEEMPH_M6DB_V4\t\t\t0x044\n+#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4\t\t\t0x048\n+#define QPHY_V3_PCS_TXDEEMPH_M6DB_LS\t\t\t0x04c\n+#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS\t\t\t0x050\n+#define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE\t\t0x054\n+#define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL\t\t\t0x058\n+#define QPHY_V3_PCS_RATE_SLEW_CNTRL\t\t\t0x05c\n+#define QPHY_V3_PCS_POWER_STATE_CONFIG1\t\t\t0x060\n+#define QPHY_V3_PCS_POWER_STATE_CONFIG2\t\t\t0x064\n+#define QPHY_V3_PCS_POWER_STATE_CONFIG3\t\t\t0x068\n+#define QPHY_V3_PCS_POWER_STATE_CONFIG4\t\t\t0x06c\n+#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L\t\t0x070\n+#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H\t\t0x074\n+#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L\t\t\t0x078\n+#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H\t\t\t0x07c\n+#define QPHY_V3_PCS_LOCK_DETECT_CONFIG1\t\t\t0x080\n+#define QPHY_V3_PCS_LOCK_DETECT_CONFIG2\t\t\t0x084\n+#define QPHY_V3_PCS_LOCK_DETECT_CONFIG3\t\t\t0x088\n+#define QPHY_V3_PCS_TSYNC_RSYNC_TIME\t\t\t0x08c\n+#define QPHY_V3_PCS_SIGDET_LOW_2_IDLE_TIME\t\t0x090\n+#define QPHY_V3_PCS_BEACON_2_IDLE_TIME_L\t\t0x094\n+#define QPHY_V3_PCS_BEACON_2_IDLE_TIME_H\t\t0x098\n+#define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_SYSCLK\t\t0x09c\n+#define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK\t\t0x0a0\n+#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK\t\t0x0a4\n+#define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME\t\t0x0a8\n+#define QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL\t\t0x0ac\n+#define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK\t\t0x0b0\n+#define QPHY_V3_PCS_LFPS_TX_END_CNT_P2U3_START\t\t0x0b4\n+#define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME\t\t0x0b8\n+#define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME\t\t0x0bc\n+#define QPHY_V3_PCS_TXONESZEROS_RUN_LENGTH\t\t0x0c0\n+#define QPHY_V3_PCS_FLL_CNTRL1\t\t\t\t0x0c4\n+#define QPHY_V3_PCS_FLL_CNTRL2\t\t\t\t0x0c8\n+#define QPHY_V3_PCS_FLL_CNT_VAL_L\t\t\t0x0cc\n+#define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL\t\t\t0x0d0\n+#define QPHY_V3_PCS_FLL_MAN_CODE\t\t\t0x0d4\n+#define QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL\t\t0x0d8\n+#define QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR\t\t0x0dc\n+#define QPHY_V3_PCS_ARCVR_DTCT_EN_PERIOD\t\t0x0e0\n+#define QPHY_V3_PCS_ARCVR_DTCT_CM_DLY\t\t\t0x0e4\n+#define QPHY_V3_PCS_ALFPS_DEGLITCH_VAL\t\t\t0x0e8\n+#define QPHY_V3_PCS_INSIG_SW_CTRL1\t\t\t0x0ec\n+#define QPHY_V3_PCS_INSIG_SW_CTRL2\t\t\t0x0f0\n+#define QPHY_V3_PCS_INSIG_SW_CTRL3\t\t\t0x0f4\n+#define QPHY_V3_PCS_INSIG_MX_CTRL1\t\t\t0x0f8\n+#define QPHY_V3_PCS_INSIG_MX_CTRL2\t\t\t0x0fc\n+#define QPHY_V3_PCS_INSIG_MX_CTRL3\t\t\t0x100\n+#define QPHY_V3_PCS_OUTSIG_SW_CTRL1\t\t\t0x104\n+#define QPHY_V3_PCS_OUTSIG_MX_CTRL1\t\t\t0x108\n+#define QPHY_V3_PCS_CLK_DEBUG_BYPASS_CTRL\t\t0x10c\n+#define QPHY_V3_PCS_TEST_CONTROL\t\t\t0x110\n+#define QPHY_V3_PCS_TEST_CONTROL2\t\t\t0x114\n+#define QPHY_V3_PCS_TEST_CONTROL3\t\t\t0x118\n+#define QPHY_V3_PCS_TEST_CONTROL4\t\t\t0x11c\n+#define QPHY_V3_PCS_TEST_CONTROL5\t\t\t0x120\n+#define QPHY_V3_PCS_TEST_CONTROL6\t\t\t0x124\n+#define QPHY_V3_PCS_TEST_CONTROL7\t\t\t0x128\n+#define QPHY_V3_PCS_COM_RESET_CONTROL\t\t\t0x12c\n+#define QPHY_V3_PCS_BIST_CTRL\t\t\t\t0x130\n+#define QPHY_V3_PCS_PRBS_POLY0\t\t\t\t0x134\n+#define QPHY_V3_PCS_PRBS_POLY1\t\t\t\t0x138\n+#define QPHY_V3_PCS_PRBS_SEED0\t\t\t\t0x13c\n+#define QPHY_V3_PCS_PRBS_SEED1\t\t\t\t0x140\n+#define QPHY_V3_PCS_FIXED_PAT_CTRL\t\t\t0x144\n+#define QPHY_V3_PCS_FIXED_PAT0\t\t\t\t0x148\n+#define QPHY_V3_PCS_FIXED_PAT1\t\t\t\t0x14c\n+#define QPHY_V3_PCS_FIXED_PAT2\t\t\t\t0x150\n+#define QPHY_V3_PCS_FIXED_PAT3\t\t\t\t0x154\n+#define QPHY_V3_PCS_COM_CLK_SWITCH_CTRL\t\t\t0x158\n+#define QPHY_V3_PCS_ELECIDLE_DLY_SEL\t\t\t0x15c\n+#define QPHY_V3_PCS_SPARE1\t\t\t\t0x160\n+#define QPHY_V3_PCS_BIST_CHK_ERR_CNT_L_STATUS\t\t0x164\n+#define QPHY_V3_PCS_BIST_CHK_ERR_CNT_H_STATUS\t\t0x168\n+#define QPHY_V3_PCS_BIST_CHK_STATUS\t\t\t0x16c\n+#define QPHY_V3_PCS_LFPS_RXTERM_IRQ_SOURCE_STATUS\t0x170\n+#define QPHY_V3_PCS_PCS_STATUS\t\t\t\t0x174\n+#define QPHY_V3_PCS_PCS_STATUS2\t\t\t\t0x178\n+#define QPHY_V3_PCS_PCS_STATUS3\t\t\t\t0x17c\n+#define QPHY_V3_PCS_COM_RESET_STATUS\t\t\t0x180\n+#define QPHY_V3_PCS_OSC_DTCT_STATUS\t\t\t0x184\n+#define QPHY_V3_PCS_REVISION_ID0\t\t\t0x188\n+#define QPHY_V3_PCS_REVISION_ID1\t\t\t0x18c\n+#define QPHY_V3_PCS_REVISION_ID2\t\t\t0x190\n+#define QPHY_V3_PCS_REVISION_ID3\t\t\t0x194\n+#define QPHY_V3_PCS_DEBUG_BUS_0_STATUS\t\t\t0x198\n+#define QPHY_V3_PCS_DEBUG_BUS_1_STATUS\t\t\t0x19c\n+#define QPHY_V3_PCS_DEBUG_BUS_2_STATUS\t\t\t0x1a0\n+#define QPHY_V3_PCS_DEBUG_BUS_3_STATUS\t\t\t0x1a4\n+#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB\t0x1a8\n+#define QPHY_V3_PCS_OSC_DTCT_ACTIONS\t\t\t0x1ac\n+#define QPHY_V3_PCS_SIGDET_CNTRL\t\t\t0x1b0\n+#define QPHY_V3_PCS_IDAC_CAL_CNTRL\t\t\t0x1b4\n+#define QPHY_V3_PCS_CMN_ACK_OUT_SEL\t\t\t0x1b8\n+#define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME_SYSCLK\t0x1bc\n+#define QPHY_V3_PCS_AUTONOMOUS_MODE_STATUS\t\t0x1c0\n+#define QPHY_V3_PCS_ENDPOINT_REFCLK_CNTRL\t\t0x1c4\n+#define QPHY_V3_PCS_EPCLK_PRE_PLL_LOCK_DLY_SYSCLK\t0x1c8\n+#define QPHY_V3_PCS_EPCLK_PRE_PLL_LOCK_DLY_AUXCLK\t0x1cc\n+#define QPHY_V3_PCS_EPCLK_DLY_COUNT_VAL_L\t\t0x1d0\n+#define QPHY_V3_PCS_EPCLK_DLY_COUNT_VAL_H\t\t0x1d4\n+#define QPHY_V3_PCS_RX_SIGDET_LVL\t\t\t0x1d8\n+#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB\t0x1dc\n+#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB\t0x1e0\n+#define QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL2\t\t0x1e4\n+#define QPHY_V3_PCS_RXTERMINATION_DLY_SEL\t\t0x1e8\n+#define QPHY_V3_PCS_LFPS_PER_TIMER_VAL\t\t\t0x1ec\n+#define QPHY_V3_PCS_SIGDET_STARTUP_TIMER_VAL\t\t0x1f0\n+#define QPHY_V3_PCS_LOCK_DETECT_CONFIG4\t\t\t0x1f4\n+#define QPHY_V3_PCS_RX_SIGDET_DTCT_CNTRL\t\t0x1f8\n+#define QPHY_V3_PCS_PCS_STATUS4\t\t\t\t0x1fc\n+#define QPHY_V3_PCS_PCS_STATUS4_CLEAR\t\t\t0x200\n+#define QPHY_V3_PCS_DEC_ERROR_COUNT_STATUS\t\t0x204\n+#define QPHY_V3_PCS_COMMA_POS_STATUS\t\t\t0x208\n+#define QPHY_V3_PCS_REFGEN_REQ_CONFIG1\t\t\t0x20c\n+#define QPHY_V3_PCS_REFGEN_REQ_CONFIG2\t\t\t0x210\n+#define QPHY_V3_PCS_REFGEN_REQ_CONFIG3\t\t\t0x214\n+\n+#endif\ndiff --git a/drivers/phy/qcom/phy-qcom-qmp-pcs-v4.h b/drivers/phy/qcom/phy-qcom-qmp-pcs-v4.h\nnew file mode 100644\nindex 0000000000..a2c1eba2b6\n--- /dev/null\n+++ b/drivers/phy/qcom/phy-qcom-qmp-pcs-v4.h\n@@ -0,0 +1,135 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.\n+ */\n+\n+#ifndef QCOM_PHY_QMP_PCS_V4_H_\n+#define QCOM_PHY_QMP_PCS_V4_H_\n+\n+/* Only for QMP V4 PHY - USB/PCIe PCS registers */\n+#define QPHY_V4_PCS_SW_RESET\t\t\t\t0x000\n+#define QPHY_V4_PCS_REVISION_ID0\t\t\t0x004\n+#define QPHY_V4_PCS_REVISION_ID1\t\t\t0x008\n+#define QPHY_V4_PCS_REVISION_ID2\t\t\t0x00c\n+#define QPHY_V4_PCS_REVISION_ID3\t\t\t0x010\n+#define QPHY_V4_PCS_PCS_STATUS1\t\t\t\t0x014\n+#define QPHY_V4_PCS_PCS_STATUS2\t\t\t\t0x018\n+#define QPHY_V4_PCS_PCS_STATUS3\t\t\t\t0x01c\n+#define QPHY_V4_PCS_PCS_STATUS4\t\t\t\t0x020\n+#define QPHY_V4_PCS_PCS_STATUS5\t\t\t\t0x024\n+#define QPHY_V4_PCS_PCS_STATUS6\t\t\t\t0x028\n+#define QPHY_V4_PCS_PCS_STATUS7\t\t\t\t0x02c\n+#define QPHY_V4_PCS_DEBUG_BUS_0_STATUS\t\t\t0x030\n+#define QPHY_V4_PCS_DEBUG_BUS_1_STATUS\t\t\t0x034\n+#define QPHY_V4_PCS_DEBUG_BUS_2_STATUS\t\t\t0x038\n+#define QPHY_V4_PCS_DEBUG_BUS_3_STATUS\t\t\t0x03c\n+#define QPHY_V4_PCS_POWER_DOWN_CONTROL\t\t\t0x040\n+#define QPHY_V4_PCS_START_CONTROL\t\t\t0x044\n+#define QPHY_V4_PCS_INSIG_SW_CTRL1\t\t\t0x048\n+#define QPHY_V4_PCS_INSIG_SW_CTRL2\t\t\t0x04c\n+#define QPHY_V4_PCS_INSIG_SW_CTRL3\t\t\t0x050\n+#define QPHY_V4_PCS_INSIG_SW_CTRL4\t\t\t0x054\n+#define QPHY_V4_PCS_INSIG_SW_CTRL5\t\t\t0x058\n+#define QPHY_V4_PCS_INSIG_SW_CTRL6\t\t\t0x05c\n+#define QPHY_V4_PCS_INSIG_SW_CTRL7\t\t\t0x060\n+#define QPHY_V4_PCS_INSIG_SW_CTRL8\t\t\t0x064\n+#define QPHY_V4_PCS_INSIG_MX_CTRL1\t\t\t0x068\n+#define QPHY_V4_PCS_INSIG_MX_CTRL2\t\t\t0x06c\n+#define QPHY_V4_PCS_INSIG_MX_CTRL3\t\t\t0x070\n+#define QPHY_V4_PCS_INSIG_MX_CTRL4\t\t\t0x074\n+#define QPHY_V4_PCS_INSIG_MX_CTRL5\t\t\t0x078\n+#define QPHY_V4_PCS_INSIG_MX_CTRL7\t\t\t0x07c\n+#define QPHY_V4_PCS_INSIG_MX_CTRL8\t\t\t0x080\n+#define QPHY_V4_PCS_OUTSIG_SW_CTRL1\t\t\t0x084\n+#define QPHY_V4_PCS_OUTSIG_MX_CTRL1\t\t\t0x088\n+#define QPHY_V4_PCS_CLAMP_ENABLE\t\t\t0x08c\n+#define QPHY_V4_PCS_POWER_STATE_CONFIG1\t\t\t0x090\n+#define QPHY_V4_PCS_POWER_STATE_CONFIG2\t\t\t0x094\n+#define QPHY_V4_PCS_FLL_CNTRL1\t\t\t\t0x098\n+#define QPHY_V4_PCS_FLL_CNTRL2\t\t\t\t0x09c\n+#define QPHY_V4_PCS_FLL_CNT_VAL_L\t\t\t0x0a0\n+#define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL\t\t\t0x0a4\n+#define QPHY_V4_PCS_FLL_MAN_CODE\t\t\t0x0a8\n+#define QPHY_V4_PCS_TEST_CONTROL1\t\t\t0x0ac\n+#define QPHY_V4_PCS_TEST_CONTROL2\t\t\t0x0b0\n+#define QPHY_V4_PCS_TEST_CONTROL3\t\t\t0x0b4\n+#define QPHY_V4_PCS_TEST_CONTROL4\t\t\t0x0b8\n+#define QPHY_V4_PCS_TEST_CONTROL5\t\t\t0x0bc\n+#define QPHY_V4_PCS_TEST_CONTROL6\t\t\t0x0c0\n+#define QPHY_V4_PCS_LOCK_DETECT_CONFIG1\t\t\t0x0c4\n+#define QPHY_V4_PCS_LOCK_DETECT_CONFIG2\t\t\t0x0c8\n+#define QPHY_V4_PCS_LOCK_DETECT_CONFIG3\t\t\t0x0cc\n+#define QPHY_V4_PCS_LOCK_DETECT_CONFIG4\t\t\t0x0d0\n+#define QPHY_V4_PCS_LOCK_DETECT_CONFIG5\t\t\t0x0d4\n+#define QPHY_V4_PCS_LOCK_DETECT_CONFIG6\t\t\t0x0d8\n+#define QPHY_V4_PCS_REFGEN_REQ_CONFIG1\t\t\t0x0dc\n+#define QPHY_V4_PCS_REFGEN_REQ_CONFIG2\t\t\t0x0e0\n+#define QPHY_V4_PCS_REFGEN_REQ_CONFIG3\t\t\t0x0e4\n+#define QPHY_V4_PCS_BIST_CTRL\t\t\t\t0x0e8\n+#define QPHY_V4_PCS_PRBS_POLY0\t\t\t\t0x0ec\n+#define QPHY_V4_PCS_PRBS_POLY1\t\t\t\t0x0f0\n+#define QPHY_V4_PCS_FIXED_PAT0\t\t\t\t0x0f4\n+#define QPHY_V4_PCS_FIXED_PAT1\t\t\t\t0x0f8\n+#define QPHY_V4_PCS_FIXED_PAT2\t\t\t\t0x0fc\n+#define QPHY_V4_PCS_FIXED_PAT3\t\t\t\t0x100\n+#define QPHY_V4_PCS_FIXED_PAT4\t\t\t\t0x104\n+#define QPHY_V4_PCS_FIXED_PAT5\t\t\t\t0x108\n+#define QPHY_V4_PCS_FIXED_PAT6\t\t\t\t0x10c\n+#define QPHY_V4_PCS_FIXED_PAT7\t\t\t\t0x110\n+#define QPHY_V4_PCS_FIXED_PAT8\t\t\t\t0x114\n+#define QPHY_V4_PCS_FIXED_PAT9\t\t\t\t0x118\n+#define QPHY_V4_PCS_FIXED_PAT10\t\t\t\t0x11c\n+#define QPHY_V4_PCS_FIXED_PAT11\t\t\t\t0x120\n+#define QPHY_V4_PCS_FIXED_PAT12\t\t\t\t0x124\n+#define QPHY_V4_PCS_FIXED_PAT13\t\t\t\t0x128\n+#define QPHY_V4_PCS_FIXED_PAT14\t\t\t\t0x12c\n+#define QPHY_V4_PCS_FIXED_PAT15\t\t\t\t0x130\n+#define QPHY_V4_PCS_TXMGN_CONFIG\t\t\t0x134\n+#define QPHY_V4_PCS_G12S1_TXMGN_V0\t\t\t0x138\n+#define QPHY_V4_PCS_G12S1_TXMGN_V1\t\t\t0x13c\n+#define QPHY_V4_PCS_G12S1_TXMGN_V2\t\t\t0x140\n+#define QPHY_V4_PCS_G12S1_TXMGN_V3\t\t\t0x144\n+#define QPHY_V4_PCS_G12S1_TXMGN_V4\t\t\t0x148\n+#define QPHY_V4_PCS_G12S1_TXMGN_V0_RS\t\t\t0x14c\n+#define QPHY_V4_PCS_G12S1_TXMGN_V1_RS\t\t\t0x150\n+#define QPHY_V4_PCS_G12S1_TXMGN_V2_RS\t\t\t0x154\n+#define QPHY_V4_PCS_G12S1_TXMGN_V3_RS\t\t\t0x158\n+#define QPHY_V4_PCS_G12S1_TXMGN_V4_RS\t\t\t0x15c\n+#define QPHY_V4_PCS_G3S2_TXMGN_MAIN\t\t\t0x160\n+#define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS\t\t\t0x164\n+#define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB\t\t\t0x168\n+#define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB\t\t0x16c\n+#define QPHY_V4_PCS_G3S2_PRE_GAIN\t\t\t0x170\n+#define QPHY_V4_PCS_G3S2_POST_GAIN\t\t\t0x174\n+#define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET\t\t0x178\n+#define QPHY_V4_PCS_G3S2_PRE_GAIN_RS\t\t\t0x17c\n+#define QPHY_V4_PCS_G3S2_POST_GAIN_RS\t\t\t0x180\n+#define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS\t\t0x184\n+#define QPHY_V4_PCS_RX_SIGDET_LVL\t\t\t0x188\n+#define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL\t\t0x18c\n+#define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L\t\t0x190\n+#define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H\t\t0x194\n+#define QPHY_V4_PCS_RATE_SLEW_CNTRL1\t\t\t0x198\n+#define QPHY_V4_PCS_RATE_SLEW_CNTRL2\t\t\t0x19c\n+#define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK\t\t0x1a0\n+#define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L\t0x1a4\n+#define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H\t0x1a8\n+#define QPHY_V4_PCS_TSYNC_RSYNC_TIME\t\t\t0x1ac\n+#define QPHY_V4_PCS_CDR_RESET_TIME\t\t\t0x1b0\n+#define QPHY_V4_PCS_TSYNC_DLY_TIME\t\t\t0x1b4\n+#define QPHY_V4_PCS_ELECIDLE_DLY_SEL\t\t\t0x1b8\n+#define QPHY_V4_PCS_CMN_ACK_OUT_SEL\t\t\t0x1bc\n+#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1\t\t0x1c0\n+#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2\t\t0x1c4\n+#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3\t\t0x1c8\n+#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4\t\t0x1cc\n+#define QPHY_V4_PCS_PCS_TX_RX_CONFIG\t\t\t0x1d0\n+#define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL\t\t\t0x1d4\n+#define QPHY_V4_PCS_RX_DCC_CAL_CONFIG\t\t\t0x1d8\n+#define QPHY_V4_PCS_EQ_CONFIG1\t\t\t\t0x1dc\n+#define QPHY_V4_PCS_EQ_CONFIG2\t\t\t\t0x1e0\n+#define QPHY_V4_PCS_EQ_CONFIG3\t\t\t\t0x1e4\n+#define QPHY_V4_PCS_EQ_CONFIG4\t\t\t\t0x1e8\n+#define QPHY_V4_PCS_EQ_CONFIG5\t\t\t\t0x1ec\n+\n+#endif\ndiff --git a/drivers/phy/qcom/phy-qcom-qmp-qserdes-com-v3.h b/drivers/phy/qcom/phy-qcom-qmp-qserdes-com-v3.h\nnew file mode 100644\nindex 0000000000..c0bd54e0e7\n--- /dev/null\n+++ b/drivers/phy/qcom/phy-qcom-qmp-qserdes-com-v3.h\n@@ -0,0 +1,111 @@\n+\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.\n+ */\n+\n+#ifndef QCOM_PHY_QMP_QSERDES_COM_V3_H_\n+#define QCOM_PHY_QMP_QSERDES_COM_V3_H_\n+\n+/* Only for QMP V3 PHY - QSERDES COM registers */\n+#define QSERDES_V3_COM_ATB_SEL1\t\t\t\t0x000\n+#define QSERDES_V3_COM_ATB_SEL2\t\t\t\t0x004\n+#define QSERDES_V3_COM_FREQ_UPDATE\t\t\t0x008\n+#define QSERDES_V3_COM_BG_TIMER\t\t\t\t0x00c\n+#define QSERDES_V3_COM_SSC_EN_CENTER\t\t\t0x010\n+#define QSERDES_V3_COM_SSC_ADJ_PER1\t\t\t0x014\n+#define QSERDES_V3_COM_SSC_ADJ_PER2\t\t\t0x018\n+#define QSERDES_V3_COM_SSC_PER1\t\t\t\t0x01c\n+#define QSERDES_V3_COM_SSC_PER2\t\t\t\t0x020\n+#define QSERDES_V3_COM_SSC_STEP_SIZE1\t\t\t0x024\n+#define QSERDES_V3_COM_SSC_STEP_SIZE2\t\t\t0x028\n+#define QSERDES_V3_COM_POST_DIV\t\t\t\t0x02c\n+#define QSERDES_V3_COM_POST_DIV_MUX\t\t\t0x030\n+#define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN\t\t0x034\n+#define QSERDES_V3_COM_CLK_ENABLE1\t\t\t0x038\n+#define QSERDES_V3_COM_SYS_CLK_CTRL\t\t\t0x03c\n+#define QSERDES_V3_COM_SYSCLK_BUF_ENABLE\t\t0x040\n+#define QSERDES_V3_COM_PLL_EN\t\t\t\t0x044\n+#define QSERDES_V3_COM_PLL_IVCO\t\t\t\t0x048\n+#define QSERDES_V3_COM_CMN_IETRIM\t\t\t0x04c\n+#define QSERDES_V3_COM_CMN_IPTRIM\t\t\t0x050\n+#define QSERDES_V3_COM_EP_CLOCK_DETECT_CTR\t\t0x054\n+#define QSERDES_V3_COM_SYSCLK_DET_COMP_STATUS\t\t0x058\n+#define QSERDES_V3_COM_CLK_EP_DIV\t\t\t0x05c\n+#define QSERDES_V3_COM_CP_CTRL_MODE0\t\t\t0x060\n+#define QSERDES_V3_COM_CP_CTRL_MODE1\t\t\t0x064\n+#define QSERDES_V3_COM_PLL_RCTRL_MODE0\t\t\t0x068\n+#define QSERDES_V3_COM_PLL_RCTRL_MODE1\t\t\t0x06c\n+#define QSERDES_V3_COM_PLL_CCTRL_MODE0\t\t\t0x070\n+#define QSERDES_V3_COM_PLL_CCTRL_MODE1\t\t\t0x074\n+#define QSERDES_V3_COM_PLL_CNTRL\t\t\t0x078\n+#define QSERDES_V3_COM_BIAS_EN_CTRL_BY_PSM\t\t0x07c\n+#define QSERDES_V3_COM_SYSCLK_EN_SEL\t\t\t0x080\n+#define QSERDES_V3_COM_CML_SYSCLK_SEL\t\t\t0x084\n+#define QSERDES_V3_COM_RESETSM_CNTRL\t\t\t0x088\n+#define QSERDES_V3_COM_RESETSM_CNTRL2\t\t\t0x08c\n+#define QSERDES_V3_COM_LOCK_CMP_EN\t\t\t0x090\n+#define QSERDES_V3_COM_LOCK_CMP_CFG\t\t\t0x094\n+#define QSERDES_V3_COM_LOCK_CMP1_MODE0\t\t\t0x098\n+#define QSERDES_V3_COM_LOCK_CMP2_MODE0\t\t\t0x09c\n+#define QSERDES_V3_COM_LOCK_CMP3_MODE0\t\t\t0x0a0\n+#define QSERDES_V3_COM_LOCK_CMP1_MODE1\t\t\t0x0a4\n+#define QSERDES_V3_COM_LOCK_CMP2_MODE1\t\t\t0x0a8\n+#define QSERDES_V3_COM_LOCK_CMP3_MODE1\t\t\t0x0ac\n+#define QSERDES_V3_COM_DEC_START_MODE0\t\t\t0x0b0\n+#define QSERDES_V3_COM_DEC_START_MODE1\t\t\t0x0b4\n+#define QSERDES_V3_COM_DIV_FRAC_START1_MODE0\t\t0x0b8\n+#define QSERDES_V3_COM_DIV_FRAC_START2_MODE0\t\t0x0bc\n+#define QSERDES_V3_COM_DIV_FRAC_START3_MODE0\t\t0x0c0\n+#define QSERDES_V3_COM_DIV_FRAC_START1_MODE1\t\t0x0c4\n+#define QSERDES_V3_COM_DIV_FRAC_START2_MODE1\t\t0x0c8\n+#define QSERDES_V3_COM_DIV_FRAC_START3_MODE1\t\t0x0cc\n+#define QSERDES_V3_COM_INTEGLOOP_INITVAL\t\t0x0d0\n+#define QSERDES_V3_COM_INTEGLOOP_EN\t\t\t0x0d4\n+#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0\t\t0x0d8\n+#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0\t\t0x0dc\n+#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1\t\t0x0e0\n+#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1\t\t0x0e4\n+#define QSERDES_V3_COM_VCOCAL_DEADMAN_CTRL\t\t0x0e8\n+#define QSERDES_V3_COM_VCO_TUNE_CTRL\t\t\t0x0ec\n+#define QSERDES_V3_COM_VCO_TUNE_MAP\t\t\t0x0f0\n+#define QSERDES_V3_COM_VCO_TUNE1_MODE0\t\t\t0x0f4\n+#define QSERDES_V3_COM_VCO_TUNE2_MODE0\t\t\t0x0f8\n+#define QSERDES_V3_COM_VCO_TUNE1_MODE1\t\t\t0x0fc\n+#define QSERDES_V3_COM_VCO_TUNE2_MODE1\t\t\t0x100\n+#define QSERDES_V3_COM_VCO_TUNE_INITVAL1\t\t0x104\n+#define QSERDES_V3_COM_VCO_TUNE_INITVAL2\t\t0x108\n+#define QSERDES_V3_COM_VCO_TUNE_MINVAL1\t\t\t0x10c\n+#define QSERDES_V3_COM_VCO_TUNE_MINVAL2\t\t\t0x110\n+#define QSERDES_V3_COM_VCO_TUNE_MAXVAL1\t\t\t0x114\n+#define QSERDES_V3_COM_VCO_TUNE_MAXVAL2\t\t\t0x118\n+#define QSERDES_V3_COM_VCO_TUNE_TIMER1\t\t\t0x11c\n+#define QSERDES_V3_COM_VCO_TUNE_TIMER2\t\t\t0x120\n+#define QSERDES_V3_COM_CMN_STATUS\t\t\t0x124\n+#define QSERDES_V3_COM_RESET_SM_STATUS\t\t\t0x128\n+#define QSERDES_V3_COM_RESTRIM_CODE_STATUS\t\t0x12c\n+#define QSERDES_V3_COM_PLLCAL_CODE1_STATUS\t\t0x130\n+#define QSERDES_V3_COM_PLLCAL_CODE2_STATUS\t\t0x134\n+#define QSERDES_V3_COM_CLK_SELECT\t\t\t0x138\n+#define QSERDES_V3_COM_HSCLK_SEL\t\t\t0x13c\n+#define QSERDES_V3_COM_INTEGLOOP_BINCODE_STATUS\t\t0x140\n+#define QSERDES_V3_COM_PLL_ANALOG\t\t\t0x144\n+#define QSERDES_V3_COM_CORECLK_DIV_MODE0\t\t0x148\n+#define QSERDES_V3_COM_CORECLK_DIV_MODE1\t\t0x14c\n+#define QSERDES_V3_COM_SW_RESET\t\t\t\t0x150\n+#define QSERDES_V3_COM_CORE_CLK_EN\t\t\t0x154\n+#define QSERDES_V3_COM_C_READY_STATUS\t\t\t0x158\n+#define QSERDES_V3_COM_CMN_CONFIG\t\t\t0x15c\n+#define QSERDES_V3_COM_CMN_RATE_OVERRIDE\t\t0x160\n+#define QSERDES_V3_COM_SVS_MODE_CLK_SEL\t\t\t0x164\n+#define QSERDES_V3_COM_DEBUG_BUS0\t\t\t0x168\n+#define QSERDES_V3_COM_DEBUG_BUS1\t\t\t0x16c\n+#define QSERDES_V3_COM_DEBUG_BUS2\t\t\t0x170\n+#define QSERDES_V3_COM_DEBUG_BUS3\t\t\t0x174\n+#define QSERDES_V3_COM_DEBUG_BUS_SEL\t\t\t0x178\n+#define QSERDES_V3_COM_CMN_MISC1\t\t\t0x17c\n+#define QSERDES_V3_COM_CMN_MISC2\t\t\t0x180\n+#define QSERDES_V3_COM_CMN_MODE\t\t\t\t0x184\n+#define QSERDES_V3_COM_CMN_VREG_SEL\t\t\t0x188\n+\n+#endif\ndiff --git a/drivers/phy/qcom/phy-qcom-qmp-qserdes-com-v4.h b/drivers/phy/qcom/phy-qcom-qmp-qserdes-com-v4.h\nnew file mode 100644\nindex 0000000000..b0e3298d99\n--- /dev/null\n+++ b/drivers/phy/qcom/phy-qcom-qmp-qserdes-com-v4.h\n@@ -0,0 +1,123 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.\n+ */\n+\n+#ifndef QCOM_PHY_QMP_QSERDES_COM_V4_H_\n+#define QCOM_PHY_QMP_QSERDES_COM_V4_H_\n+\n+/* Only for QMP V4 PHY - QSERDES COM registers */\n+#define QSERDES_V4_COM_ATB_SEL1\t\t\t\t0x000\n+#define QSERDES_V4_COM_ATB_SEL2\t\t\t\t0x004\n+#define QSERDES_V4_COM_FREQ_UPDATE\t\t\t0x008\n+#define QSERDES_V4_COM_BG_TIMER\t\t\t\t0x00c\n+#define QSERDES_V4_COM_SSC_EN_CENTER\t\t\t0x010\n+#define QSERDES_V4_COM_SSC_ADJ_PER1\t\t\t0x014\n+#define QSERDES_V4_COM_SSC_ADJ_PER2\t\t\t0x018\n+#define QSERDES_V4_COM_SSC_PER1\t\t\t\t0x01c\n+#define QSERDES_V4_COM_SSC_PER2\t\t\t\t0x020\n+#define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0\t\t0x024\n+#define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0\t\t0x028\n+#define QSERDES_V4_COM_SSC_STEP_SIZE3_MODE0\t\t0x02c\n+#define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1\t\t0x030\n+#define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1\t\t0x034\n+#define QSERDES_V4_COM_SSC_STEP_SIZE3_MODE1\t\t0x038\n+#define QSERDES_V4_COM_POST_DIV\t\t\t\t0x03c\n+#define QSERDES_V4_COM_POST_DIV_MUX\t\t\t0x040\n+#define QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN\t\t0x044\n+#define QSERDES_V4_COM_CLK_ENABLE1\t\t\t0x048\n+#define QSERDES_V4_COM_SYS_CLK_CTRL\t\t\t0x04c\n+#define QSERDES_V4_COM_SYSCLK_BUF_ENABLE\t\t0x050\n+#define QSERDES_V4_COM_PLL_EN\t\t\t\t0x054\n+#define QSERDES_V4_COM_PLL_IVCO\t\t\t\t0x058\n+#define QSERDES_V4_COM_CMN_IETRIM\t\t\t0x05c\n+#define QSERDES_V4_COM_CMN_IPTRIM\t\t\t0x060\n+#define QSERDES_V4_COM_EP_CLOCK_DETECT_CTRL\t\t0x064\n+#define QSERDES_V4_COM_SYSCLK_DET_COMP_STATUS\t\t0x068\n+#define QSERDES_V4_COM_CLK_EP_DIV_MODE0\t\t\t0x06c\n+#define QSERDES_V4_COM_CLK_EP_DIV_MODE1\t\t\t0x070\n+#define QSERDES_V4_COM_CP_CTRL_MODE0\t\t\t0x074\n+#define QSERDES_V4_COM_CP_CTRL_MODE1\t\t\t0x078\n+#define QSERDES_V4_COM_PLL_RCTRL_MODE0\t\t\t0x07c\n+#define QSERDES_V4_COM_PLL_RCTRL_MODE1\t\t\t0x080\n+#define QSERDES_V4_COM_PLL_CCTRL_MODE0\t\t\t0x084\n+#define QSERDES_V4_COM_PLL_CCTRL_MODE1\t\t\t0x088\n+#define QSERDES_V4_COM_PLL_CNTRL\t\t\t0x08c\n+#define QSERDES_V4_COM_BIAS_EN_CTRL_BY_PSM\t\t0x090\n+#define QSERDES_V4_COM_SYSCLK_EN_SEL\t\t\t0x094\n+#define QSERDES_V4_COM_CML_SYSCLK_SEL\t\t\t0x098\n+#define QSERDES_V4_COM_RESETSM_CNTRL\t\t\t0x09c\n+#define QSERDES_V4_COM_RESETSM_CNTRL2\t\t\t0x0a0\n+#define QSERDES_V4_COM_LOCK_CMP_EN\t\t\t0x0a4\n+#define QSERDES_V4_COM_LOCK_CMP_CFG\t\t\t0x0a8\n+#define QSERDES_V4_COM_LOCK_CMP1_MODE0\t\t\t0x0ac\n+#define QSERDES_V4_COM_LOCK_CMP2_MODE0\t\t\t0x0b0\n+#define QSERDES_V4_COM_LOCK_CMP1_MODE1\t\t\t0x0b4\n+#define QSERDES_V4_COM_LOCK_CMP2_MODE1\t\t\t0x0b8\n+#define QSERDES_V4_COM_DEC_START_MODE0\t\t\t0x0bc\n+#define QSERDES_V4_COM_DEC_START_MSB_MODE0\t\t0x0c0\n+#define QSERDES_V4_COM_DEC_START_MODE1\t\t\t0x0c4\n+#define QSERDES_V4_COM_DEC_START_MSB_MODE1\t\t0x0c8\n+#define QSERDES_V4_COM_DIV_FRAC_START1_MODE0\t\t0x0cc\n+#define QSERDES_V4_COM_DIV_FRAC_START2_MODE0\t\t0x0d0\n+#define QSERDES_V4_COM_DIV_FRAC_START3_MODE0\t\t0x0d4\n+#define QSERDES_V4_COM_DIV_FRAC_START1_MODE1\t\t0x0d8\n+#define QSERDES_V4_COM_DIV_FRAC_START2_MODE1\t\t0x0dc\n+#define QSERDES_V4_COM_DIV_FRAC_START3_MODE1\t\t0x0e0\n+#define QSERDES_V4_COM_INTEGLOOP_INITVAL\t\t0x0e4\n+#define QSERDES_V4_COM_INTEGLOOP_EN\t\t\t0x0e8\n+#define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0\t\t0x0ec\n+#define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0\t\t0x0f0\n+#define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1\t\t0x0f4\n+#define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1\t\t0x0f8\n+#define QSERDES_V4_COM_INTEGLOOP_P_PATH_GAIN0\t\t0x0fc\n+#define QSERDES_V4_COM_INTEGLOOP_P_PATH_GAIN1\t\t0x100\n+#define QSERDES_V4_COM_VCOCAL_DEADMAN_CTRL\t\t0x104\n+#define QSERDES_V4_COM_VCO_TUNE_CTRL\t\t\t0x108\n+#define QSERDES_V4_COM_VCO_TUNE_MAP\t\t\t0x10c\n+#define QSERDES_V4_COM_VCO_TUNE1_MODE0\t\t\t0x110\n+#define QSERDES_V4_COM_VCO_TUNE2_MODE0\t\t\t0x114\n+#define QSERDES_V4_COM_VCO_TUNE1_MODE1\t\t\t0x118\n+#define QSERDES_V4_COM_VCO_TUNE2_MODE1\t\t\t0x11c\n+#define QSERDES_V4_COM_VCO_TUNE_INITVAL1\t\t0x120\n+#define QSERDES_V4_COM_VCO_TUNE_INITVAL2\t\t0x124\n+#define QSERDES_V4_COM_VCO_TUNE_MINVAL1\t\t\t0x128\n+#define QSERDES_V4_COM_VCO_TUNE_MINVAL2\t\t\t0x12c\n+#define QSERDES_V4_COM_VCO_TUNE_MAXVAL1\t\t\t0x130\n+#define QSERDES_V4_COM_VCO_TUNE_MAXVAL2\t\t\t0x134\n+#define QSERDES_V4_COM_VCO_TUNE_TIMER1\t\t\t0x138\n+#define QSERDES_V4_COM_VCO_TUNE_TIMER2\t\t\t0x13c\n+#define QSERDES_V4_COM_CMN_STATUS\t\t\t0x140\n+#define QSERDES_V4_COM_RESET_SM_STATUS\t\t\t0x144\n+#define QSERDES_V4_COM_RESTRIM_CODE_STATUS\t\t0x148\n+#define QSERDES_V4_COM_PLLCAL_CODE1_STATUS\t\t0x14c\n+#define QSERDES_V4_COM_PLLCAL_CODE2_STATUS\t\t0x150\n+#define QSERDES_V4_COM_CLK_SELECT\t\t\t0x154\n+#define QSERDES_V4_COM_HSCLK_SEL\t\t\t0x158\n+#define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL\t\t0x15c\n+#define QSERDES_V4_COM_INTEGLOOP_BINCODE_STATUS\t\t0x160\n+#define QSERDES_V4_COM_PLL_ANALOG\t\t\t0x164\n+#define QSERDES_V4_COM_CORECLK_DIV_MODE0\t\t0x168\n+#define QSERDES_V4_COM_CORECLK_DIV_MODE1\t\t0x16c\n+#define QSERDES_V4_COM_SW_RESET\t\t\t\t0x170\n+#define QSERDES_V4_COM_CORE_CLK_EN\t\t\t0x174\n+#define QSERDES_V4_COM_C_READY_STATUS\t\t\t0x178\n+#define QSERDES_V4_COM_CMN_CONFIG\t\t\t0x17c\n+#define QSERDES_V4_COM_CMN_RATE_OVERRIDE\t\t0x180\n+#define QSERDES_V4_COM_SVS_MODE_CLK_SEL\t\t\t0x184\n+#define QSERDES_V4_COM_DEBUG_BUS0\t\t\t0x188\n+#define QSERDES_V4_COM_DEBUG_BUS1\t\t\t0x18c\n+#define QSERDES_V4_COM_DEBUG_BUS2\t\t\t0x190\n+#define QSERDES_V4_COM_DEBUG_BUS3\t\t\t0x194\n+#define QSERDES_V4_COM_DEBUG_BUS_SEL\t\t\t0x198\n+#define QSERDES_V4_COM_CMN_MISC1\t\t\t0x19c\n+#define QSERDES_V4_COM_CMN_MISC2\t\t\t0x1a0\n+#define QSERDES_V4_COM_CMN_MODE\t\t\t\t0x1a4\n+#define QSERDES_V4_COM_VCO_DC_LEVEL_CTRL\t\t0x1a8\n+#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0\t0x1ac\n+#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0\t0x1b0\n+#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1\t0x1b4\n+#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1\t0x1b8\n+#define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL\t\t0x1bc\n+\n+#endif\ndiff --git a/drivers/phy/qcom/phy-qcom-qmp-qserdes-com.h b/drivers/phy/qcom/phy-qcom-qmp-qserdes-com.h\nnew file mode 100644\nindex 0000000000..7fa5363fee\n--- /dev/null\n+++ b/drivers/phy/qcom/phy-qcom-qmp-qserdes-com.h\n@@ -0,0 +1,140 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.\n+ */\n+\n+#ifndef QCOM_PHY_QMP_QSERDES_COM_H_\n+#define QCOM_PHY_QMP_QSERDES_COM_H_\n+\n+/* Only for QMP V2 PHY - QSERDES COM registers */\n+#define QSERDES_COM_ATB_SEL1\t\t\t\t0x000\n+#define QSERDES_COM_ATB_SEL2\t\t\t\t0x004\n+#define QSERDES_COM_FREQ_UPDATE\t\t\t\t0x008\n+#define QSERDES_COM_BG_TIMER\t\t\t\t0x00c\n+#define QSERDES_COM_SSC_EN_CENTER\t\t\t0x010\n+#define QSERDES_COM_SSC_ADJ_PER1\t\t\t0x014\n+#define QSERDES_COM_SSC_ADJ_PER2\t\t\t0x018\n+#define QSERDES_COM_SSC_PER1\t\t\t\t0x01c\n+#define QSERDES_COM_SSC_PER2\t\t\t\t0x020\n+#define QSERDES_COM_SSC_STEP_SIZE1\t\t\t0x024\n+#define QSERDES_COM_SSC_STEP_SIZE2\t\t\t0x028\n+#define QSERDES_COM_POST_DIV\t\t\t\t0x02c\n+#define QSERDES_COM_POST_DIV_MUX\t\t\t0x030\n+#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN\t\t\t0x034\n+#define QSERDES_COM_CLK_ENABLE1\t\t\t\t0x038\n+#define QSERDES_COM_SYS_CLK_CTRL\t\t\t0x03c\n+#define QSERDES_COM_SYSCLK_BUF_ENABLE\t\t\t0x040\n+#define QSERDES_COM_PLL_EN\t\t\t\t0x044\n+#define QSERDES_COM_PLL_IVCO\t\t\t\t0x048\n+#define QSERDES_COM_LOCK_CMP1_MODE0\t\t\t0x04c\n+#define QSERDES_COM_LOCK_CMP2_MODE0\t\t\t0x050\n+#define QSERDES_COM_LOCK_CMP3_MODE0\t\t\t0x054\n+#define QSERDES_COM_LOCK_CMP1_MODE1\t\t\t0x058\n+#define QSERDES_COM_LOCK_CMP2_MODE1\t\t\t0x05c\n+#define QSERDES_COM_LOCK_CMP3_MODE1\t\t\t0x060\n+#define QSERDES_COM_LOCK_CMP1_MODE2\t\t\t0x064\n+#define QSERDES_COM_CMN_RSVD0\t\t\t\t0x064\n+#define QSERDES_COM_LOCK_CMP2_MODE2\t\t\t0x068\n+#define QSERDES_COM_EP_CLOCK_DETECT_CTRL\t\t0x068\n+#define QSERDES_COM_LOCK_CMP3_MODE2\t\t\t0x06c\n+#define QSERDES_COM_SYSCLK_DET_COMP_STATUS\t\t0x06c\n+#define QSERDES_COM_BG_TRIM\t\t\t\t0x070\n+#define QSERDES_COM_CLK_EP_DIV\t\t\t\t0x074\n+#define QSERDES_COM_CP_CTRL_MODE0\t\t\t0x078\n+#define QSERDES_COM_CP_CTRL_MODE1\t\t\t0x07c\n+#define QSERDES_COM_CP_CTRL_MODE2\t\t\t0x080\n+#define QSERDES_COM_CMN_RSVD1\t\t\t\t0x080\n+#define QSERDES_COM_PLL_RCTRL_MODE0\t\t\t0x084\n+#define QSERDES_COM_PLL_RCTRL_MODE1\t\t\t0x088\n+#define QSERDES_COM_PLL_RCTRL_MODE2\t\t\t0x08c\n+#define QSERDES_COM_CMN_RSVD2\t\t\t\t0x08c\n+#define QSERDES_COM_PLL_CCTRL_MODE0\t\t\t0x090\n+#define QSERDES_COM_PLL_CCTRL_MODE1\t\t\t0x094\n+#define QSERDES_COM_PLL_CCTRL_MODE2\t\t\t0x098\n+#define QSERDES_COM_CMN_RSVD3\t\t\t\t0x098\n+#define QSERDES_COM_PLL_CNTRL\t\t\t\t0x09c\n+#define QSERDES_COM_PHASE_SEL_CTRL\t\t\t0x0a0\n+#define QSERDES_COM_PHASE_SEL_DC\t\t\t0x0a4\n+#define QSERDES_COM_CORE_CLK_IN_SYNC_SEL\t\t0x0a8\n+#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM\t\t\t0x0a8\n+#define QSERDES_COM_SYSCLK_EN_SEL\t\t\t0x0ac\n+#define QSERDES_COM_CML_SYSCLK_SEL\t\t\t0x0b0\n+#define QSERDES_COM_RESETSM_CNTRL\t\t\t0x0b4\n+#define QSERDES_COM_RESETSM_CNTRL2\t\t\t0x0b8\n+#define QSERDES_COM_RESTRIM_CTRL\t\t\t0x0bc\n+#define QSERDES_COM_RESTRIM_CTRL2\t\t\t0x0c0\n+#define QSERDES_COM_RESCODE_DIV_NUM\t\t\t0x0c4\n+#define QSERDES_COM_LOCK_CMP_EN\t\t\t\t0x0c8\n+#define QSERDES_COM_LOCK_CMP_CFG\t\t\t0x0cc\n+#define QSERDES_COM_DEC_START_MODE0\t\t\t0x0d0\n+#define QSERDES_COM_DEC_START_MODE1\t\t\t0x0d4\n+#define QSERDES_COM_DEC_START_MODE2\t\t\t0x0d8\n+#define QSERDES_COM_VCOCAL_DEADMAN_CTRL\t\t\t0x0d8\n+#define QSERDES_COM_DIV_FRAC_START1_MODE0\t\t0x0dc\n+#define QSERDES_COM_DIV_FRAC_START2_MODE0\t\t0x0e0\n+#define QSERDES_COM_DIV_FRAC_START3_MODE0\t\t0x0e4\n+#define QSERDES_COM_DIV_FRAC_START1_MODE1\t\t0x0e8\n+#define QSERDES_COM_DIV_FRAC_START2_MODE1\t\t0x0ec\n+#define QSERDES_COM_DIV_FRAC_START3_MODE1\t\t0x0f0\n+#define QSERDES_COM_DIV_FRAC_START1_MODE2\t\t0x0f4\n+#define QSERDES_COM_VCO_TUNE_MINVAL1\t\t\t0x0f4\n+#define QSERDES_COM_DIV_FRAC_START2_MODE2\t\t0x0f8\n+#define QSERDES_COM_VCO_TUNE_MINVAL2\t\t\t0x0f8\n+#define QSERDES_COM_DIV_FRAC_START3_MODE2\t\t0x0fc\n+#define QSERDES_COM_CMN_RSVD4\t\t\t\t0x0fc\n+#define QSERDES_COM_INTEGLOOP_INITVAL\t\t\t0x100\n+#define QSERDES_COM_INTEGLOOP_EN\t\t\t0x104\n+#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0\t\t0x108\n+#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0\t\t0x10c\n+#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1\t\t0x110\n+#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1\t\t0x114\n+#define QSERDES_COM_INTEGLOOP_GAIN0_MODE2\t\t0x118\n+#define QSERDES_COM_VCO_TUNE_MAXVAL1\t\t\t0x118\n+#define QSERDES_COM_INTEGLOOP_GAIN1_MODE2\t\t0x11c\n+#define QSERDES_COM_VCO_TUNE_MAXVAL2\t\t\t0x11c\n+#define QSERDES_COM_RES_TRIM_CONTROL2\t\t\t0x120\n+#define QSERDES_COM_VCO_TUNE_CTRL\t\t\t0x124\n+#define QSERDES_COM_VCO_TUNE_MAP\t\t\t0x128\n+#define QSERDES_COM_VCO_TUNE1_MODE0\t\t\t0x12c\n+#define QSERDES_COM_VCO_TUNE2_MODE0\t\t\t0x130\n+#define QSERDES_COM_VCO_TUNE1_MODE1\t\t\t0x134\n+#define QSERDES_COM_VCO_TUNE2_MODE1\t\t\t0x138\n+#define QSERDES_COM_VCO_TUNE1_MODE2\t\t\t0x13c\n+#define QSERDES_COM_VCO_TUNE_INITVAL1\t\t\t0x13c\n+#define QSERDES_COM_VCO_TUNE2_MODE2\t\t\t0x140\n+#define QSERDES_COM_VCO_TUNE_INITVAL2\t\t\t0x140\n+#define QSERDES_COM_VCO_TUNE_TIMER1\t\t\t0x144\n+#define QSERDES_COM_VCO_TUNE_TIMER2\t\t\t0x148\n+#define QSERDES_COM_SAR\t\t\t\t\t0x14c\n+#define QSERDES_COM_SAR_CLK\t\t\t\t0x150\n+#define QSERDES_COM_SAR_CODE_OUT_STATUS\t\t\t0x154\n+#define QSERDES_COM_SAR_CODE_READY_STATUS\t\t0x158\n+#define QSERDES_COM_CMN_STATUS\t\t\t\t0x15c\n+#define QSERDES_COM_RESET_SM_STATUS\t\t\t0x160\n+#define QSERDES_COM_RESTRIM_CODE_STATUS\t\t\t0x164\n+#define QSERDES_COM_PLLCAL_CODE1_STATUS\t\t\t0x168\n+#define QSERDES_COM_PLLCAL_CODE2_STATUS\t\t\t0x16c\n+#define QSERDES_COM_BG_CTRL\t\t\t\t0x170\n+#define QSERDES_COM_CLK_SELECT\t\t\t\t0x174\n+#define QSERDES_COM_HSCLK_SEL\t\t\t\t0x178\n+#define QSERDES_COM_INTEGLOOP_BINCODE_STATUS\t\t0x17c\n+#define QSERDES_COM_PLL_ANALOG\t\t\t\t0x180\n+#define QSERDES_COM_CORECLK_DIV\t\t\t\t0x184\n+#define QSERDES_COM_SW_RESET\t\t\t\t0x188\n+#define QSERDES_COM_CORE_CLK_EN\t\t\t\t0x18c\n+#define QSERDES_COM_C_READY_STATUS\t\t\t0x190\n+#define QSERDES_COM_CMN_CONFIG\t\t\t\t0x194\n+#define QSERDES_COM_CMN_RATE_OVERRIDE\t\t\t0x198\n+#define QSERDES_COM_SVS_MODE_CLK_SEL\t\t\t0x19c\n+#define QSERDES_COM_DEBUG_BUS0\t\t\t\t0x1a0\n+#define QSERDES_COM_DEBUG_BUS1\t\t\t\t0x1a4\n+#define QSERDES_COM_DEBUG_BUS2\t\t\t\t0x1a8\n+#define QSERDES_COM_DEBUG_BUS3\t\t\t\t0x1ac\n+#define QSERDES_COM_DEBUG_BUS_SEL\t\t\t0x1b0\n+#define QSERDES_COM_CMN_MISC1\t\t\t\t0x1b4\n+#define QSERDES_COM_CMN_MISC2\t\t\t\t0x1b8\n+#define QSERDES_COM_CORECLK_DIV_MODE1\t\t\t0x1bc\n+#define QSERDES_COM_CORECLK_DIV_MODE2\t\t\t0x1c0\n+#define QSERDES_COM_CMN_RSVD5\t\t\t\t0x1c4\n+\n+#endif\ndiff --git a/drivers/phy/qcom/phy-qcom-qmp-qserdes-pll.h b/drivers/phy/qcom/phy-qcom-qmp-qserdes-pll.h\nnew file mode 100644\nindex 0000000000..ad326e301a\n--- /dev/null\n+++ b/drivers/phy/qcom/phy-qcom-qmp-qserdes-pll.h\n@@ -0,0 +1,66 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.\n+ */\n+\n+#ifndef QCOM_PHY_QMP_QSERDES_PLL_H_\n+#define QCOM_PHY_QMP_QSERDES_PLL_H_\n+\n+/* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */\n+#define QSERDES_PLL_BG_TIMER\t\t\t\t0x00c\n+#define QSERDES_PLL_SSC_PER1\t\t\t\t0x01c\n+#define QSERDES_PLL_SSC_PER2\t\t\t\t0x020\n+#define QSERDES_PLL_SSC_STEP_SIZE1_MODE0\t\t0x024\n+#define QSERDES_PLL_SSC_STEP_SIZE2_MODE0\t\t0x028\n+#define QSERDES_PLL_SSC_STEP_SIZE1_MODE1\t\t0x02c\n+#define QSERDES_PLL_SSC_STEP_SIZE2_MODE1\t\t0x030\n+#define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN\t\t\t0x03c\n+#define QSERDES_PLL_CLK_ENABLE1\t\t\t\t0x040\n+#define QSERDES_PLL_SYS_CLK_CTRL\t\t\t0x044\n+#define QSERDES_PLL_SYSCLK_BUF_ENABLE\t\t\t0x048\n+#define QSERDES_PLL_PLL_IVCO\t\t\t\t0x050\n+#define QSERDES_PLL_LOCK_CMP1_MODE0\t\t\t0x054\n+#define QSERDES_PLL_LOCK_CMP2_MODE0\t\t\t0x058\n+#define QSERDES_PLL_LOCK_CMP1_MODE1\t\t\t0x060\n+#define QSERDES_PLL_LOCK_CMP2_MODE1\t\t\t0x064\n+#define QSERDES_PLL_BG_TRIM\t\t\t\t0x074\n+#define QSERDES_PLL_CLK_EP_DIV_MODE0\t\t\t0x078\n+#define QSERDES_PLL_CLK_EP_DIV_MODE1\t\t\t0x07c\n+#define QSERDES_PLL_CP_CTRL_MODE0\t\t\t0x080\n+#define QSERDES_PLL_CP_CTRL_MODE1\t\t\t0x084\n+#define QSERDES_PLL_PLL_RCTRL_MODE0\t\t\t0x088\n+#define QSERDES_PLL_PLL_RCTRL_MODE1\t\t\t0x08c\n+#define QSERDES_PLL_PLL_CCTRL_MODE0\t\t\t0x090\n+#define QSERDES_PLL_PLL_CCTRL_MODE1\t\t\t0x094\n+#define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM\t\t\t0x0a4\n+#define QSERDES_PLL_SYSCLK_EN_SEL\t\t\t0x0a8\n+#define QSERDES_PLL_RESETSM_CNTRL\t\t\t0x0b0\n+#define QSERDES_PLL_LOCK_CMP_EN\t\t\t\t0x0c4\n+#define QSERDES_PLL_DEC_START_MODE0\t\t\t0x0cc\n+#define QSERDES_PLL_DEC_START_MODE1\t\t\t0x0d0\n+#define QSERDES_PLL_DIV_FRAC_START1_MODE0\t\t0x0d8\n+#define QSERDES_PLL_DIV_FRAC_START2_MODE0\t\t0x0dc\n+#define QSERDES_PLL_DIV_FRAC_START3_MODE0\t\t0x0e0\n+#define QSERDES_PLL_DIV_FRAC_START1_MODE1\t\t0x0e4\n+#define QSERDES_PLL_DIV_FRAC_START2_MODE1\t\t0x0e8\n+#define QSERDES_PLL_DIV_FRAC_START3_MODE1\t\t0x0ec\n+#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0\t\t0x100\n+#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0\t\t0x104\n+#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1\t\t0x108\n+#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1\t\t0x10c\n+#define QSERDES_PLL_VCO_TUNE_MAP\t\t\t0x120\n+#define QSERDES_PLL_VCO_TUNE1_MODE0\t\t\t0x124\n+#define QSERDES_PLL_VCO_TUNE2_MODE0\t\t\t0x128\n+#define QSERDES_PLL_VCO_TUNE1_MODE1\t\t\t0x12c\n+#define QSERDES_PLL_VCO_TUNE2_MODE1\t\t\t0x130\n+#define QSERDES_PLL_VCO_TUNE_TIMER1\t\t\t0x13c\n+#define QSERDES_PLL_VCO_TUNE_TIMER2\t\t\t0x140\n+#define QSERDES_PLL_CLK_SELECT\t\t\t\t0x16c\n+#define QSERDES_PLL_HSCLK_SEL\t\t\t\t0x170\n+#define QSERDES_PLL_CORECLK_DIV\t\t\t\t0x17c\n+#define QSERDES_PLL_CORE_CLK_EN\t\t\t\t0x184\n+#define QSERDES_PLL_CMN_CONFIG\t\t\t\t0x18c\n+#define QSERDES_PLL_SVS_MODE_CLK_SEL\t\t\t0x194\n+#define QSERDES_PLL_CORECLK_DIV_MODE1\t\t\t0x1b4\n+\n+#endif\ndiff --git a/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-ufs-v6.h\nnew file mode 100644\nindex 0000000000..15bcb4ba91\n--- /dev/null\n+++ b/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-ufs-v6.h\n@@ -0,0 +1,30 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) 2023, Linaro Limited\n+ */\n+\n+#ifndef QCOM_PHY_QMP_QSERDES_TXRX_UFS_V6_H_\n+#define QCOM_PHY_QMP_QSERDES_TXRX_UFS_V6_H_\n+\n+#define QSERDES_UFS_V6_TX_RES_CODE_LANE_TX\t\t\t0x28\n+#define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX\t\t\t0x2c\n+#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX\t\t0x30\n+#define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX\t\t0x34\n+\n+#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2\t\t0x08\n+#define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4\t\t0x10\n+#define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL\t\t\t0x178\n+#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0\t\t\t0x208\n+#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1\t\t\t0x20c\n+#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B3\t\t\t0x214\n+#define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B6\t\t\t0x220\n+#define QSERDES_UFS_V6_RX_MODE_RATE2_B3\t\t\t\t0x238\n+#define QSERDES_UFS_V6_RX_MODE_RATE2_B6\t\t\t\t0x244\n+#define QSERDES_UFS_V6_RX_MODE_RATE3_B3\t\t\t\t0x25c\n+#define QSERDES_UFS_V6_RX_MODE_RATE3_B4\t\t\t\t0x260\n+#define QSERDES_UFS_V6_RX_MODE_RATE3_B5\t\t\t\t0x264\n+#define QSERDES_UFS_V6_RX_MODE_RATE3_B8\t\t\t\t0x270\n+#define QSERDES_UFS_V6_RX_MODE_RATE4_B3\t\t\t\t0x280\n+#define QSERDES_UFS_V6_RX_MODE_RATE4_B6\t\t\t\t0x28c\n+\n+#endif\ndiff --git a/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v3.h b/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v3.h\nnew file mode 100644\nindex 0000000000..161e6df30e\n--- /dev/null\n+++ b/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v3.h\n@@ -0,0 +1,68 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.\n+ */\n+\n+#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V3_H_\n+#define QCOM_PHY_QMP_QSERDES_TXRX_V3_H_\n+\n+/* Only for QMP V3 PHY - TX registers */\n+#define QSERDES_V3_TX_BIST_MODE_LANENO\t\t\t0x000\n+#define QSERDES_V3_TX_CLKBUF_ENABLE\t\t\t0x008\n+#define QSERDES_V3_TX_TX_EMP_POST1_LVL\t\t\t0x00c\n+#define QSERDES_V3_TX_TX_DRV_LVL\t\t\t0x01c\n+#define QSERDES_V3_TX_RESET_TSYNC_EN\t\t\t0x024\n+#define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN\t\t0x028\n+#define QSERDES_V3_TX_TX_BAND\t\t\t\t0x02c\n+#define QSERDES_V3_TX_SLEW_CNTL\t\t\t\t0x030\n+#define QSERDES_V3_TX_INTERFACE_SELECT\t\t\t0x034\n+#define QSERDES_V3_TX_RES_CODE_LANE_TX\t\t\t0x03c\n+#define QSERDES_V3_TX_RES_CODE_LANE_RX\t\t\t0x040\n+#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX\t\t0x044\n+#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX\t\t0x048\n+#define QSERDES_V3_TX_DEBUG_BUS_SEL\t\t\t0x058\n+#define QSERDES_V3_TX_TRANSCEIVER_BIAS_EN\t\t0x05c\n+#define QSERDES_V3_TX_HIGHZ_DRVR_EN\t\t\t0x060\n+#define QSERDES_V3_TX_TX_POL_INV\t\t\t0x064\n+#define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN\t0x068\n+#define QSERDES_V3_TX_LANE_MODE_1\t\t\t0x08c\n+#define QSERDES_V3_TX_LANE_MODE_2\t\t\t0x090\n+#define QSERDES_V3_TX_LANE_MODE_3\t\t\t0x094\n+#define QSERDES_V3_TX_RCV_DETECT_LVL_2\t\t\t0x0a4\n+#define QSERDES_V3_TX_TRAN_DRVR_EMP_EN\t\t\t0x0c0\n+#define QSERDES_V3_TX_TX_INTERFACE_MODE\t\t\t0x0c4\n+#define QSERDES_V3_TX_VMODE_CTRL1\t\t\t0x0f0\n+\n+/* Only for QMP V3 PHY - RX registers */\n+#define QSERDES_V3_RX_UCDR_FO_GAIN\t\t\t0x008\n+#define QSERDES_V3_RX_UCDR_SO_GAIN_HALF\t\t\t0x00c\n+#define QSERDES_V3_RX_UCDR_SO_GAIN\t\t\t0x014\n+#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF\t\t0x024\n+#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER\t\t0x028\n+#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN\t\t\t0x02c\n+#define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN\t\t0x030\n+#define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE\t0x034\n+#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW\t\t0x03c\n+#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH\t\t0x040\n+#define QSERDES_V3_RX_UCDR_PI_CONTROLS\t\t\t0x044\n+#define QSERDES_V3_RX_RX_TERM_BW\t\t\t0x07c\n+#define QSERDES_V3_RX_VGA_CAL_CNTRL1\t\t\t0x0bc\n+#define QSERDES_V3_RX_VGA_CAL_CNTRL2\t\t\t0x0c0\n+#define QSERDES_V3_RX_RX_EQ_GAIN2_LSB\t\t\t0x0c8\n+#define QSERDES_V3_RX_RX_EQ_GAIN2_MSB\t\t\t0x0cc\n+#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL1\t\t0x0d0\n+#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2\t\t0x0d4\n+#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3\t\t0x0d8\n+#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4\t\t0x0dc\n+#define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1\t0x0f8\n+#define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2\t\t0x0fc\n+#define QSERDES_V3_RX_SIGDET_ENABLES\t\t\t0x100\n+#define QSERDES_V3_RX_SIGDET_CNTRL\t\t\t0x104\n+#define QSERDES_V3_RX_SIGDET_LVL\t\t\t0x108\n+#define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL\t\t0x10c\n+#define QSERDES_V3_RX_RX_BAND\t\t\t\t0x110\n+#define QSERDES_V3_RX_RX_INTERFACE_MODE\t\t\t0x11c\n+#define QSERDES_V3_RX_RX_MODE_00\t\t\t0x164\n+#define QSERDES_V3_RX_RX_MODE_01\t\t\t0x168\n+\n+#endif\ndiff --git a/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v4.h b/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v4.h\nnew file mode 100644\nindex 0000000000..6ee3bec9ac\n--- /dev/null\n+++ b/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx-v4.h\n@@ -0,0 +1,233 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.\n+ */\n+\n+#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V4_H_\n+#define QCOM_PHY_QMP_QSERDES_TXRX_V4_H_\n+\n+/* Only for QMP V4 PHY - TX registers */\n+#define QSERDES_V4_TX_BIST_MODE_LANENO\t\t\t0x000\n+#define QSERDES_V4_TX_BIST_INVERT\t\t\t0x004\n+#define QSERDES_V4_TX_CLKBUF_ENABLE\t\t\t0x008\n+#define QSERDES_V4_TX_TX_EMP_POST1_LVL\t\t\t0x00c\n+#define QSERDES_V4_TX_TX_IDLE_LVL_LARGE_AMP\t\t0x010\n+#define QSERDES_V4_TX_TX_DRV_LVL\t\t\t0x014\n+#define QSERDES_V4_TX_TX_DRV_LVL_OFFSET\t\t\t0x018\n+#define QSERDES_V4_TX_RESET_TSYNC_EN\t\t\t0x01c\n+#define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN\t\t0x020\n+#define QSERDES_V4_TX_TX_BAND\t\t\t\t0x024\n+#define QSERDES_V4_TX_SLEW_CNTL\t\t\t\t0x028\n+#define QSERDES_V4_TX_INTERFACE_SELECT\t\t\t0x02c\n+#define QSERDES_V4_TX_LPB_EN\t\t\t\t0x030\n+#define QSERDES_V4_TX_RES_CODE_LANE_TX\t\t\t0x034\n+#define QSERDES_V4_TX_RES_CODE_LANE_RX\t\t\t0x038\n+#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX\t\t0x03c\n+#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX\t\t0x040\n+#define QSERDES_V4_TX_PERL_LENGTH1\t\t\t0x044\n+#define QSERDES_V4_TX_PERL_LENGTH2\t\t\t0x048\n+#define QSERDES_V4_TX_SERDES_BYP_EN_OUT\t\t\t0x04c\n+#define QSERDES_V4_TX_DEBUG_BUS_SEL\t\t\t0x050\n+#define QSERDES_V4_TX_TRANSCEIVER_BIAS_EN\t\t0x054\n+#define QSERDES_V4_TX_HIGHZ_DRVR_EN\t\t\t0x058\n+#define QSERDES_V4_TX_TX_POL_INV\t\t\t0x05c\n+#define QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN\t0x060\n+#define QSERDES_V4_TX_BIST_PATTERN1\t\t\t0x064\n+#define QSERDES_V4_TX_BIST_PATTERN2\t\t\t0x068\n+#define QSERDES_V4_TX_BIST_PATTERN3\t\t\t0x06c\n+#define QSERDES_V4_TX_BIST_PATTERN4\t\t\t0x070\n+#define QSERDES_V4_TX_BIST_PATTERN5\t\t\t0x074\n+#define QSERDES_V4_TX_BIST_PATTERN6\t\t\t0x078\n+#define QSERDES_V4_TX_BIST_PATTERN7\t\t\t0x07c\n+#define QSERDES_V4_TX_BIST_PATTERN8\t\t\t0x080\n+#define QSERDES_V4_TX_LANE_MODE_1\t\t\t0x084\n+#define QSERDES_V4_TX_LANE_MODE_2\t\t\t0x088\n+#define QSERDES_V4_TX_LANE_MODE_3\t\t\t0x08c\n+#define QSERDES_V4_TX_ATB_SEL1\t\t\t\t0x090\n+#define QSERDES_V4_TX_ATB_SEL2\t\t\t\t0x094\n+#define QSERDES_V4_TX_RCV_DETECT_LVL\t\t\t0x098\n+#define QSERDES_V4_TX_RCV_DETECT_LVL_2\t\t\t0x09c\n+#define QSERDES_V4_TX_PRBS_SEED1\t\t\t0x0a0\n+#define QSERDES_V4_TX_PRBS_SEED2\t\t\t0x0a4\n+#define QSERDES_V4_TX_PRBS_SEED3\t\t\t0x0a8\n+#define QSERDES_V4_TX_PRBS_SEED4\t\t\t0x0ac\n+#define QSERDES_V4_TX_RESET_GEN\t\t\t\t0x0b0\n+#define QSERDES_V4_TX_RESET_GEN_MUXES\t\t\t0x0b4\n+#define QSERDES_V4_TX_TRAN_DRVR_EMP_EN\t\t\t0x0b8\n+#define QSERDES_V4_TX_TX_INTERFACE_MODE\t\t\t0x0bc\n+#define QSERDES_V4_TX_PWM_CTRL\t\t\t\t0x0c0\n+#define QSERDES_V4_TX_PWM_ENCODED_OR_DATA\t\t0x0c4\n+#define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND2\t\t0x0c8\n+#define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND2\t\t0x0cc\n+#define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND2\t\t0x0d0\n+#define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND2\t\t0x0d4\n+#define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1\t0x0d8\n+#define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1\t0x0dc\n+#define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1\t0x0e0\n+#define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1\t0x0e4\n+#define QSERDES_V4_TX_VMODE_CTRL1\t\t\t0x0e8\n+#define QSERDES_V4_TX_ALOG_OBSV_BUS_CTRL_1\t\t0x0ec\n+#define QSERDES_V4_TX_BIST_STATUS\t\t\t0x0f0\n+#define QSERDES_V4_TX_BIST_ERROR_COUNT1\t\t\t0x0f4\n+#define QSERDES_V4_TX_BIST_ERROR_COUNT2\t\t\t0x0f8\n+#define QSERDES_V4_TX_ALOG_OBSV_BUS_STATUS_1\t\t0x0fc\n+#define QSERDES_V4_TX_LANE_DIG_CONFIG\t\t\t0x100\n+#define QSERDES_V4_TX_PI_QEC_CTRL\t\t\t0x104\n+#define QSERDES_V4_TX_PRE_EMPH\t\t\t\t0x108\n+#define QSERDES_V4_TX_SW_RESET\t\t\t\t0x10c\n+#define QSERDES_V4_TX_DCC_OFFSET\t\t\t0x110\n+#define QSERDES_V4_TX_DIG_BKUP_CTRL\t\t\t0x114\n+#define QSERDES_V4_TX_DEBUG_BUS0\t\t\t0x118\n+#define QSERDES_V4_TX_DEBUG_BUS1\t\t\t0x11c\n+#define QSERDES_V4_TX_DEBUG_BUS2\t\t\t0x120\n+#define QSERDES_V4_TX_DEBUG_BUS3\t\t\t0x124\n+#define QSERDES_V4_TX_READ_EQCODE\t\t\t0x128\n+#define QSERDES_V4_TX_READ_OFFSETCODE\t\t\t0x12c\n+#define QSERDES_V4_TX_IA_ERROR_COUNTER_LOW\t\t0x130\n+#define QSERDES_V4_TX_IA_ERROR_COUNTER_HIGH\t\t0x134\n+#define QSERDES_V4_TX_VGA_READ_CODE\t\t\t0x138\n+#define QSERDES_V4_TX_VTH_READ_CODE\t\t\t0x13c\n+#define QSERDES_V4_TX_DFE_TAP1_READ_CODE\t\t0x140\n+#define QSERDES_V4_TX_DFE_TAP2_READ_CODE\t\t0x144\n+#define QSERDES_V4_TX_IDAC_STATUS_I\t\t\t0x148\n+#define QSERDES_V4_TX_IDAC_STATUS_IBAR\t\t\t0x14c\n+#define QSERDES_V4_TX_IDAC_STATUS_Q\t\t\t0x150\n+#define QSERDES_V4_TX_IDAC_STATUS_QBAR\t\t\t0x154\n+#define QSERDES_V4_TX_IDAC_STATUS_A\t\t\t0x158\n+#define QSERDES_V4_TX_IDAC_STATUS_ABAR\t\t\t0x15c\n+#define QSERDES_V4_TX_IDAC_STATUS_SM_ON\t\t\t0x160\n+#define QSERDES_V4_TX_IDAC_STATUS_CAL_DONE\t\t0x164\n+#define QSERDES_V4_TX_IDAC_STATUS_SIGNERROR\t\t0x168\n+#define QSERDES_V4_TX_DCC_CAL_STATUS\t\t\t0x16c\n+\n+/* Only for QMP V4 PHY - RX registers */\n+#define QSERDES_V4_RX_UCDR_FO_GAIN_HALF\t\t\t0x000\n+#define QSERDES_V4_RX_UCDR_FO_GAIN_QUARTER\t\t0x004\n+#define QSERDES_V4_RX_UCDR_FO_GAIN\t\t\t0x008\n+#define QSERDES_V4_RX_UCDR_SO_GAIN_HALF\t\t\t0x00c\n+#define QSERDES_V4_RX_UCDR_SO_GAIN_QUARTER\t\t0x010\n+#define QSERDES_V4_RX_UCDR_SO_GAIN\t\t\t0x014\n+#define QSERDES_V4_RX_UCDR_SVS_FO_GAIN_HALF\t\t0x018\n+#define QSERDES_V4_RX_UCDR_SVS_FO_GAIN_QUARTER\t\t0x01c\n+#define QSERDES_V4_RX_UCDR_SVS_FO_GAIN\t\t\t0x020\n+#define QSERDES_V4_RX_UCDR_SVS_SO_GAIN_HALF\t\t0x024\n+#define QSERDES_V4_RX_UCDR_SVS_SO_GAIN_QUARTER\t\t0x028\n+#define QSERDES_V4_RX_UCDR_SVS_SO_GAIN\t\t\t0x02c\n+#define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN\t\t0x030\n+#define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE\t0x034\n+#define QSERDES_V4_RX_UCDR_FO_TO_SO_DELAY\t\t0x038\n+#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW\t\t0x03c\n+#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH\t\t0x040\n+#define QSERDES_V4_RX_UCDR_PI_CONTROLS\t\t\t0x044\n+#define QSERDES_V4_RX_UCDR_PI_CTRL2\t\t\t0x048\n+#define QSERDES_V4_RX_UCDR_SB2_THRESH1\t\t\t0x04c\n+#define QSERDES_V4_RX_UCDR_SB2_THRESH2\t\t\t0x050\n+#define QSERDES_V4_RX_UCDR_SB2_GAIN1\t\t\t0x054\n+#define QSERDES_V4_RX_UCDR_SB2_GAIN2\t\t\t0x058\n+#define QSERDES_V4_RX_AUX_CONTROL\t\t\t0x05c\n+#define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE\t\t0x060\n+#define QSERDES_V4_RX_RCLK_AUXDATA_SEL\t\t\t0x064\n+#define QSERDES_V4_RX_AC_JTAG_ENABLE\t\t\t0x068\n+#define QSERDES_V4_RX_AC_JTAG_INITP\t\t\t0x06c\n+#define QSERDES_V4_RX_AC_JTAG_INITN\t\t\t0x070\n+#define QSERDES_V4_RX_AC_JTAG_LVL\t\t\t0x074\n+#define QSERDES_V4_RX_AC_JTAG_MODE\t\t\t0x078\n+#define QSERDES_V4_RX_AC_JTAG_RESET\t\t\t0x07c\n+#define QSERDES_V4_RX_RX_TERM_BW\t\t\t0x080\n+#define QSERDES_V4_RX_RX_RCVR_IQ_EN\t\t\t0x084\n+#define QSERDES_V4_RX_RX_IDAC_I_DC_OFFSETS\t\t0x088\n+#define QSERDES_V4_RX_RX_IDAC_IBAR_DC_OFFSETS\t\t0x08c\n+#define QSERDES_V4_RX_RX_IDAC_Q_DC_OFFSETS\t\t0x090\n+#define QSERDES_V4_RX_RX_IDAC_QBAR_DC_OFFSETS\t\t0x094\n+#define QSERDES_V4_RX_RX_IDAC_A_DC_OFFSETS\t\t0x098\n+#define QSERDES_V4_RX_RX_IDAC_ABAR_DC_OFFSETS\t\t0x09c\n+#define QSERDES_V4_RX_RX_IDAC_EN\t\t\t0x0a0\n+#define QSERDES_V4_RX_RX_IDAC_ENABLES\t\t\t0x0a4\n+#define QSERDES_V4_RX_RX_IDAC_SIGN\t\t\t0x0a8\n+#define QSERDES_V4_RX_RX_HIGHZ_HIGHRATE\t\t\t0x0ac\n+#define QSERDES_V4_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x0b0\n+#define QSERDES_V4_RX_DFE_1\t\t\t\t0x0b4\n+#define QSERDES_V4_RX_DFE_2\t\t\t\t0x0b8\n+#define QSERDES_V4_RX_DFE_3\t\t\t\t0x0bc\n+#define QSERDES_V4_RX_DFE_4\t\t\t\t0x0c0\n+#define QSERDES_V4_RX_TX_ADAPT_PRE_THRESH1\t\t0x0c4\n+#define QSERDES_V4_RX_TX_ADAPT_PRE_THRESH2\t\t0x0c8\n+#define QSERDES_V4_RX_TX_ADAPT_POST_THRESH\t\t0x0cc\n+#define QSERDES_V4_RX_TX_ADAPT_MAIN_THRESH\t\t0x0d0\n+#define QSERDES_V4_RX_VGA_CAL_CNTRL1\t\t\t0x0d4\n+#define QSERDES_V4_RX_VGA_CAL_CNTRL2\t\t\t0x0d8\n+#define QSERDES_V4_RX_GM_CAL\t\t\t\t0x0dc\n+#define QSERDES_V4_RX_RX_VGA_GAIN2_LSB\t\t\t0x0e0\n+#define QSERDES_V4_RX_RX_VGA_GAIN2_MSB\t\t\t0x0e4\n+#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1\t\t0x0e8\n+#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2\t\t0x0ec\n+#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3\t\t0x0f0\n+#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4\t\t0x0f4\n+#define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW\t\t0x0f8\n+#define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH\t\t0x0fc\n+#define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME\t\t0x100\n+#define QSERDES_V4_RX_RX_IDAC_ACCUMULATOR\t\t0x104\n+#define QSERDES_V4_RX_RX_EQ_OFFSET_LSB\t\t\t0x108\n+#define QSERDES_V4_RX_RX_EQ_OFFSET_MSB\t\t\t0x10c\n+#define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1\t0x110\n+#define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2\t\t0x114\n+#define QSERDES_V4_RX_SIGDET_ENABLES\t\t\t0x118\n+#define QSERDES_V4_RX_SIGDET_CNTRL\t\t\t0x11c\n+#define QSERDES_V4_RX_SIGDET_LVL\t\t\t0x120\n+#define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL\t\t0x124\n+#define QSERDES_V4_RX_RX_BAND\t\t\t\t0x128\n+#define QSERDES_V4_RX_CDR_FREEZE_UP_DN\t\t\t0x12c\n+#define QSERDES_V4_RX_CDR_RESET_OVERRIDE\t\t0x130\n+#define QSERDES_V4_RX_RX_INTERFACE_MODE\t\t\t0x134\n+#define QSERDES_V4_RX_JITTER_GEN_MODE\t\t\t0x138\n+#define QSERDES_V4_RX_SJ_AMP1\t\t\t\t0x13c\n+#define QSERDES_V4_RX_SJ_AMP2\t\t\t\t0x140\n+#define QSERDES_V4_RX_SJ_PER1\t\t\t\t0x144\n+#define QSERDES_V4_RX_SJ_PER2\t\t\t\t0x148\n+#define QSERDES_V4_RX_PPM_OFFSET1\t\t\t0x14c\n+#define QSERDES_V4_RX_PPM_OFFSET2\t\t\t0x150\n+#define QSERDES_V4_RX_SIGN_PPM_PERIOD1\t\t\t0x154\n+#define QSERDES_V4_RX_SIGN_PPM_PERIOD2\t\t\t0x158\n+#define QSERDES_V4_RX_RX_PWM_ENABLE_AND_DATA\t\t0x15c\n+#define QSERDES_V4_RX_RX_PWM_GEAR1_TIMEOUT_COUNT\t0x160\n+#define QSERDES_V4_RX_RX_PWM_GEAR2_TIMEOUT_COUNT\t0x164\n+#define QSERDES_V4_RX_RX_PWM_GEAR3_TIMEOUT_COUNT\t0x168\n+#define QSERDES_V4_RX_RX_PWM_GEAR4_TIMEOUT_COUNT\t0x16c\n+#define QSERDES_V4_RX_RX_MODE_00_LOW\t\t\t0x170\n+#define QSERDES_V4_RX_RX_MODE_00_HIGH\t\t\t0x174\n+#define QSERDES_V4_RX_RX_MODE_00_HIGH2\t\t\t0x178\n+#define QSERDES_V4_RX_RX_MODE_00_HIGH3\t\t\t0x17c\n+#define QSERDES_V4_RX_RX_MODE_00_HIGH4\t\t\t0x180\n+#define QSERDES_V4_RX_RX_MODE_01_LOW\t\t\t0x184\n+#define QSERDES_V4_RX_RX_MODE_01_HIGH\t\t\t0x188\n+#define QSERDES_V4_RX_RX_MODE_01_HIGH2\t\t\t0x18c\n+#define QSERDES_V4_RX_RX_MODE_01_HIGH3\t\t\t0x190\n+#define QSERDES_V4_RX_RX_MODE_01_HIGH4\t\t\t0x194\n+#define QSERDES_V4_RX_RX_MODE_10_LOW\t\t\t0x198\n+#define QSERDES_V4_RX_RX_MODE_10_HIGH\t\t\t0x19c\n+#define QSERDES_V4_RX_RX_MODE_10_HIGH2\t\t\t0x1a0\n+#define QSERDES_V4_RX_RX_MODE_10_HIGH3\t\t\t0x1a4\n+#define QSERDES_V4_RX_RX_MODE_10_HIGH4\t\t\t0x1a8\n+#define QSERDES_V4_RX_PHPRE_CTRL\t\t\t0x1ac\n+#define QSERDES_V4_RX_PHPRE_INITVAL\t\t\t0x1b0\n+#define QSERDES_V4_RX_DFE_EN_TIMER\t\t\t0x1b4\n+#define QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET\t\t0x1b8\n+#define QSERDES_V4_RX_DCC_CTRL1\t\t\t\t0x1bc\n+#define QSERDES_V4_RX_DCC_CTRL2\t\t\t\t0x1c0\n+#define QSERDES_V4_RX_VTH_CODE\t\t\t\t0x1c4\n+#define QSERDES_V4_RX_VTH_MIN_THRESH\t\t\t0x1c8\n+#define QSERDES_V4_RX_VTH_MAX_THRESH\t\t\t0x1cc\n+#define QSERDES_V4_RX_ALOG_OBSV_BUS_CTRL_1\t\t0x1d0\n+#define QSERDES_V4_RX_PI_CTRL1\t\t\t\t0x1d4\n+#define QSERDES_V4_RX_PI_CTRL2\t\t\t\t0x1d8\n+#define QSERDES_V4_RX_PI_QUAD\t\t\t\t0x1dc\n+#define QSERDES_V4_RX_IDATA1\t\t\t\t0x1e0\n+#define QSERDES_V4_RX_IDATA2\t\t\t\t0x1e4\n+#define QSERDES_V4_RX_AUX_DATA1\t\t\t\t0x1e8\n+#define QSERDES_V4_RX_AUX_DATA2\t\t\t\t0x1ec\n+#define QSERDES_V4_RX_AC_JTAG_OUTP\t\t\t0x1f0\n+#define QSERDES_V4_RX_AC_JTAG_OUTN\t\t\t0x1f4\n+#define QSERDES_V4_RX_RX_SIGDET\t\t\t\t0x1f8\n+#define QSERDES_V4_RX_ALOG_OBSV_BUS_STATUS_1\t\t0x1fc\n+\n+#endif\ndiff --git a/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx.h b/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx.h\nnew file mode 100644\nindex 0000000000..d20694513e\n--- /dev/null\n+++ b/drivers/phy/qcom/phy-qcom-qmp-qserdes-txrx.h\n@@ -0,0 +1,205 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.\n+ */\n+\n+#ifndef QCOM_PHY_QMP_QSERDES_TXRX_H_\n+#define QCOM_PHY_QMP_QSERDES_TXRX_H_\n+\n+/* Only for QMP V2 PHY - TX registers */\n+#define QSERDES_TX_BIST_MODE_LANENO\t\t\t0x000\n+#define QSERDES_TX_BIST_INVERT\t\t\t\t0x004\n+#define QSERDES_TX_CLKBUF_ENABLE\t\t\t0x008\n+#define QSERDES_TX_CMN_CONTROL_ONE\t\t\t0x00c\n+#define QSERDES_TX_CMN_CONTROL_TWO\t\t\t0x010\n+#define QSERDES_TX_CMN_CONTROL_THREE\t\t\t0x014\n+#define QSERDES_TX_TX_EMP_POST1_LVL\t\t\t0x018\n+#define QSERDES_TX_TX_POST2_EMPH\t\t\t0x01c\n+#define QSERDES_TX_TX_BOOST_LVL_UP_DN\t\t\t0x020\n+#define QSERDES_TX_HP_PD_ENABLES\t\t\t0x024\n+#define QSERDES_TX_TX_IDLE_LVL_LARGE_AMP\t\t0x028\n+#define QSERDES_TX_TX_DRV_LVL\t\t\t\t0x02c\n+#define QSERDES_TX_TX_DRV_LVL_OFFSET\t\t\t0x030\n+#define QSERDES_TX_RESET_TSYNC_EN\t\t\t0x034\n+#define QSERDES_TX_PRE_STALL_LDO_BOOST_EN\t\t0x038\n+#define QSERDES_TX_TX_BAND\t\t\t\t0x03c\n+#define QSERDES_TX_SLEW_CNTL\t\t\t\t0x040\n+#define QSERDES_TX_INTERFACE_SELECT\t\t\t0x044\n+#define QSERDES_TX_LPB_EN\t\t\t\t0x048\n+#define QSERDES_TX_RES_CODE_LANE_TX\t\t\t0x04c\n+#define QSERDES_TX_RES_CODE_LANE_RX\t\t\t0x050\n+#define QSERDES_TX_RES_CODE_LANE_OFFSET\t\t\t0x054\n+#define QSERDES_TX_PERL_LENGTH1\t\t\t\t0x058\n+#define QSERDES_TX_PERL_LENGTH2\t\t\t\t0x05c\n+#define QSERDES_TX_SERDES_BYP_EN_OUT\t\t\t0x060\n+#define QSERDES_TX_DEBUG_BUS_SEL\t\t\t0x064\n+#define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN\t0x068\n+#define QSERDES_TX_TX_POL_INV\t\t\t\t0x06c\n+#define QSERDES_TX_PARRATE_REC_DETECT_IDLE_EN\t\t0x070\n+#define QSERDES_TX_BIST_PATTERN1\t\t\t0x074\n+#define QSERDES_TX_BIST_PATTERN2\t\t\t0x078\n+#define QSERDES_TX_BIST_PATTERN3\t\t\t0x07c\n+#define QSERDES_TX_BIST_PATTERN4\t\t\t0x080\n+#define QSERDES_TX_BIST_PATTERN5\t\t\t0x084\n+#define QSERDES_TX_BIST_PATTERN6\t\t\t0x088\n+#define QSERDES_TX_BIST_PATTERN7\t\t\t0x08c\n+#define QSERDES_TX_BIST_PATTERN8\t\t\t0x090\n+#define QSERDES_TX_LANE_MODE\t\t\t\t0x094\n+#define QSERDES_TX_IDAC_CAL_LANE_MODE\t\t\t0x098\n+#define QSERDES_TX_IDAC_CAL_LANE_MODE_CONFIGURATION\t0x09c\n+#define QSERDES_TX_ATB_SEL1\t\t\t\t0x0a0\n+#define QSERDES_TX_ATB_SEL2\t\t\t\t0x0a4\n+#define QSERDES_TX_RCV_DETECT_LVL\t\t\t0x0a8\n+#define QSERDES_TX_RCV_DETECT_LVL_2\t\t\t0x0ac\n+#define QSERDES_TX_PRBS_SEED1\t\t\t\t0x0b0\n+#define QSERDES_TX_PRBS_SEED2\t\t\t\t0x0b4\n+#define QSERDES_TX_PRBS_SEED3\t\t\t\t0x0b8\n+#define QSERDES_TX_PRBS_SEED4\t\t\t\t0x0bc\n+#define QSERDES_TX_RESET_GEN\t\t\t\t0x0c0\n+#define QSERDES_TX_RESET_GEN_MUXES\t\t\t0x0c4\n+#define QSERDES_TX_TRAN_DRVR_EMP_EN\t\t\t0x0c8\n+#define QSERDES_TX_TX_INTERFACE_MODE\t\t\t0x0cc\n+#define QSERDES_TX_PWM_CTRL\t\t\t\t0x0d0\n+#define QSERDES_TX_PWM_ENCODED_OR_DATA\t\t\t0x0d4\n+#define QSERDES_TX_PWM_GEAR_1_DIVIDER_BAND2\t\t0x0d8\n+#define QSERDES_TX_PWM_GEAR_2_DIVIDER_BAND2\t\t0x0dc\n+#define QSERDES_TX_PWM_GEAR_3_DIVIDER_BAND2\t\t0x0e0\n+#define QSERDES_TX_PWM_GEAR_4_DIVIDER_BAND2\t\t0x0e4\n+#define QSERDES_TX_PWM_GEAR_1_DIVIDER_BAND0_1\t\t0x0e8\n+#define QSERDES_TX_PWM_GEAR_2_DIVIDER_BAND0_1\t\t0x0ec\n+#define QSERDES_TX_PWM_GEAR_3_DIVIDER_BAND0_1\t\t0x0f0\n+#define QSERDES_TX_PWM_GEAR_4_DIVIDER_BAND0_1\t\t0x0f4\n+#define QSERDES_TX_VMODE_CTRL1\t\t\t\t0x0f8\n+#define QSERDES_TX_VMODE_CTRL2\t\t\t\t0x0fc\n+#define QSERDES_TX_TX_ALOG_INTF_OBSV_CNTL\t\t0x100\n+#define QSERDES_TX_BIST_STATUS\t\t\t\t0x104\n+#define QSERDES_TX_BIST_ERROR_COUNT1\t\t\t0x108\n+#define QSERDES_TX_BIST_ERROR_COUNT2\t\t\t0x10c\n+#define QSERDES_TX_TX_ALOG_INTF_OBSV\t\t\t0x110\n+\n+/* Only for QMP V2 PHY - RX registers */\n+#define QSERDES_RX_UCDR_FO_GAIN_HALF\t\t\t0x000\n+#define QSERDES_RX_UCDR_FO_GAIN_QUARTER\t\t\t0x004\n+#define QSERDES_RX_UCDR_FO_GAIN_EIGHTH\t\t\t0x008\n+#define QSERDES_RX_UCDR_FO_GAIN\t\t\t\t0x00c\n+#define QSERDES_RX_UCDR_SO_GAIN_HALF\t\t\t0x010\n+#define QSERDES_RX_UCDR_SO_GAIN_QUARTER\t\t\t0x014\n+#define QSERDES_RX_UCDR_SO_GAIN_EIGHTH\t\t\t0x018\n+#define QSERDES_RX_UCDR_SO_GAIN\t\t\t\t0x01c\n+#define QSERDES_RX_UCDR_SVS_FO_GAIN_HALF\t\t0x020\n+#define QSERDES_RX_UCDR_SVS_FO_GAIN_QUARTER\t\t0x024\n+#define QSERDES_RX_UCDR_SVS_FO_GAIN_EIGHTH\t\t0x028\n+#define QSERDES_RX_UCDR_SVS_FO_GAIN\t\t\t0x02c\n+#define QSERDES_RX_UCDR_SVS_SO_GAIN_HALF\t\t0x030\n+#define QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER\t\t0x034\n+#define QSERDES_RX_UCDR_SVS_SO_GAIN_EIGHTH\t\t0x038\n+#define QSERDES_RX_UCDR_SVS_SO_GAIN\t\t\t0x03c\n+#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN\t\t0x040\n+#define QSERDES_RX_UCDR_FD_GAIN\t\t\t\t0x044\n+#define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE\t0x048\n+#define QSERDES_RX_UCDR_FO_TO_SO_DELAY\t\t\t0x04c\n+#define QSERDES_RX_UCDR_FASTLOCK_COUNT_LOW\t\t0x050\n+#define QSERDES_RX_UCDR_FASTLOCK_COUNT_HIGH\t\t0x054\n+#define QSERDES_RX_UCDR_MODULATE\t\t\t0x058\n+#define QSERDES_RX_UCDR_PI_CONTROLS\t\t\t0x05c\n+#define QSERDES_RX_RBIST_CONTROL\t\t\t0x060\n+#define QSERDES_RX_AUX_CONTROL\t\t\t\t0x064\n+#define QSERDES_RX_AUX_DATA_TCOARSE\t\t\t0x068\n+#define QSERDES_RX_AUX_DATA_TFINE_LSB\t\t\t0x06c\n+#define QSERDES_RX_AUX_DATA_TFINE_MSB\t\t\t0x070\n+#define QSERDES_RX_RCLK_AUXDATA_SEL\t\t\t0x074\n+#define QSERDES_RX_AC_JTAG_ENABLE\t\t\t0x078\n+#define QSERDES_RX_AC_JTAG_INITP\t\t\t0x07c\n+#define QSERDES_RX_AC_JTAG_INITN\t\t\t0x080\n+#define QSERDES_RX_AC_JTAG_LVL\t\t\t\t0x084\n+#define QSERDES_RX_AC_JTAG_MODE\t\t\t\t0x088\n+#define QSERDES_RX_AC_JTAG_RESET\t\t\t0x08c\n+#define QSERDES_RX_RX_TERM_BW\t\t\t\t0x090\n+#define QSERDES_RX_RX_RCVR_IQ_EN\t\t\t0x094\n+#define QSERDES_RX_RX_IDAC_I_DC_OFFSETS\t\t\t0x098\n+#define QSERDES_RX_RX_IDAC_IBAR_DC_OFFSETS\t\t0x09c\n+#define QSERDES_RX_RX_IDAC_Q_DC_OFFSETS\t\t\t0x0a0\n+#define QSERDES_RX_RX_IDAC_QBAR_DC_OFFSETS\t\t0x0a4\n+#define QSERDES_RX_RX_IDAC_A_DC_OFFSETS\t\t\t0x0a8\n+#define QSERDES_RX_RX_IDAC_ABAR_DC_OFFSETS\t\t0x0ac\n+#define QSERDES_RX_RX_IDAC_EN\t\t\t\t0x0b0\n+#define QSERDES_RX_RX_IDAC_ENABLES\t\t\t0x0b4\n+#define QSERDES_RX_RX_IDAC_SIGN\t\t\t\t0x0b8\n+#define QSERDES_RX_RX_HIGHZ_HIGHRATE\t\t\t0x0bc\n+#define QSERDES_RX_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET\t0x0c0\n+#define QSERDES_RX_RX_EQ_GAIN1_LSB\t\t\t0x0c4\n+#define QSERDES_RX_RX_EQ_GAIN1_MSB\t\t\t0x0c8\n+#define QSERDES_RX_RX_EQ_GAIN2_LSB\t\t\t0x0cc\n+#define QSERDES_RX_RX_EQ_GAIN2_MSB\t\t\t0x0d0\n+#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL1\t\t0x0d4\n+#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2\t\t0x0d8\n+#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3\t\t0x0dc\n+#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4\t\t0x0e0\n+#define QSERDES_RX_RX_IDAC_CAL_CONFIGURATION\t\t0x0e4\n+#define QSERDES_RX_RX_IDAC_TSETTLE_LOW\t\t\t0x0e8\n+#define QSERDES_RX_RX_IDAC_TSETTLE_HIGH\t\t\t0x0ec\n+#define QSERDES_RX_RX_IDAC_ENDSAMP_LOW\t\t\t0x0f0\n+#define QSERDES_RX_RX_IDAC_ENDSAMP_HIGH\t\t\t0x0f4\n+#define QSERDES_RX_RX_IDAC_MIDPOINT_LOW\t\t\t0x0f8\n+#define QSERDES_RX_RX_IDAC_MIDPOINT_HIGH\t\t0x0fc\n+#define QSERDES_RX_RX_EQ_OFFSET_LSB\t\t\t0x100\n+#define QSERDES_RX_RX_EQ_OFFSET_MSB\t\t\t0x104\n+#define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1\t\t0x108\n+#define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2\t\t0x10c\n+#define QSERDES_RX_SIGDET_ENABLES\t\t\t0x110\n+#define QSERDES_RX_SIGDET_CNTRL\t\t\t\t0x114\n+#define QSERDES_RX_SIGDET_LVL\t\t\t\t0x118\n+#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL\t\t0x11c\n+#define QSERDES_RX_RX_BAND\t\t\t\t0x120\n+#define QSERDES_RX_CDR_FREEZE_UP_DN\t\t\t0x124\n+#define QSERDES_RX_CDR_RESET_OVERRIDE\t\t\t0x128\n+#define QSERDES_RX_RX_INTERFACE_MODE\t\t\t0x12c\n+#define QSERDES_RX_JITTER_GEN_MODE\t\t\t0x130\n+#define QSERDES_RX_BUJ_AMP\t\t\t\t0x134\n+#define QSERDES_RX_SJ_AMP1\t\t\t\t0x138\n+#define QSERDES_RX_SJ_AMP2\t\t\t\t0x13c\n+#define QSERDES_RX_SJ_PER1\t\t\t\t0x140\n+#define QSERDES_RX_SJ_PER2\t\t\t\t0x144\n+#define QSERDES_RX_BUJ_STEP_FREQ1\t\t\t0x148\n+#define QSERDES_RX_BUJ_STEP_FREQ2\t\t\t0x14c\n+#define QSERDES_RX_PPM_OFFSET1\t\t\t\t0x150\n+#define QSERDES_RX_PPM_OFFSET2\t\t\t\t0x154\n+#define QSERDES_RX_SIGN_PPM_PERIOD1\t\t\t0x158\n+#define QSERDES_RX_SIGN_PPM_PERIOD2\t\t\t0x15c\n+#define QSERDES_RX_SSC_CTRL\t\t\t\t0x160\n+#define QSERDES_RX_SSC_COUNT1\t\t\t\t0x164\n+#define QSERDES_RX_SSC_COUNT2\t\t\t\t0x168\n+#define QSERDES_RX_RX_ALOG_INTF_OBSV_CNTL\t\t0x16c\n+#define QSERDES_RX_RX_PWM_ENABLE_AND_DATA\t\t0x170\n+#define QSERDES_RX_RX_PWM_GEAR1_TIMEOUT_COUNT\t\t0x174\n+#define QSERDES_RX_RX_PWM_GEAR2_TIMEOUT_COUNT\t\t0x178\n+#define QSERDES_RX_RX_PWM_GEAR3_TIMEOUT_COUNT\t\t0x17c\n+#define QSERDES_RX_RX_PWM_GEAR4_TIMEOUT_COUNT\t\t0x180\n+#define QSERDES_RX_PI_CTRL1\t\t\t\t0x184\n+#define QSERDES_RX_PI_CTRL2\t\t\t\t0x188\n+#define QSERDES_RX_PI_QUAD\t\t\t\t0x18c\n+#define QSERDES_RX_IDATA1\t\t\t\t0x190\n+#define QSERDES_RX_IDATA2\t\t\t\t0x194\n+#define QSERDES_RX_AUX_DATA1\t\t\t\t0x198\n+#define QSERDES_RX_AUX_DATA2\t\t\t\t0x19c\n+#define QSERDES_RX_AC_JTAG_OUTP\t\t\t\t0x1a0\n+#define QSERDES_RX_AC_JTAG_OUTN\t\t\t\t0x1a4\n+#define QSERDES_RX_RX_SIGDET\t\t\t\t0x1a8\n+#define QSERDES_RX_RX_VDCOFF\t\t\t\t0x1ac\n+#define QSERDES_RX_IDAC_CAL_ON\t\t\t\t0x1b0\n+#define QSERDES_RX_IDAC_STATUS_I\t\t\t0x1b4\n+#define QSERDES_RX_IDAC_STATUS_IBAR\t\t\t0x1b8\n+#define QSERDES_RX_IDAC_STATUS_Q\t\t\t0x1bc\n+#define QSERDES_RX_IDAC_STATUS_QBAR\t\t\t0x1c0\n+#define QSERDES_RX_IDAC_STATUS_A\t\t\t0x1c4\n+#define QSERDES_RX_IDAC_STATUS_ABAR\t\t\t0x1c8\n+#define QSERDES_RX_CALST_STATUS_I\t\t\t0x1cc\n+#define QSERDES_RX_CALST_STATUS_Q\t\t\t0x1d0\n+#define QSERDES_RX_CALST_STATUS_A\t\t\t0x1d4\n+#define QSERDES_RX_RX_ALOG_INTF_OBSV\t\t\t0x1d8\n+#define QSERDES_RX_READ_EQCODE\t\t\t\t0x1dc\n+#define QSERDES_RX_READ_OFFSETCODE\t\t\t0x1e0\n+#define QSERDES_RX_IA_ERROR_COUNTER_LOW\t\t\t0x1e4\n+#define QSERDES_RX_IA_ERROR_COUNTER_HIGH\t\t0x1e8\n+\n+#endif\n",
    "prefixes": [
        "02/17"
    ]
}