Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 1814130,
    "url": "http://patchwork.ozlabs.org/api/patches/1814130/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1690533192-22220-3-git-send-email-quic_srichara@quicinc.com/",
    "project": {
        "id": 42,
        "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api",
        "name": "Linux GPIO development",
        "link_name": "linux-gpio",
        "list_id": "linux-gpio.vger.kernel.org",
        "list_email": "linux-gpio@vger.kernel.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": "",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<1690533192-22220-3-git-send-email-quic_srichara@quicinc.com>",
    "list_archive_url": null,
    "date": "2023-07-28T08:33:08",
    "name": "[V12,2/6] clk: qcom: Add Global Clock controller (GCC) driver for IPQ5018",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "ebc10ced1171cd73326dd470b41279efa5d0d22c",
    "submitter": {
        "id": 84297,
        "url": "http://patchwork.ozlabs.org/api/people/84297/?format=api",
        "name": "Sricharan Ramabadhran",
        "email": "quic_srichara@quicinc.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1690533192-22220-3-git-send-email-quic_srichara@quicinc.com/mbox/",
    "series": [
        {
            "id": 366189,
            "url": "http://patchwork.ozlabs.org/api/series/366189/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=366189",
            "date": "2023-07-28T08:33:06",
            "name": "Add minimal boot support for IPQ5018",
            "version": 12,
            "mbox": "http://patchwork.ozlabs.org/series/366189/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/1814130/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/1814130/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<linux-gpio-owner@vger.kernel.org>",
        "X-Original-To": "incoming@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming@legolas.ozlabs.org",
        "Authentication-Results": [
            "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2620:137:e000::1:20; helo=out1.vger.email;\n envelope-from=linux-gpio-owner@vger.kernel.org; receiver=<UNKNOWN>)",
            "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=quicinc.com header.i=@quicinc.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=SoNCdVqk;\n\tdkim-atps=neutral"
        ],
        "Received": [
            "from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20])\n\tby legolas.ozlabs.org (Postfix) with ESMTP id 4RC1CY1Wz5z1yZb\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 28 Jul 2023 18:34:49 +1000 (AEST)",
            "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n        id S235068AbjG1Ier (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n        Fri, 28 Jul 2023 04:34:47 -0400",
            "from lindbergh.monkeyblade.net ([23.128.96.19]:35240 \"EHLO\n        lindbergh.monkeyblade.net\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n        with ESMTP id S234957AbjG1Ie2 (ORCPT\n        <rfc822;linux-gpio@vger.kernel.org>); Fri, 28 Jul 2023 04:34:28 -0400",
            "from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com\n [205.220.168.131])\n        by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 07A03269E;\n        Fri, 28 Jul 2023 01:34:24 -0700 (PDT)",
            "from pps.filterd (m0279862.ppops.net [127.0.0.1])\n        by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id\n 36S54d7F003948;\n        Fri, 28 Jul 2023 08:33:50 GMT",
            "from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com\n [129.46.96.20])\n        by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3s469hgd8p-1\n        (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256\n verify=NOT);\n        Fri, 28 Jul 2023 08:33:49 +0000",
            "from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com\n [10.47.97.35])\n        by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id\n 36S8XkpZ019690\n        (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256\n verify=NOT);\n        Fri, 28 Jul 2023 08:33:46 GMT",
            "from srichara-linux.qualcomm.com (10.80.80.8) by\n nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.1118.30; Fri, 28 Jul 2023 01:33:37 -0700"
        ],
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=qcppdkim1;\n bh=yCun2ej6Aswb6A24y1CU4gRRKc0Hrk+/ozKnhI9tQhQ=;\n b=SoNCdVqkNrP4760/jghEaiESMY4pf8dJXDWuOP+Vpo5vwhpEMXz2Cj8486h4sHQMIHWz\n EQNZRFPR9lrsdDRUkVDRaU9WhaCmz3T1sfmfeRIiKuM8jrNQ5h3jcF4lrCOTAg8A12Y4\n +Ira9YSPNA0/9ZlEEFDEpChlbsltn13o3OTUSoTOYib5J24GlJPIUeqOhTFu8rE7LkMq\n PUt34UmmwWRVhRtb8W+nbsJ8I9BwpmDicS7D8XEx169FKiOMAVkrLiImb9zprrV6vnD1\n TY2O++yDLcpZegmNl4eAK7Yxo8VZrcKoZJVIx3Sr+mLfaFV0+O5wdn865NOdVF3cHOwF Ng==",
        "From": "Sricharan Ramabadhran <quic_srichara@quicinc.com>",
        "To": "<agross@kernel.org>, <andersson@kernel.org>,\n        <konrad.dybcio@linaro.org>, <robh+dt@kernel.org>,\n        <krzysztof.kozlowski+dt@linaro.org>, <mturquette@baylibre.com>,\n        <sboyd@kernel.org>, <ulf.hansson@linaro.org>,\n        <linus.walleij@linaro.org>, <catalin.marinas@arm.com>,\n        <will@kernel.org>, <p.zabel@pengutronix.de>,\n        <linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>,\n        <linux-kernel@vger.kernel.org>, <linux-mmc@vger.kernel.org>,\n        <linux-gpio@vger.kernel.org>,\n        <linux-arm-kernel@lists.infradead.org>, <robimarko@gmail.com>,\n        <krzysztof.kozlowski@linaro.org>, <andy.shevchenko@gmail.com>",
        "CC": "<quic_srichara@quicinc.com>",
        "Subject": "[PATCH V12 2/6] clk: qcom: Add Global Clock controller (GCC) driver\n for IPQ5018",
        "Date": "Fri, 28 Jul 2023 14:03:08 +0530",
        "Message-ID": "<1690533192-22220-3-git-send-email-quic_srichara@quicinc.com>",
        "X-Mailer": "git-send-email 2.7.4",
        "In-Reply-To": "<1690533192-22220-1-git-send-email-quic_srichara@quicinc.com>",
        "References": "<1690533192-22220-1-git-send-email-quic_srichara@quicinc.com>",
        "MIME-Version": "1.0",
        "Content-Type": "text/plain",
        "X-Originating-IP": "[10.80.80.8]",
        "X-ClientProxiedBy": "nasanex01a.na.qualcomm.com (10.52.223.231) To\n nalasex01c.na.qualcomm.com (10.47.97.35)",
        "X-QCInternal": "smtphost",
        "X-Proofpoint-Virus-Version": [
            "vendor=nai engine=6200 definitions=5800\n signatures=585085",
            "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26\n definitions=2023-07-27_10,2023-07-26_01,2023-05-22_02"
        ],
        "X-Proofpoint-ORIG-GUID": "SmYlhxsrhTQ4TjYQTBAnzDW8i2686DNk",
        "X-Proofpoint-GUID": "SmYlhxsrhTQ4TjYQTBAnzDW8i2686DNk",
        "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n suspectscore=0\n priorityscore=1501 impostorscore=0 malwarescore=0 phishscore=0\n adultscore=0 clxscore=1015 mlxlogscore=999 mlxscore=0 spamscore=0\n lowpriorityscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx\n scancount=1 engine=8.12.0-2306200000 definitions=main-2307280077",
        "X-Spam-Status": "No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n        DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,\n        SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham\n        autolearn_force=no version=3.4.6",
        "X-Spam-Checker-Version": "SpamAssassin 3.4.6 (2021-04-09) on\n        lindbergh.monkeyblade.net",
        "Precedence": "bulk",
        "List-ID": "<linux-gpio.vger.kernel.org>",
        "X-Mailing-List": "linux-gpio@vger.kernel.org"
    },
    "content": "Add support for the global clock controller found on IPQ5018\nbased devices.\n\nAcked-by: Konrad Dybcio <konrad.dybcio@linaro.org>\nCo-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>\nSigned-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>\nCo-developed-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>\nSigned-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>\nSigned-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>\n---\n drivers/clk/qcom/Kconfig       |    8 +\n drivers/clk/qcom/Makefile      |    1 +\n drivers/clk/qcom/gcc-ipq5018.c | 3724 ++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 3733 insertions(+)\n create mode 100644 drivers/clk/qcom/gcc-ipq5018.c",
    "diff": "diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig\nindex 263e55d..1fc8d25 100644\n--- a/drivers/clk/qcom/Kconfig\n+++ b/drivers/clk/qcom/Kconfig\n@@ -145,6 +145,14 @@ config IPQ_GCC_4019\n \t  Say Y if you want to use peripheral devices such as UART, SPI,\n \t  i2c, USB, SD/eMMC, etc.\n \n+config IPQ_GCC_5018\n+\ttristate \"IPQ5018 Global Clock Controller\"\n+\tdepends on ARM64 || COMPILE_TEST\n+\thelp\n+\t  Support for global clock controller on ipq5018 devices.\n+\t  Say Y if you want to use peripheral devices such as UART, SPI,\n+\t  i2c, USB, SD/eMMC, etc.\n+\n config IPQ_GCC_5332\n \ttristate \"IPQ5332 Global Clock Controller\"\n \tdepends on ARM64 || COMPILE_TEST\ndiff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile\nindex e6e2942..0e623bc 100644\n--- a/drivers/clk/qcom/Makefile\n+++ b/drivers/clk/qcom/Makefile\n@@ -24,6 +24,7 @@ obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o\n obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o\n obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o\n obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o\n+obj-$(CONFIG_IPQ_GCC_5018) += gcc-ipq5018.o\n obj-$(CONFIG_IPQ_GCC_5332) += gcc-ipq5332.o\n obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o\n obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o\ndiff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c\nnew file mode 100644\nindex 0000000..313ff22\n--- /dev/null\n+++ b/drivers/clk/qcom/gcc-ipq5018.c\n@@ -0,0 +1,3724 @@\n+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+/*\n+ * Copyright (c) 2023, The Linux Foundation. All rights reserved.\n+ */\n+#include <linux/clk-provider.h>\n+#include <linux/module.h>\n+#include <linux/of_device.h>\n+#include <linux/regmap.h>\n+\n+#include <dt-bindings/clock/qcom,gcc-ipq5018.h>\n+#include <dt-bindings/reset/qcom,gcc-ipq5018.h>\n+\n+#include \"clk-alpha-pll.h\"\n+#include \"clk-branch.h\"\n+#include \"clk-rcg.h\"\n+#include \"clk-regmap.h\"\n+#include \"clk-regmap-divider.h\"\n+#include \"clk-regmap-mux.h\"\n+#include \"clk-regmap-phy-mux.h\"\n+#include \"reset.h\"\n+\n+/* Need to match the order of clocks in DT binding */\n+enum {\n+\tDT_XO,\n+\tDT_SLEEP_CLK,\n+\tDT_PCIE20_PHY0_PIPE_CLK,\n+\tDT_PCIE20_PHY1_PIPE_CLK,\n+\tDT_USB3_PHY0_CC_PIPE_CLK,\n+\tDT_GEPHY_RX_CLK,\n+\tDT_GEPHY_TX_CLK,\n+\tDT_UNIPHY_RX_CLK,\n+\tDT_UNIPHY_TX_CLK,\n+};\n+\n+enum {\n+\tP_XO,\n+\tP_CORE_PI_SLEEP_CLK,\n+\tP_PCIE20_PHY0_PIPE,\n+\tP_PCIE20_PHY1_PIPE,\n+\tP_USB3PHY_0_PIPE,\n+\tP_GEPHY_RX,\n+\tP_GEPHY_TX,\n+\tP_UNIPHY_RX,\n+\tP_UNIPHY_TX,\n+\tP_GPLL0,\n+\tP_GPLL0_DIV2,\n+\tP_GPLL2,\n+\tP_GPLL4,\n+\tP_UBI32_PLL,\n+};\n+\n+static const struct clk_parent_data gcc_xo_data[] = {\n+\t{ .index = DT_XO },\n+};\n+\n+static const struct clk_parent_data gcc_sleep_clk_data[] = {\n+\t{ .index = DT_SLEEP_CLK },\n+};\n+\n+static struct clk_alpha_pll gpll0_main = {\n+\t.offset = 0x21000,\n+\t.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],\n+\t.clkr = {\n+\t\t.enable_reg = 0x0b000,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gpll0_main\",\n+\t\t\t.parent_data = gcc_xo_data,\n+\t\t\t.num_parents = ARRAY_SIZE(gcc_xo_data),\n+\t\t\t.ops = &clk_alpha_pll_stromer_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_alpha_pll gpll2_main = {\n+\t.offset = 0x4a000,\n+\t.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],\n+\t.clkr = {\n+\t\t.enable_reg = 0x0b000,\n+\t\t.enable_mask = BIT(2),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gpll2_main\",\n+\t\t\t.parent_data = gcc_xo_data,\n+\t\t\t.num_parents = ARRAY_SIZE(gcc_xo_data),\n+\t\t\t.ops = &clk_alpha_pll_stromer_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_alpha_pll gpll4_main = {\n+\t.offset = 0x24000,\n+\t.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],\n+\t.clkr = {\n+\t\t.enable_reg = 0x0b000,\n+\t\t.enable_mask = BIT(5),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gpll4_main\",\n+\t\t\t.parent_data = gcc_xo_data,\n+\t\t\t.num_parents = ARRAY_SIZE(gcc_xo_data),\n+\t\t\t.ops = &clk_alpha_pll_stromer_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_alpha_pll ubi32_pll_main = {\n+\t.offset = 0x25000,\n+\t.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],\n+\t.clkr = {\n+\t\t.enable_reg = 0x0b000,\n+\t\t.enable_mask = BIT(6),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"ubi32_pll_main\",\n+\t\t\t.parent_data = gcc_xo_data,\n+\t\t\t.num_parents = ARRAY_SIZE(gcc_xo_data),\n+\t\t\t.ops = &clk_alpha_pll_stromer_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_alpha_pll_postdiv gpll0 = {\n+\t.offset = 0x21000,\n+\t.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],\n+\t.width = 4,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"gpll0\",\n+\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t&gpll0_main.clkr.hw,\n+\t\t},\n+\t\t.num_parents = 1,\n+\t\t.ops = &clk_alpha_pll_postdiv_ro_ops,\n+\t\t.flags = CLK_SET_RATE_PARENT,\n+\t},\n+};\n+\n+static struct clk_alpha_pll_postdiv gpll2 = {\n+\t.offset = 0x4a000,\n+\t.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],\n+\t.width = 4,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"gpll2\",\n+\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t&gpll2_main.clkr.hw,\n+\t\t},\n+\t\t.num_parents = 1,\n+\t\t.ops = &clk_alpha_pll_postdiv_ro_ops,\n+\t\t.flags = CLK_SET_RATE_PARENT,\n+\t},\n+};\n+\n+static struct clk_alpha_pll_postdiv gpll4 = {\n+\t.offset = 0x24000,\n+\t.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],\n+\t.width = 4,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"gpll4\",\n+\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t&gpll4_main.clkr.hw,\n+\t\t},\n+\t\t.num_parents = 1,\n+\t\t.ops = &clk_alpha_pll_postdiv_ro_ops,\n+\t\t.flags = CLK_SET_RATE_PARENT,\n+\t},\n+};\n+\n+static struct clk_alpha_pll_postdiv ubi32_pll = {\n+\t.offset = 0x25000,\n+\t.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],\n+\t.width = 4,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"ubi32_pll\",\n+\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t&ubi32_pll_main.clkr.hw,\n+\t\t},\n+\t\t.num_parents = 1,\n+\t\t.ops = &clk_alpha_pll_postdiv_ro_ops,\n+\t\t.flags = CLK_SET_RATE_PARENT,\n+\t},\n+};\n+\n+static struct clk_fixed_factor gpll0_out_main_div2 = {\n+\t.mult = 1,\n+\t.div = 2,\n+\t.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"gpll0_out_main_div2\",\n+\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t&gpll0_main.clkr.hw,\n+\t\t},\n+\t\t.num_parents = 1,\n+\t\t.ops = &clk_fixed_factor_ops,\n+\t\t.flags = CLK_SET_RATE_PARENT,\n+\t},\n+};\n+\n+static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .hw = &gpll0_out_main_div2.hw },\n+};\n+\n+static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0, 1 },\n+\t{ P_GPLL0_DIV2, 4 },\n+};\n+\n+static const struct clk_parent_data gcc_xo_gpll0[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll0.clkr.hw },\n+};\n+\n+static const struct parent_map gcc_xo_gpll0_map[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0, 1 },\n+};\n+\n+static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll0_out_main_div2.hw },\n+\t{ .hw = &gpll0.clkr.hw },\n+};\n+\n+static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0_DIV2, 2 },\n+\t{ P_GPLL0, 1 },\n+};\n+\n+static const struct clk_parent_data gcc_xo_ubi32_gpll0[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &ubi32_pll.clkr.hw },\n+\t{ .hw = &gpll0.clkr.hw },\n+};\n+\n+static const struct parent_map gcc_xo_ubi32_gpll0_map[] = {\n+\t{ P_XO, 0 },\n+\t{ P_UBI32_PLL, 1 },\n+\t{ P_GPLL0, 2 },\n+};\n+\n+static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .hw = &gpll2.clkr.hw },\n+};\n+\n+static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0, 1 },\n+\t{ P_GPLL2, 2 },\n+};\n+\n+static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .hw = &gpll2.clkr.hw },\n+\t{ .hw = &gpll4.clkr.hw },\n+};\n+\n+static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_map[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0, 1 },\n+\t{ P_GPLL2, 2 },\n+\t{ P_GPLL4, 3 },\n+};\n+\n+static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .hw = &gpll4.clkr.hw },\n+};\n+\n+static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0, 1 },\n+\t{ P_GPLL4, 2 },\n+};\n+\n+static const struct clk_parent_data gcc_xo_gpll0_core_pi_sleep_clk[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .index = DT_SLEEP_CLK },\n+};\n+\n+static const struct parent_map gcc_xo_gpll0_core_pi_sleep_clk_map[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0, 2 },\n+\t{ P_CORE_PI_SLEEP_CLK, 6 },\n+};\n+\n+static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .hw = &gpll0_out_main_div2.hw },\n+\t{ .index = DT_SLEEP_CLK },\n+};\n+\n+static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0, 1 },\n+\t{ P_GPLL0_DIV2, 4 },\n+\t{ P_CORE_PI_SLEEP_CLK, 6 },\n+};\n+\n+static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .hw = &gpll2.clkr.hw },\n+\t{ .hw = &gpll0_out_main_div2.hw },\n+};\n+\n+static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0, 1 },\n+\t{ P_GPLL2, 2 },\n+\t{ P_GPLL0_DIV2, 4 },\n+};\n+\n+static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll0_out_main_div2[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll4.clkr.hw },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .hw = &gpll0_out_main_div2.hw },\n+};\n+\n+static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL4, 1 },\n+\t{ P_GPLL0, 2 },\n+\t{ P_GPLL0_DIV2, 4 },\n+};\n+\n+static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map2[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL4, 1 },\n+\t{ P_GPLL0, 3 },\n+\t{ P_GPLL0_DIV2, 4 },\n+};\n+\n+static const struct clk_parent_data gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0[] = {\n+\t{ .index = DT_XO },\n+\t{ .index = DT_GEPHY_RX_CLK },\n+\t{ .index = DT_GEPHY_TX_CLK },\n+\t{ .hw = &ubi32_pll.clkr.hw },\n+\t{ .hw = &gpll0.clkr.hw },\n+};\n+\n+static const struct parent_map gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0_map[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GEPHY_RX, 1 },\n+\t{ P_GEPHY_TX, 2 },\n+\t{ P_UBI32_PLL, 3 },\n+\t{ P_GPLL0, 4 },\n+};\n+\n+static const struct clk_parent_data gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0[] = {\n+\t{ .index = DT_XO },\n+\t{ .index = DT_GEPHY_TX_CLK },\n+\t{ .index = DT_GEPHY_RX_CLK },\n+\t{ .hw = &ubi32_pll.clkr.hw },\n+\t{ .hw = &gpll0.clkr.hw },\n+};\n+\n+static const struct parent_map gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0_map[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GEPHY_TX, 1 },\n+\t{ P_GEPHY_RX, 2 },\n+\t{ P_UBI32_PLL, 3 },\n+\t{ P_GPLL0, 4 },\n+};\n+\n+static const struct clk_parent_data gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0[] = {\n+\t{ .index = DT_XO },\n+\t{ .index = DT_UNIPHY_RX_CLK },\n+\t{ .index = DT_UNIPHY_TX_CLK },\n+\t{ .hw = &ubi32_pll.clkr.hw },\n+\t{ .hw = &gpll0.clkr.hw },\n+};\n+\n+static const struct parent_map gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0_map[] = {\n+\t{ P_XO, 0 },\n+\t{ P_UNIPHY_RX, 1 },\n+\t{ P_UNIPHY_TX, 2 },\n+\t{ P_UBI32_PLL, 3 },\n+\t{ P_GPLL0, 4 },\n+};\n+\n+static const struct clk_parent_data gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0[] = {\n+\t{ .index = DT_XO },\n+\t{ .index = DT_UNIPHY_TX_CLK },\n+\t{ .index = DT_UNIPHY_RX_CLK },\n+\t{ .hw = &ubi32_pll.clkr.hw },\n+\t{ .hw = &gpll0.clkr.hw },\n+};\n+\n+static const struct parent_map gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0_map[] = {\n+\t{ P_XO, 0 },\n+\t{ P_UNIPHY_TX, 1 },\n+\t{ P_UNIPHY_RX, 2 },\n+\t{ P_UBI32_PLL, 3 },\n+\t{ P_GPLL0, 4 },\n+};\n+\n+static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {\n+\t{ .index = DT_PCIE20_PHY0_PIPE_CLK },\n+\t{ .index = DT_XO },\n+};\n+\n+static const struct parent_map gcc_pcie20_phy0_pipe_clk_xo_map[] = {\n+\t{ P_PCIE20_PHY0_PIPE, 0 },\n+\t{ P_XO, 2 },\n+};\n+\n+static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {\n+\t{ .index = DT_PCIE20_PHY1_PIPE_CLK },\n+\t{ .index = DT_XO },\n+};\n+\n+static const struct parent_map gcc_pcie20_phy1_pipe_clk_xo_map[] = {\n+\t{ P_PCIE20_PHY1_PIPE, 0 },\n+\t{ P_XO, 2 },\n+};\n+\n+static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {\n+\t{ .index = DT_USB3_PHY0_CC_PIPE_CLK },\n+\t{ .index = DT_XO },\n+};\n+\n+static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {\n+\t{ P_USB3PHY_0_PIPE, 0 },\n+\t{ P_XO, 2 },\n+};\n+\n+static const struct freq_tbl ftbl_adss_pwm_clk_src[] = {\n+\tF(24000000, P_XO, 1, 0, 0),\n+\tF(100000000, P_GPLL0, 8, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 adss_pwm_clk_src = {\n+\t.cmd_rcgr = 0x1f008,\n+\t.freq_tbl = ftbl_adss_pwm_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"adss_pwm_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {\n+\tF(50000000, P_GPLL0, 16, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {\n+\t.cmd_rcgr = 0x0200c,\n+\t.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"blsp1_qup1_i2c_apps_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {\n+\t.cmd_rcgr = 0x03000,\n+\t.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"blsp1_qup2_i2c_apps_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {\n+\t.cmd_rcgr = 0x04000,\n+\t.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"blsp1_qup3_i2c_apps_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {\n+\tF(960000, P_XO, 10, 2, 5),\n+\tF(4800000, P_XO, 5, 0, 0),\n+\tF(9600000, P_XO, 2, 4, 5),\n+\tF(16000000, P_GPLL0, 10, 1, 5),\n+\tF(24000000, P_XO, 1, 0, 0),\n+\tF(50000000, P_GPLL0, 16, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {\n+\t.cmd_rcgr = 0x02024,\n+\t.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,\n+\t.mnd_width = 8,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"blsp1_qup1_spi_apps_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {\n+\t.cmd_rcgr = 0x03014,\n+\t.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,\n+\t.mnd_width = 8,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"blsp1_qup2_spi_apps_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {\n+\t.cmd_rcgr = 0x04014,\n+\t.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,\n+\t.mnd_width = 8,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"blsp1_qup3_spi_apps_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {\n+\tF(3686400, P_GPLL0_DIV2, 1, 144, 15625),\n+\tF(7372800, P_GPLL0_DIV2, 1, 288, 15625),\n+\tF(14745600, P_GPLL0_DIV2, 1, 576, 15625),\n+\tF(24000000, P_XO, 1, 0, 0),\n+\tF(25000000, P_GPLL0, 16, 1, 2),\n+\tF(40000000, P_GPLL0, 1, 1, 20),\n+\tF(46400000, P_GPLL0, 1, 29, 500),\n+\tF(48000000, P_GPLL0, 1, 3, 50),\n+\tF(51200000, P_GPLL0, 1, 8, 125),\n+\tF(56000000, P_GPLL0, 1, 7, 100),\n+\tF(58982400, P_GPLL0, 1, 1152, 15625),\n+\tF(60000000, P_GPLL0, 1, 3, 40),\n+\tF(64000000, P_GPLL0, 10, 4, 5),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 blsp1_uart1_apps_clk_src = {\n+\t.cmd_rcgr = 0x02044,\n+\t.freq_tbl = ftbl_blsp1_uart_apps_clk_src,\n+\t.mnd_width = 16,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"blsp1_uart1_apps_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 blsp1_uart2_apps_clk_src = {\n+\t.cmd_rcgr = 0x03034,\n+\t.freq_tbl = ftbl_blsp1_uart_apps_clk_src,\n+\t.mnd_width = 16,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"blsp1_uart2_apps_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_crypto_clk_src[] = {\n+\tF(160000000, P_GPLL0, 5, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 crypto_clk_src = {\n+\t.cmd_rcgr = 0x16004,\n+\t.freq_tbl = ftbl_crypto_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"crypto_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_gmac0_tx_clk_src[] = {\n+\tF(2500000, P_GEPHY_TX, 5, 0, 0),\n+\tF(24000000, P_XO, 1, 0, 0),\n+\tF(25000000, P_GEPHY_TX, 5, 0, 0),\n+\tF(125000000, P_GEPHY_TX, 1, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 gmac0_rx_clk_src = {\n+\t.cmd_rcgr = 0x68020,\n+\t.parent_map = gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0_map,\n+\t.hid_width = 5,\n+\t.freq_tbl = ftbl_gmac0_tx_clk_src,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"gmac0_rx_clk_src\",\n+\t\t.parent_data = gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gephy_gcc_rx_gephy_gcc_tx_ubi32_pll_gpll0),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_regmap_div gmac0_rx_div_clk_src = {\n+\t.reg = 0x68420,\n+\t.shift = 0,\n+\t.width = 4,\n+\t.clkr = {\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gmac0_rx_div_clk_src\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gmac0_rx_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.ops = &clk_regmap_div_ops,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_rcg2 gmac0_tx_clk_src = {\n+\t.cmd_rcgr = 0x68028,\n+\t.parent_map = gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0_map,\n+\t.hid_width = 5,\n+\t.freq_tbl = ftbl_gmac0_tx_clk_src,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"gmac0_tx_clk_src\",\n+\t\t.parent_data = gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gephy_gcc_tx_gephy_gcc_rx_ubi32_pll_gpll0),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_regmap_div gmac0_tx_div_clk_src = {\n+\t.reg = 0x68424,\n+\t.shift = 0,\n+\t.width = 4,\n+\t.clkr = {\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gmac0_tx_div_clk_src\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gmac0_tx_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.ops = &clk_regmap_div_ops,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_gmac1_rx_clk_src[] = {\n+\tF(2500000, P_UNIPHY_RX, 12.5, 0, 0),\n+\tF(24000000, P_XO, 1, 0, 0),\n+\tF(25000000, P_UNIPHY_RX, 2.5, 0, 0),\n+\tF(125000000, P_UNIPHY_RX, 2.5, 0, 0),\n+\tF(125000000, P_UNIPHY_RX, 1, 0, 0),\n+\tF(312500000, P_UNIPHY_RX, 1, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 gmac1_rx_clk_src = {\n+\t.cmd_rcgr = 0x68030,\n+\t.parent_map = gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0_map,\n+\t.hid_width = 5,\n+\t.freq_tbl = ftbl_gmac1_rx_clk_src,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"gmac1_rx_clk_src\",\n+\t\t.parent_data = gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_uniphy_gcc_rx_uniphy_gcc_tx_ubi32_pll_gpll0),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_regmap_div gmac1_rx_div_clk_src = {\n+\t.reg = 0x68430,\n+\t.shift = 0,\n+\t.width = 4,\n+\t.clkr = {\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gmac1_rx_div_clk_src\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gmac1_rx_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.ops = &clk_regmap_div_ops,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_gmac1_tx_clk_src[] = {\n+\tF(2500000, P_UNIPHY_TX, 12.5, 0, 0),\n+\tF(24000000, P_XO, 1, 0, 0),\n+\tF(25000000, P_UNIPHY_TX, 2.5, 0, 0),\n+\tF(125000000, P_UNIPHY_TX, 2.5, 0, 0),\n+\tF(125000000, P_UNIPHY_TX, 1, 0, 0),\n+\tF(312500000, P_UNIPHY_TX, 1, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 gmac1_tx_clk_src = {\n+\t.cmd_rcgr = 0x68038,\n+\t.parent_map = gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0_map,\n+\t.hid_width = 5,\n+\t.freq_tbl = ftbl_gmac1_tx_clk_src,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"gmac1_tx_clk_src\",\n+\t\t.parent_data = gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_uniphy_gcc_tx_uniphy_gcc_rx_ubi32_pll_gpll0),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_regmap_div gmac1_tx_div_clk_src = {\n+\t.reg = 0x68434,\n+\t.shift = 0,\n+\t.width = 4,\n+\t.clkr = {\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gmac1_tx_div_clk_src\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gmac1_tx_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.ops = &clk_regmap_div_ops,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_gmac_clk_src[] = {\n+\tF(240000000, P_GPLL4, 5, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 gmac_clk_src = {\n+\t.cmd_rcgr = 0x68080,\n+\t.parent_map = gcc_xo_gpll0_gpll4_map,\n+\t.hid_width = 5,\n+\t.freq_tbl = ftbl_gmac_clk_src,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"gmac_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll4,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_gp_clk_src[] = {\n+\tF(200000000, P_GPLL0, 4, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 gp1_clk_src = {\n+\t.cmd_rcgr = 0x08004,\n+\t.freq_tbl = ftbl_gp_clk_src,\n+\t.mnd_width = 8,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"gp1_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 gp2_clk_src = {\n+\t.cmd_rcgr = 0x09004,\n+\t.freq_tbl = ftbl_gp_clk_src,\n+\t.mnd_width = 8,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"gp2_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 gp3_clk_src = {\n+\t.cmd_rcgr = 0x0a004,\n+\t.freq_tbl = ftbl_gp_clk_src,\n+\t.mnd_width = 8,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"gp3_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2_sleep_clk),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_lpass_axim_clk_src[] = {\n+\tF(133333334, P_GPLL0, 6, 0, 0),\n+\t{ }\n+};\n+\n+struct clk_rcg2 lpass_axim_clk_src = {\n+\t.cmd_rcgr = 0x2e028,\n+\t.freq_tbl = ftbl_lpass_axim_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"lpass_axim_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_lpass_sway_clk_src[] = {\n+\tF(66666667, P_GPLL0, 12, 0, 0),\n+\t{ }\n+};\n+\n+struct clk_rcg2 lpass_sway_clk_src = {\n+\t.cmd_rcgr = 0x2e040,\n+\t.freq_tbl = ftbl_lpass_sway_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"lpass_sway_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_pcie0_aux_clk_src[] = {\n+\tF(2000000, P_XO, 12, 0, 0),\n+};\n+\n+static struct clk_rcg2 pcie0_aux_clk_src = {\n+\t.cmd_rcgr = 0x75020,\n+\t.freq_tbl = ftbl_pcie0_aux_clk_src,\n+\t.mnd_width = 16,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"pcie0_aux_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_core_pi_sleep_clk,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_pcie0_axi_clk_src[] = {\n+\tF(240000000, P_GPLL4, 5, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 pcie0_axi_clk_src = {\n+\t.cmd_rcgr = 0x75050,\n+\t.freq_tbl = ftbl_pcie0_axi_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll4_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"pcie0_axi_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll4,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 pcie1_aux_clk_src = {\n+\t.cmd_rcgr = 0x76020,\n+\t.freq_tbl = ftbl_pcie0_aux_clk_src,\n+\t.mnd_width = 16,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"pcie1_aux_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_core_pi_sleep_clk,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 pcie1_axi_clk_src = {\n+\t.cmd_rcgr = 0x76050,\n+\t.freq_tbl = ftbl_gp_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"pcie1_axi_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_regmap_mux pcie0_pipe_clk_src = {\n+\t.reg = 0x7501c,\n+\t.shift = 8,\n+\t.width = 2,\n+\t.parent_map = gcc_pcie20_phy0_pipe_clk_xo_map,\n+\t.clkr = {\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"pcie0_pipe_clk_src\",\n+\t\t\t.parent_data = gcc_pcie20_phy0_pipe_clk_xo,\n+\t\t\t.num_parents = ARRAY_SIZE(gcc_pcie20_phy0_pipe_clk_xo),\n+\t\t\t.ops = &clk_regmap_mux_closest_ops,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_regmap_mux pcie1_pipe_clk_src = {\n+\t.reg = 0x7601c,\n+\t.shift = 8,\n+\t.width = 2,\n+\t.parent_map = gcc_pcie20_phy1_pipe_clk_xo_map, .clkr = {\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"pcie1_pipe_clk_src\",\n+\t\t\t.parent_data = gcc_pcie20_phy1_pipe_clk_xo,\n+\t\t\t.num_parents = ARRAY_SIZE(gcc_pcie20_phy1_pipe_clk_xo),\n+\t\t\t.ops = &clk_regmap_mux_closest_ops,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {\n+\tF(100000000, P_GPLL0, 8, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 pcnoc_bfdcd_clk_src = {\n+\t.cmd_rcgr = 0x27000,\n+\t.freq_tbl = ftbl_pcnoc_bfdcd_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"pcnoc_bfdcd_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_fixed_factor pcnoc_clk_src = {\n+\t.mult = 1,\n+\t.div = 1,\n+\t.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"pcnoc_clk_src\",\n+\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t&pcnoc_bfdcd_clk_src.clkr.hw,\n+\t\t},\n+\t\t.num_parents = 1,\n+\t\t.ops = &clk_fixed_factor_ops,\n+\t\t.flags = CLK_SET_RATE_PARENT,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_qdss_at_clk_src[] = {\n+\tF(240000000, P_GPLL4, 5, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 qdss_at_clk_src = {\n+\t.cmd_rcgr = 0x2900c,\n+\t.freq_tbl = ftbl_qdss_at_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"qdss_at_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_qdss_stm_clk_src[] = {\n+\tF(200000000, P_GPLL0, 4, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 qdss_stm_clk_src = {\n+\t.cmd_rcgr = 0x2902c,\n+\t.freq_tbl = ftbl_qdss_stm_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"qdss_stm_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = {\n+\tF(266666667, P_GPLL0, 3, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 qdss_traceclkin_clk_src = {\n+\t.cmd_rcgr = 0x29048,\n+\t.freq_tbl = ftbl_qdss_traceclkin_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"qdss_traceclkin_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = {\n+\tF(600000000, P_GPLL4, 2, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 qdss_tsctr_clk_src = {\n+\t.cmd_rcgr = 0x29064,\n+\t.freq_tbl = ftbl_qdss_tsctr_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map1,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"qdss_tsctr_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_fixed_factor qdss_tsctr_div2_clk_src = {\n+\t.mult = 1,\n+\t.div = 2,\n+\t.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"qdss_tsctr_div2_clk_src\",\n+\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t&qdss_tsctr_clk_src.clkr.hw,\n+\t\t},\n+\t\t.num_parents = 1,\n+\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t.ops = &clk_fixed_factor_ops,\n+\t},\n+};\n+\n+static struct clk_fixed_factor qdss_dap_sync_clk_src = {\n+\t.mult = 1,\n+\t.div = 4,\n+\t.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"qdss_dap_sync_clk_src\",\n+\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t&qdss_tsctr_clk_src.clkr.hw,\n+\t\t},\n+\t\t.num_parents = 1,\n+\t\t.ops = &clk_fixed_factor_ops,\n+\t},\n+};\n+\n+static struct clk_fixed_factor eud_at_clk_src = {\n+\t.mult = 1,\n+\t.div = 6,\n+\t.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"eud_at_clk_src\",\n+\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t&qdss_at_clk_src.clkr.hw,\n+\t\t},\n+\t\t.num_parents = 1,\n+\t\t.ops = &clk_fixed_factor_ops,\n+\t\t.flags = CLK_SET_RATE_PARENT,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_qpic_io_macro_clk_src[] = {\n+\tF(24000000, P_XO, 1, 0, 0),\n+\tF(100000000, P_GPLL0, 8, 0, 0),\n+\tF(200000000, P_GPLL0, 4, 0, 0),\n+\tF(320000000, P_GPLL0, 2.5, 0, 0),\n+};\n+\n+static struct clk_rcg2 qpic_io_macro_clk_src = {\n+\t.cmd_rcgr = 0x57010,\n+\t.freq_tbl = ftbl_qpic_io_macro_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"qpic_io_macro_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_sdcc1_apps_clk_src[] = {\n+\tF(143713, P_XO, 1, 1, 167),\n+\tF(400000, P_XO, 1, 1, 60),\n+\tF(24000000, P_XO, 1, 0, 0),\n+\tF(48000000, P_GPLL2, 12, 1, 2),\n+\tF(96000000, P_GPLL2, 12, 0, 0),\n+\tF(177777778, P_GPLL0, 1, 2, 9),\n+\tF(192000000, P_GPLL2, 6, 0, 0),\n+\tF(200000000, P_GPLL0, 4, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 sdcc1_apps_clk_src = {\n+\t.cmd_rcgr = 0x42004,\n+\t.freq_tbl = ftbl_sdcc1_apps_clk_src,\n+\t.mnd_width = 8,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"sdcc1_apps_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_floor_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {\n+\tF(266666667, P_GPLL0, 3, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 system_noc_bfdcd_clk_src = {\n+\t.cmd_rcgr = 0x26004,\n+\t.freq_tbl = ftbl_system_noc_bfdcd_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"system_noc_bfdcd_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_fixed_factor system_noc_clk_src = {\n+\t.mult = 1,\n+\t.div = 1,\n+\t.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"system_noc_clk_src\",\n+\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t&system_noc_bfdcd_clk_src.clkr.hw,\n+\t\t},\n+\t\t.num_parents = 1,\n+\t\t.ops = &clk_fixed_factor_ops,\n+\t\t.flags = CLK_SET_RATE_PARENT,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_apss_axi_clk_src[] = {\n+\tF(400000000, P_GPLL0, 2, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 ubi0_axi_clk_src = {\n+\t.cmd_rcgr = 0x68088,\n+\t.freq_tbl = ftbl_apss_axi_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"ubi0_axi_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t\t.flags = CLK_SET_RATE_PARENT,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_ubi0_core_clk_src[] = {\n+\tF(850000000, P_UBI32_PLL, 1, 0, 0),\n+\tF(1000000000, P_UBI32_PLL, 1, 0, 0),\n+};\n+\n+static struct clk_rcg2 ubi0_core_clk_src = {\n+\t.cmd_rcgr = 0x68100,\n+\t.freq_tbl = ftbl_ubi0_core_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_ubi32_gpll0_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"ubi0_core_clk_src\",\n+\t\t.parent_data = gcc_xo_ubi32_gpll0,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_ubi32_gpll0),\n+\t\t.ops = &clk_rcg2_ops,\n+\t\t.flags = CLK_SET_RATE_PARENT,\n+\t},\n+};\n+\n+static struct clk_rcg2 usb0_aux_clk_src = {\n+\t.cmd_rcgr = 0x3e05c,\n+\t.freq_tbl = ftbl_pcie0_aux_clk_src,\n+\t.mnd_width = 16,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"usb0_aux_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_core_pi_sleep_clk,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_usb0_lfps_clk_src[] = {\n+\tF(25000000, P_GPLL0, 16, 1, 2),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 usb0_lfps_clk_src = {\n+\t.cmd_rcgr = 0x3e090,\n+\t.freq_tbl = ftbl_usb0_lfps_clk_src,\n+\t.mnd_width = 8,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"usb0_lfps_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 usb0_master_clk_src = {\n+\t.cmd_rcgr = 0x3e00c,\n+\t.freq_tbl = ftbl_gp_clk_src,\n+\t.mnd_width = 8,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"usb0_master_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_out_main_div2_gpll0,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_usb0_mock_utmi_clk_src[] = {\n+\tF(60000000, P_GPLL4, 10, 1, 2),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 usb0_mock_utmi_clk_src = {\n+\t.cmd_rcgr = 0x3e020,\n+\t.freq_tbl = ftbl_usb0_mock_utmi_clk_src,\n+\t.mnd_width = 8,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map2,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"usb0_mock_utmi_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_regmap_mux usb0_pipe_clk_src = {\n+\t.reg = 0x3e048,\n+\t.shift = 8,\n+\t.width = 2,\n+\t.parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,\n+\t.clkr = {\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"usb0_pipe_clk_src\",\n+\t\t\t.parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,\n+\t\t\t.num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo),\n+\t\t\t.ops = &clk_regmap_mux_closest_ops,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_q6_axi_clk_src[] = {\n+\tF(400000000, P_GPLL0, 2, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 q6_axi_clk_src = {\n+\t.cmd_rcgr = 0x59120,\n+\t.freq_tbl = ftbl_q6_axi_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll2_gpll4_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"q6_axi_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll2_gpll4,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = {\n+\tF(133333333, P_GPLL0, 6, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 wcss_ahb_clk_src = {\n+\t.cmd_rcgr = 0x59020,\n+\t.freq_tbl = ftbl_wcss_ahb_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"wcss_ahb_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_sleep_clk_src = {\n+\t.halt_reg = 0x30000,\n+\t.clkr = {\n+\t\t.enable_reg = 0x30000,\n+\t\t.enable_mask = BIT(1),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_sleep_clk_src\",\n+\t\t\t.parent_data = gcc_sleep_clk_data,\n+\t\t\t.num_parents = ARRAY_SIZE(gcc_sleep_clk_data),\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_xo_clk_src = {\n+\t.halt_reg = 0x30018,\n+\t.clkr = {\n+\t\t.enable_reg = 0x30018,\n+\t\t.enable_mask = BIT(1),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_xo_clk_src\",\n+\t\t\t.parent_data = gcc_xo_data,\n+\t\t\t.num_parents = ARRAY_SIZE(gcc_xo_data),\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_xo_clk = {\n+\t.halt_reg = 0x30030,\n+\t.clkr = {\n+\t\t.enable_reg = 0x30030,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_xo_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gcc_xo_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_adss_pwm_clk = {\n+\t.halt_reg = 0x1f020,\n+\t.clkr = {\n+\t\t.enable_reg = 0x1f020,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_adss_pwm_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&adss_pwm_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_ahb_clk = {\n+\t.halt_reg = 0x01008,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x0b004,\n+\t\t.enable_mask = BIT(10),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {\n+\t.halt_reg = 0x02008,\n+\t.clkr = {\n+\t\t.enable_reg = 0x02008,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_qup1_i2c_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&blsp1_qup1_i2c_apps_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {\n+\t.halt_reg = 0x02004,\n+\t.clkr = {\n+\t\t.enable_reg = 0x02004,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_qup1_spi_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&blsp1_qup1_spi_apps_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {\n+\t.halt_reg = 0x03010,\n+\t.clkr = {\n+\t\t.enable_reg = 0x03010,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_qup2_i2c_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&blsp1_qup2_i2c_apps_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {\n+\t.halt_reg = 0x0300c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x0300c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_qup2_spi_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&blsp1_qup2_spi_apps_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {\n+\t.halt_reg = 0x04010,\n+\t.clkr = {\n+\t\t.enable_reg = 0x04010,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_qup3_i2c_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&blsp1_qup3_i2c_apps_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {\n+\t.halt_reg = 0x0400c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x0400c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_qup3_spi_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&blsp1_qup3_spi_apps_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_uart1_apps_clk = {\n+\t.halt_reg = 0x0203c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x0203c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_uart1_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&blsp1_uart1_apps_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_uart2_apps_clk = {\n+\t.halt_reg = 0x0302c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x0302c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_uart2_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&blsp1_uart2_apps_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_btss_lpo_clk = {\n+\t.halt_reg = 0x1c004,\n+\t.clkr = {\n+\t\t.enable_reg = 0x1c004,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_btss_lpo_clk\",\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_cmn_blk_ahb_clk = {\n+\t.halt_reg = 0x56308,\n+\t.clkr = {\n+\t\t.enable_reg = 0x56308,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_cmn_blk_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_cmn_blk_sys_clk = {\n+\t.halt_reg = 0x5630c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x5630c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_cmn_blk_sys_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gcc_xo_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_crypto_ahb_clk = {\n+\t.halt_reg = 0x16024,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x0b004,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_crypto_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_crypto_axi_clk = {\n+\t.halt_reg = 0x16020,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x0b004,\n+\t\t.enable_mask = BIT(1),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_crypto_axi_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_crypto_clk = {\n+\t.halt_reg = 0x1601c,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x0b004,\n+\t\t.enable_mask = BIT(2),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_crypto_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&crypto_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_dcc_clk = {\n+\t.halt_reg = 0x77004,\n+\t.clkr = {\n+\t\t.enable_reg = 0x77004,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_dcc_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_gephy_rx_clk = {\n+\t.halt_reg = 0x56010,\n+\t.halt_check = BRANCH_HALT_DELAY,\n+\t.clkr = {\n+\t\t.enable_reg = 0x56010,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_gephy_rx_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gmac0_rx_div_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_gephy_tx_clk = {\n+\t.halt_reg = 0x56014,\n+\t.halt_check = BRANCH_HALT_DELAY,\n+\t.clkr = {\n+\t\t.enable_reg = 0x56014,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_gephy_tx_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gmac0_tx_div_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_gmac0_cfg_clk = {\n+\t.halt_reg = 0x68304,\n+\t.clkr = {\n+\t\t.enable_reg = 0x68304,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_gmac0_cfg_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gmac_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_gmac0_ptp_clk = {\n+\t.halt_reg = 0x68300,\n+\t.clkr = {\n+\t\t.enable_reg = 0x68300,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_gmac0_ptp_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gmac_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_gmac0_rx_clk = {\n+\t.halt_reg = 0x68240,\n+\t.clkr = {\n+\t\t.enable_reg = 0x68240,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_gmac0_rx_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gmac0_rx_div_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_gmac0_sys_clk = {\n+\t.halt_reg = 0x68190,\n+\t.halt_check = BRANCH_HALT_DELAY,\n+\t.halt_bit = 31,\n+\t.clkr = {\n+\t\t.enable_reg = 0x683190,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_gmac0_sys_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gmac_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_gmac0_tx_clk = {\n+\t.halt_reg = 0x68244,\n+\t.clkr = {\n+\t\t.enable_reg = 0x68244,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_gmac0_tx_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gmac0_tx_div_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_gmac1_cfg_clk = {\n+\t.halt_reg = 0x68324,\n+\t.clkr = {\n+\t\t.enable_reg = 0x68324,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_gmac1_cfg_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gmac_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_gmac1_ptp_clk = {\n+\t.halt_reg = 0x68320,\n+\t.clkr = {\n+\t\t.enable_reg = 0x68320,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_gmac1_ptp_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gmac_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_gmac1_rx_clk = {\n+\t.halt_reg = 0x68248,\n+\t.clkr = {\n+\t\t.enable_reg = 0x68248,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_gmac1_rx_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gmac1_rx_div_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_gmac1_sys_clk = {\n+\t.halt_reg = 0x68310,\n+\t.clkr = {\n+\t\t.enable_reg = 0x68310,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_gmac1_sys_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gmac_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_gmac1_tx_clk = {\n+\t.halt_reg = 0x6824c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x6824c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_gmac1_tx_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gmac1_tx_div_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_gp1_clk = {\n+\t.halt_reg = 0x08000,\n+\t.clkr = {\n+\t\t.enable_reg = 0x08000,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_gp1_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gp1_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_gp2_clk = {\n+\t.halt_reg = 0x09000,\n+\t.clkr = {\n+\t\t.enable_reg = 0x09000,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_gp2_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gp2_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_gp3_clk = {\n+\t.halt_reg = 0x0a000,\n+\t.clkr = {\n+\t\t.enable_reg = 0x0a000,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_gp3_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gp3_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_lpass_core_axim_clk = {\n+\t.halt_reg = 0x2e048,\n+\t.halt_check = BRANCH_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2e048,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_lpass_core_axim_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&lpass_axim_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_lpass_sway_clk = {\n+\t.halt_reg = 0x2e04c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2e04c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_lpass_sway_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&lpass_sway_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_mdio0_ahb_clk = {\n+\t.halt_reg = 0x58004,\n+\t.clkr = {\n+\t\t.enable_reg = 0x58004,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_mdioi0_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_mdio1_ahb_clk = {\n+\t.halt_reg = 0x58014,\n+\t.clkr = {\n+\t\t.enable_reg = 0x58014,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_mdio1_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie0_ahb_clk = {\n+\t.halt_reg = 0x75010,\n+\t.clkr = {\n+\t\t.enable_reg = 0x75010,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie0_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie0_aux_clk = {\n+\t.halt_reg = 0x75014,\n+\t.clkr = {\n+\t\t.enable_reg = 0x75014,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie0_aux_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie0_aux_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie0_axi_m_clk = {\n+\t.halt_reg = 0x75008,\n+\t.clkr = {\n+\t\t.enable_reg = 0x75008,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie0_axi_m_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie0_axi_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {\n+\t.halt_reg = 0x75048,\n+\t.clkr = {\n+\t\t.enable_reg = 0x75048,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie0_axi_s_bridge_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie0_axi_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie0_axi_s_clk = {\n+\t.halt_reg = 0x7500c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x7500c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie0_axi_s_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie0_axi_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie0_pipe_clk = {\n+\t.halt_reg = 0x75018,\n+\t.halt_check = BRANCH_HALT_DELAY,\n+\t.halt_bit = 31,\n+\t.clkr = {\n+\t\t.enable_reg = 0x75018,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie0_pipe_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie0_pipe_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie1_ahb_clk = {\n+\t.halt_reg = 0x76010,\n+\t.clkr = {\n+\t\t.enable_reg = 0x76010,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie1_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie1_aux_clk = {\n+\t.halt_reg = 0x76014,\n+\t.clkr = {\n+\t\t.enable_reg = 0x76014,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie1_aux_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie1_aux_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie1_axi_m_clk = {\n+\t.halt_reg = 0x76008,\n+\t.clkr = {\n+\t\t.enable_reg = 0x76008,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie1_axi_m_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie1_axi_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie1_axi_s_bridge_clk = {\n+\t.halt_reg = 0x76048,\n+\t.clkr = {\n+\t\t.enable_reg = 0x76048,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie1_axi_s_bridge_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie1_axi_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie1_axi_s_clk = {\n+\t.halt_reg = 0x7600c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x7600c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie1_axi_s_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie1_axi_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie1_pipe_clk = {\n+\t.halt_reg = 8,\n+\t.halt_check = BRANCH_HALT_DELAY,\n+\t.halt_bit = 31,\n+\t.clkr = {\n+\t\t.enable_reg = 0x76018,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie1_pipe_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie1_pipe_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_prng_ahb_clk = {\n+\t.halt_reg = 0x13004,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x0b004,\n+\t\t.enable_mask = BIT(8),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_prng_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_q6_ahb_clk = {\n+\t.halt_reg = 0x59138,\n+\t.clkr = {\n+\t\t.enable_reg = 0x59138,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_q6_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&wcss_ahb_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_q6_ahb_s_clk = {\n+\t.halt_reg = 0x5914c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x5914c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_q6_ahb_s_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&wcss_ahb_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_q6_axim_clk = {\n+\t.halt_reg = 0x5913c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x5913c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_q6_axim_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&q6_axi_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_q6_axim2_clk = {\n+\t.halt_reg = 0x59150,\n+\t.clkr = {\n+\t\t.enable_reg = 0x59150,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_q6_axim2_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&q6_axi_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_q6_axis_clk = {\n+\t.halt_reg = 0x59154,\n+\t.clkr = {\n+\t\t.enable_reg = 0x59154,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_q6_axis_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&system_noc_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_q6_tsctr_1to2_clk = {\n+\t.halt_reg = 0x59148,\n+\t.clkr = {\n+\t\t.enable_reg = 0x59148,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_q6_tsctr_1to2_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_tsctr_div2_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_q6ss_atbm_clk = {\n+\t.halt_reg = 0x59144,\n+\t.clkr = {\n+\t\t.enable_reg = 0x59144,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_q6ss_atbm_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_at_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_q6ss_pclkdbg_clk = {\n+\t.halt_reg = 0x59140,\n+\t.clkr = {\n+\t\t.enable_reg = 0x59140,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_q6ss_pclkdbg_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_dap_sync_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_q6ss_trig_clk = {\n+\t.halt_reg = 0x59128,\n+\t.clkr = {\n+\t\t.enable_reg = 0x59128,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_q6ss_trig_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_dap_sync_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_qdss_at_clk = {\n+\t.halt_reg = 0x29024,\n+\t.clkr = {\n+\t\t.enable_reg = 0x29024,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_qdss_at_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_at_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_qdss_dap_clk = {\n+\t.halt_reg = 0x29084,\n+\t.clkr = {\n+\t\t.enable_reg = 0x29084,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_qdss_dap_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_tsctr_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_qdss_cfg_ahb_clk = {\n+\t.halt_reg = 0x29008,\n+\t.clkr = {\n+\t\t.enable_reg = 0x29008,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_qdss_cfg_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_qdss_dap_ahb_clk = {\n+\t.halt_reg = 0x29004,\n+\t.clkr = {\n+\t\t.enable_reg = 0x29004,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_qdss_dap_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_qdss_etr_usb_clk = {\n+\t.halt_reg = 0x29028,\n+\t.clkr = {\n+\t\t.enable_reg = 0x29028,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_qdss_etr_usb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&system_noc_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_qdss_eud_at_clk = {\n+\t.halt_reg = 0x29020,\n+\t.clkr = {\n+\t\t.enable_reg = 0x29020,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_qdss_eud_at_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&eud_at_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_qdss_stm_clk = {\n+\t.halt_reg = 0x29044,\n+\t.clkr = {\n+\t\t.enable_reg = 0x29044,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_qdss_stm_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_stm_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_qdss_traceclkin_clk = {\n+\t.halt_reg = 0x29060,\n+\t.clkr = {\n+\t\t.enable_reg = 0x29060,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_qdss_traceclkin_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_traceclkin_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_qdss_tsctr_div8_clk = {\n+\t.halt_reg = 0x2908c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2908c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_qdss_tsctr_div8_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_tsctr_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_qpic_ahb_clk = {\n+\t.halt_reg = 0x57024,\n+\t.clkr = {\n+\t\t.enable_reg = 0x57024,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_qpic_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_qpic_clk = {\n+\t.halt_reg = 0x57020,\n+\t.clkr = {\n+\t\t.enable_reg = 0x57020,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_qpic_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_qpic_io_macro_clk = {\n+\t.halt_reg = 0x5701c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x5701c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_qpic_io_macro_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qpic_io_macro_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_sdcc1_ahb_clk = {\n+\t.halt_reg = 0x4201c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x4201c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_sdcc1_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_sdcc1_apps_clk = {\n+\t.halt_reg = 0x42018,\n+\t.clkr = {\n+\t\t.enable_reg = 0x42018,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_sdcc1_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&sdcc1_apps_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_snoc_gmac0_ahb_clk = {\n+\t.halt_reg = 0x260a0,\n+\t.clkr = {\n+\t\t.enable_reg = 0x260a0,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_snoc_gmac0_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gmac_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_snoc_gmac0_axi_clk = {\n+\t.halt_reg = 0x26084,\n+\t.clkr = {\n+\t\t.enable_reg = 0x26084,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_snoc_gmac0_axi_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gmac_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_snoc_gmac1_ahb_clk = {\n+\t.halt_reg = 0x260a4,\n+\t.clkr = {\n+\t\t.enable_reg = 0x260a4,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_snoc_gmac1_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gmac_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_snoc_gmac1_axi_clk = {\n+\t.halt_reg = 0x26088,\n+\t.clkr = {\n+\t\t.enable_reg = 0x26088,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_snoc_gmac1_axi_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gmac_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_snoc_lpass_axim_clk = {\n+\t.halt_reg = 0x26074,\n+\t.clkr = {\n+\t\t.enable_reg = 0x26074,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_snoc_lpass_axim_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&lpass_axim_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_snoc_lpass_sway_clk = {\n+\t.halt_reg = 0x26078,\n+\t.clkr = {\n+\t\t.enable_reg = 0x26078,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_snoc_lpass_sway_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&lpass_sway_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_snoc_ubi0_axi_clk = {\n+\t.halt_reg = 0x26094,\n+\t.clkr = {\n+\t\t.enable_reg = 0x26094,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_snoc_ubi0_axi_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&ubi0_axi_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_sys_noc_pcie0_axi_clk = {\n+\t.halt_reg = 0x26048,\n+\t.clkr = {\n+\t\t.enable_reg = 0x26048,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_sys_noc_pcie0_axi_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie0_axi_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_sys_noc_pcie1_axi_clk = {\n+\t.halt_reg = 0x2604c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2604c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_sys_noc_pcie1_axi_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie1_axi_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_sys_noc_qdss_stm_axi_clk = {\n+\t.halt_reg = 0x26024,\n+\t.clkr = {\n+\t\t.enable_reg = 0x26024,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_sys_noc_qdss_stm_axi_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_stm_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_sys_noc_usb0_axi_clk = {\n+\t.halt_reg = 0x26040,\n+\t.clkr = {\n+\t\t.enable_reg = 0x26040,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_sys_noc_usb0_axi_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&usb0_master_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_sys_noc_wcss_ahb_clk = {\n+\t.halt_reg = 0x26034,\n+\t.clkr = {\n+\t\t.enable_reg = 0x26034,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_sys_noc_wcss_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&wcss_ahb_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_ubi0_axi_clk = {\n+\t.halt_reg = 0x68200,\n+\t.halt_check = BRANCH_HALT_DELAY,\n+\t.clkr = {\n+\t\t.enable_reg = 0x68200,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_ubi0_axi_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&ubi0_axi_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_ubi0_cfg_clk = {\n+\t.halt_reg = 0x68160,\n+\t.halt_check = BRANCH_HALT_DELAY,\n+\t.clkr = {\n+\t\t.enable_reg = 0x68160,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_ubi0_cfg_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_ubi0_dbg_clk = {\n+\t.halt_reg = 0x68214,\n+\t.halt_check = BRANCH_HALT_DELAY,\n+\t.clkr = {\n+\t\t.enable_reg = 0x68214,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_ubi0_dbg_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_tsctr_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_ubi0_core_clk = {\n+\t.halt_reg = 0x68210,\n+\t.halt_check = BRANCH_HALT_DELAY,\n+\t.clkr = {\n+\t\t.enable_reg = 0x68210,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_ubi0_core_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&ubi0_core_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_ubi0_nc_axi_clk = {\n+\t.halt_reg = 0x68204,\n+\t.halt_check = BRANCH_HALT_DELAY,\n+\t.clkr = {\n+\t\t.enable_reg = 0x68204,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_ubi0_nc_axi_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&system_noc_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_ubi0_utcm_clk = {\n+\t.halt_reg = 0x68208,\n+\t.halt_check = BRANCH_HALT_DELAY,\n+\t.clkr = {\n+\t\t.enable_reg = 0x68208,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_ubi0_utcm_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&system_noc_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_uniphy_ahb_clk = {\n+\t.halt_reg = 0x56108,\n+\t.clkr = {\n+\t\t.enable_reg = 0x56108,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_uniphy_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_uniphy_rx_clk = {\n+\t.halt_reg = 0x56110,\n+\t.clkr = {\n+\t\t.enable_reg = 0x56110,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_uniphy_rx_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gmac1_rx_div_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_uniphy_tx_clk = {\n+\t.halt_reg = 0x56114,\n+\t.clkr = {\n+\t\t.enable_reg = 0x56114,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_uniphy_tx_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gmac1_tx_div_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_uniphy_sys_clk = {\n+\t.halt_reg = 0x5610c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x5610c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_uniphy_sys_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gcc_xo_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_usb0_aux_clk = {\n+\t.halt_reg = 0x3e044,\n+\t.clkr = {\n+\t\t.enable_reg = 0x3e044,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_usb0_aux_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&usb0_aux_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_usb0_eud_at_clk = {\n+\t.halt_reg = 0x3e04c,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x3e04c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_usb0_eud_at_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&eud_at_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_usb0_lfps_clk = {\n+\t.halt_reg = 0x3e050,\n+\t.clkr = {\n+\t\t.enable_reg = 0x3e050,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_usb0_lfps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&usb0_lfps_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_usb0_master_clk = {\n+\t.halt_reg = 0x3e000,\n+\t.clkr = {\n+\t\t.enable_reg = 0x3e000,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_usb0_master_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&usb0_master_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_usb0_mock_utmi_clk = {\n+\t.halt_reg = 0x3e008,\n+\t.clkr = {\n+\t\t.enable_reg = 0x3e008,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_usb0_mock_utmi_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&usb0_mock_utmi_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {\n+\t.halt_reg = 0x3e080,\n+\t.clkr = {\n+\t\t.enable_reg = 0x3e080,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_usb0_phy_cfg_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_usb0_sleep_clk = {\n+\t.halt_reg = 0x3e004,\n+\t.clkr = {\n+\t\t.enable_reg = 0x3e004,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_usb0_sleep_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gcc_sleep_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_usb0_pipe_clk = {\n+\t.halt_reg = 0x3e040,\n+\t.halt_check = BRANCH_HALT_DELAY,\n+\t.clkr = {\n+\t\t.enable_reg = 0x3e040,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_usb0_pipe_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&usb0_pipe_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_wcss_acmt_clk = {\n+\t.halt_reg = 0x59064,\n+\t.clkr = {\n+\t\t.enable_reg = 0x59064,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_wcss_acmt_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&wcss_ahb_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_wcss_ahb_s_clk = {\n+\t.halt_reg = 0x59034,\n+\t.clkr = {\n+\t\t.enable_reg = 0x59034,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_wcss_ahb_s_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&wcss_ahb_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_wcss_axi_m_clk = {\n+\t.halt_reg = 0x5903c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x5903c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_wcss_axi_m_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&system_noc_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_wcss_axi_s_clk = {\n+\t.halt_reg = 0x59068,\n+\t.clkr = {\n+\t\t.enable_reg = 0x59068,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_wi_s_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&system_noc_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_wcss_dbg_ifc_apb_bdg_clk = {\n+\t.halt_reg = 0x59050,\n+\t.clkr = {\n+\t\t.enable_reg = 0x59050,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_wcss_dbg_ifc_apb_bdg_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_dap_sync_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = {\n+\t.halt_reg = 0x59040,\n+\t.clkr = {\n+\t\t.enable_reg = 0x59040,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_wcss_dbg_ifc_apb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_dap_sync_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_wcss_dbg_ifc_atb_bdg_clk = {\n+\t.halt_reg = 0x59054,\n+\t.clkr = {\n+\t\t.enable_reg = 0x59054,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_wcss_dbg_ifc_atb_bdg_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_at_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = {\n+\t.halt_reg = 0x59044,\n+\t.clkr = {\n+\t\t.enable_reg = 0x59044,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_wcss_dbg_ifc_atb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_at_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_wcss_dbg_ifc_dapbus_bdg_clk = {\n+\t.halt_reg = 0x59060,\n+\t.clkr = {\n+\t\t.enable_reg = 0x59060,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_wcss_dbg_ifc_dapbus_bdg_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_dap_sync_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = {\n+\t.halt_reg = 0x5905c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x5905c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_wcss_dbg_ifc_dapbus_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_dap_sync_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_wcss_dbg_ifc_nts_bdg_clk = {\n+\t.halt_reg = 0x59058,\n+\t.clkr = {\n+\t\t.enable_reg = 0x59058,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_wcss_dbg_ifc_nts_bdg_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_tsctr_div2_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = {\n+\t.halt_reg = 0x59048,\n+\t.clkr = {\n+\t\t.enable_reg = 0x59048,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_wcss_dbg_ifc_nts_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_tsctr_div2_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_wcss_ecahb_clk = {\n+\t.halt_reg = 0x59038,\n+\t.clkr = {\n+\t\t.enable_reg = 0x59038,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_wcss_ecahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&wcss_ahb_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_hw *gcc_ipq5018_hws[] = {\n+\t&gpll0_out_main_div2.hw,\n+\t&pcnoc_clk_src.hw,\n+\t&system_noc_clk_src.hw,\n+\t&qdss_dap_sync_clk_src.hw,\n+\t&qdss_tsctr_div2_clk_src.hw,\n+\t&eud_at_clk_src.hw,\n+};\n+\n+static const struct alpha_pll_config ubi32_pll_config = {\n+\t.l = 0x29,\n+\t.alpha = 0xaaaaaaaa,\n+\t.alpha_hi = 0xaa,\n+\t.config_ctl_val = 0x4001075b,\n+\t.main_output_mask = BIT(0),\n+\t.aux_output_mask = BIT(1),\n+\t.alpha_en_mask = BIT(24),\n+\t.vco_val = 0x1,\n+\t.vco_mask = GENMASK(21, 20),\n+\t.test_ctl_val = 0x0,\n+\t.test_ctl_hi_val = 0x0,\n+};\n+\n+static struct clk_regmap *gcc_ipq5018_clks[] = {\n+\t[GPLL0_MAIN] = &gpll0_main.clkr,\n+\t[GPLL0] = &gpll0.clkr,\n+\t[GPLL2_MAIN] = &gpll2_main.clkr,\n+\t[GPLL2] = &gpll2.clkr,\n+\t[GPLL4_MAIN] = &gpll4_main.clkr,\n+\t[GPLL4] = &gpll4.clkr,\n+\t[UBI32_PLL_MAIN] = &ubi32_pll_main.clkr,\n+\t[UBI32_PLL] = &ubi32_pll.clkr,\n+\t[ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr,\n+\t[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,\n+\t[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,\n+\t[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,\n+\t[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,\n+\t[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,\n+\t[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,\n+\t[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,\n+\t[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,\n+\t[CRYPTO_CLK_SRC] = &crypto_clk_src.clkr,\n+\t[GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,\n+\t[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,\n+\t[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,\n+\t[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,\n+\t[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,\n+\t[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,\n+\t[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,\n+\t[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,\n+\t[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,\n+\t[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,\n+\t[GCC_BTSS_LPO_CLK] = &gcc_btss_lpo_clk.clkr,\n+\t[GCC_CMN_BLK_AHB_CLK] = &gcc_cmn_blk_ahb_clk.clkr,\n+\t[GCC_CMN_BLK_SYS_CLK] = &gcc_cmn_blk_sys_clk.clkr,\n+\t[GCC_CRYPTO_AHB_CLK] = &gcc_crypto_ahb_clk.clkr,\n+\t[GCC_CRYPTO_AXI_CLK] = &gcc_crypto_axi_clk.clkr,\n+\t[GCC_CRYPTO_CLK] = &gcc_crypto_clk.clkr,\n+\t[GCC_DCC_CLK] = &gcc_dcc_clk.clkr,\n+\t[GCC_GEPHY_RX_CLK] = &gcc_gephy_rx_clk.clkr,\n+\t[GCC_GEPHY_TX_CLK] = &gcc_gephy_tx_clk.clkr,\n+\t[GCC_GMAC0_CFG_CLK] = &gcc_gmac0_cfg_clk.clkr,\n+\t[GCC_GMAC0_PTP_CLK] = &gcc_gmac0_ptp_clk.clkr,\n+\t[GCC_GMAC0_RX_CLK] = &gcc_gmac0_rx_clk.clkr,\n+\t[GCC_GMAC0_SYS_CLK] = &gcc_gmac0_sys_clk.clkr,\n+\t[GCC_GMAC0_TX_CLK] = &gcc_gmac0_tx_clk.clkr,\n+\t[GCC_GMAC1_CFG_CLK] = &gcc_gmac1_cfg_clk.clkr,\n+\t[GCC_GMAC1_PTP_CLK] = &gcc_gmac1_ptp_clk.clkr,\n+\t[GCC_GMAC1_RX_CLK] = &gcc_gmac1_rx_clk.clkr,\n+\t[GCC_GMAC1_SYS_CLK] = &gcc_gmac1_sys_clk.clkr,\n+\t[GCC_GMAC1_TX_CLK] = &gcc_gmac1_tx_clk.clkr,\n+\t[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,\n+\t[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,\n+\t[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,\n+\t[GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr,\n+\t[GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,\n+\t[GCC_MDIO0_AHB_CLK] = &gcc_mdio0_ahb_clk.clkr,\n+\t[GCC_MDIO1_AHB_CLK] = &gcc_mdio1_ahb_clk.clkr,\n+\t[GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,\n+\t[GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,\n+\t[GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,\n+\t[GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,\n+\t[GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,\n+\t[GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,\n+\t[GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,\n+\t[GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,\n+\t[GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr,\n+\t[GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,\n+\t[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,\n+\t[GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr,\n+\t[GCC_Q6_AXIM2_CLK] = &gcc_q6_axim2_clk.clkr,\n+\t[GCC_Q6_AXIS_CLK] = &gcc_q6_axis_clk.clkr,\n+\t[GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr,\n+\t[GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr,\n+\t[GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr,\n+\t[GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr,\n+\t[GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr,\n+\t[GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr,\n+\t[GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,\n+\t[GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr,\n+\t[GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr,\n+\t[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,\n+\t[GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr,\n+\t[GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr,\n+\t[GCC_QDSS_STM_CLK] = &gcc_qdss_stm_clk.clkr,\n+\t[GCC_QDSS_TRACECLKIN_CLK] = &gcc_qdss_traceclkin_clk.clkr,\n+\t[GCC_QDSS_TSCTR_DIV8_CLK] = &gcc_qdss_tsctr_div8_clk.clkr,\n+\t[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,\n+\t[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,\n+\t[GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,\n+\t[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,\n+\t[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,\n+\t[GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,\n+\t[GCC_SNOC_GMAC0_AHB_CLK] = &gcc_snoc_gmac0_ahb_clk.clkr,\n+\t[GCC_SNOC_GMAC0_AXI_CLK] = &gcc_snoc_gmac0_axi_clk.clkr,\n+\t[GCC_SNOC_GMAC1_AHB_CLK] = &gcc_snoc_gmac1_ahb_clk.clkr,\n+\t[GCC_SNOC_GMAC1_AXI_CLK] = &gcc_snoc_gmac1_axi_clk.clkr,\n+\t[GCC_SNOC_LPASS_AXIM_CLK] = &gcc_snoc_lpass_axim_clk.clkr,\n+\t[GCC_SNOC_LPASS_SWAY_CLK] = &gcc_snoc_lpass_sway_clk.clkr,\n+\t[GCC_SNOC_UBI0_AXI_CLK] = &gcc_snoc_ubi0_axi_clk.clkr,\n+\t[GCC_SYS_NOC_PCIE0_AXI_CLK] = &gcc_sys_noc_pcie0_axi_clk.clkr,\n+\t[GCC_SYS_NOC_PCIE1_AXI_CLK] = &gcc_sys_noc_pcie1_axi_clk.clkr,\n+\t[GCC_SYS_NOC_QDSS_STM_AXI_CLK] = &gcc_sys_noc_qdss_stm_axi_clk.clkr,\n+\t[GCC_SYS_NOC_USB0_AXI_CLK] = &gcc_sys_noc_usb0_axi_clk.clkr,\n+\t[GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr,\n+\t[GCC_UBI0_AXI_CLK] = &gcc_ubi0_axi_clk.clkr,\n+\t[GCC_UBI0_CFG_CLK] = &gcc_ubi0_cfg_clk.clkr,\n+\t[GCC_UBI0_CORE_CLK] = &gcc_ubi0_core_clk.clkr,\n+\t[GCC_UBI0_DBG_CLK] = &gcc_ubi0_dbg_clk.clkr,\n+\t[GCC_UBI0_NC_AXI_CLK] = &gcc_ubi0_nc_axi_clk.clkr,\n+\t[GCC_UBI0_UTCM_CLK] = &gcc_ubi0_utcm_clk.clkr,\n+\t[GCC_UNIPHY_AHB_CLK] = &gcc_uniphy_ahb_clk.clkr,\n+\t[GCC_UNIPHY_RX_CLK] = &gcc_uniphy_rx_clk.clkr,\n+\t[GCC_UNIPHY_SYS_CLK] = &gcc_uniphy_sys_clk.clkr,\n+\t[GCC_UNIPHY_TX_CLK] = &gcc_uniphy_tx_clk.clkr,\n+\t[GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,\n+\t[GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr,\n+\t[GCC_USB0_LFPS_CLK] = &gcc_usb0_lfps_clk.clkr,\n+\t[GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,\n+\t[GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,\n+\t[GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,\n+\t[GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,\n+\t[GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr,\n+\t[GCC_WCSS_AHB_S_CLK] = &gcc_wcss_ahb_s_clk.clkr,\n+\t[GCC_WCSS_AXI_M_CLK] = &gcc_wcss_axi_m_clk.clkr,\n+\t[GCC_WCSS_AXI_S_CLK] = &gcc_wcss_axi_s_clk.clkr,\n+\t[GCC_WCSS_DBG_IFC_APB_BDG_CLK] = &gcc_wcss_dbg_ifc_apb_bdg_clk.clkr,\n+\t[GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr,\n+\t[GCC_WCSS_DBG_IFC_ATB_BDG_CLK] = &gcc_wcss_dbg_ifc_atb_bdg_clk.clkr,\n+\t[GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr,\n+\t[GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK] = &gcc_wcss_dbg_ifc_dapbus_bdg_clk.clkr,\n+\t[GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr,\n+\t[GCC_WCSS_DBG_IFC_NTS_BDG_CLK] = &gcc_wcss_dbg_ifc_nts_bdg_clk.clkr,\n+\t[GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr,\n+\t[GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr,\n+\t[GCC_XO_CLK] = &gcc_xo_clk.clkr,\n+\t[GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,\n+\t[GMAC0_RX_CLK_SRC] = &gmac0_rx_clk_src.clkr,\n+\t[GMAC0_RX_DIV_CLK_SRC] = &gmac0_rx_div_clk_src.clkr,\n+\t[GMAC0_TX_CLK_SRC] = &gmac0_tx_clk_src.clkr,\n+\t[GMAC0_TX_DIV_CLK_SRC] = &gmac0_tx_div_clk_src.clkr,\n+\t[GMAC1_RX_CLK_SRC] = &gmac1_rx_clk_src.clkr,\n+\t[GMAC1_RX_DIV_CLK_SRC] = &gmac1_rx_div_clk_src.clkr,\n+\t[GMAC1_TX_CLK_SRC] = &gmac1_tx_clk_src.clkr,\n+\t[GMAC1_TX_DIV_CLK_SRC] = &gmac1_tx_div_clk_src.clkr,\n+\t[GMAC_CLK_SRC] = &gmac_clk_src.clkr,\n+\t[GP1_CLK_SRC] = &gp1_clk_src.clkr,\n+\t[GP2_CLK_SRC] = &gp2_clk_src.clkr,\n+\t[GP3_CLK_SRC] = &gp3_clk_src.clkr,\n+\t[LPASS_AXIM_CLK_SRC] = &lpass_axim_clk_src.clkr,\n+\t[LPASS_SWAY_CLK_SRC] = &lpass_sway_clk_src.clkr,\n+\t[PCIE0_AUX_CLK_SRC] = &pcie0_aux_clk_src.clkr,\n+\t[PCIE0_AXI_CLK_SRC] = &pcie0_axi_clk_src.clkr,\n+\t[PCIE1_AUX_CLK_SRC] = &pcie1_aux_clk_src.clkr,\n+\t[PCIE1_AXI_CLK_SRC] = &pcie1_axi_clk_src.clkr,\n+\t[PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,\n+\t[Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr,\n+\t[QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr,\n+\t[QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr,\n+\t[QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr,\n+\t[QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr,\n+\t[QPIC_IO_MACRO_CLK_SRC] = &qpic_io_macro_clk_src.clkr,\n+\t[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,\n+\t[SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,\n+\t[UBI0_AXI_CLK_SRC] = &ubi0_axi_clk_src.clkr,\n+\t[UBI0_CORE_CLK_SRC] = &ubi0_core_clk_src.clkr,\n+\t[USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,\n+\t[USB0_LFPS_CLK_SRC] = &usb0_lfps_clk_src.clkr,\n+\t[USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,\n+\t[USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,\n+\t[WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr,\n+\t[PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,\n+\t[PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,\n+\t[GCC_PCIE0_PIPE_CLK] = &gcc_pcie0_pipe_clk.clkr,\n+\t[GCC_PCIE1_PIPE_CLK] = &gcc_pcie1_pipe_clk.clkr,\n+\t[USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,\n+\t[GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,\n+};\n+\n+static const struct qcom_reset_map gcc_ipq5018_resets[] = {\n+\t[GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x78000, 0 },\n+\t[GCC_BLSP1_BCR] = { 0x01000, 0 },\n+\t[GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },\n+\t[GCC_BLSP1_QUP2_BCR] = { 0x03008, 0 },\n+\t[GCC_BLSP1_QUP3_BCR] = { 0x04008, 0 },\n+\t[GCC_BLSP1_UART1_BCR] = { 0x02038, 0 },\n+\t[GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },\n+\t[GCC_BOOT_ROM_BCR] = { 0x13008, 0 },\n+\t[GCC_BTSS_BCR] = { 0x1c000, 0 },\n+\t[GCC_CMN_BLK_BCR] = { 0x56300, 0 },\n+\t[GCC_CMN_LDO_BCR] = { 0x33000, 0 },\n+\t[GCC_CE_BCR] = { 0x33014, 0 },\n+\t[GCC_CRYPTO_BCR] = { 0x16000, 0 },\n+\t[GCC_DCC_BCR] = { 0x77000, 0 },\n+\t[GCC_DCD_BCR] = { 0x2a000, 0 },\n+\t[GCC_DDRSS_BCR] = { 0x1e000, 0 },\n+\t[GCC_EDPD_BCR] = { 0x3a000, 0 },\n+\t[GCC_GEPHY_BCR] = { 0x56000, 0 },\n+\t[GCC_GEPHY_MDC_SW_ARES] = { 0x56004, 0 },\n+\t[GCC_GEPHY_DSP_HW_ARES] = { 0x56004, 1 },\n+\t[GCC_GEPHY_RX_ARES] = { 0x56004, 2 },\n+\t[GCC_GEPHY_TX_ARES] = { 0x56004, 3 },\n+\t[GCC_GMAC0_BCR] = { 0x19000, 0 },\n+\t[GCC_GMAC0_CFG_ARES] = { 0x68428, 0 },\n+\t[GCC_GMAC0_SYS_ARES] = { 0x68428, 1 },\n+\t[GCC_GMAC1_BCR] = { 0x19100, 0 },\n+\t[GCC_GMAC1_CFG_ARES] = { 0x68438, 0 },\n+\t[GCC_GMAC1_SYS_ARES] = { 0x68438, 1 },\n+\t[GCC_IMEM_BCR] = { 0x0e000, 0 },\n+\t[GCC_LPASS_BCR] = { 0x2e000, 0 },\n+\t[GCC_MDIO0_BCR] = { 0x58000, 0 },\n+\t[GCC_MDIO1_BCR] = { 0x58010, 0 },\n+\t[GCC_MPM_BCR] = { 0x2c000, 0 },\n+\t[GCC_PCIE0_BCR] = { 0x75004, 0 },\n+\t[GCC_PCIE0_LINK_DOWN_BCR] = { 0x750a8, 0 },\n+\t[GCC_PCIE0_PHY_BCR] = { 0x75038, 0 },\n+\t[GCC_PCIE0PHY_PHY_BCR] = { 0x7503c, 0 },\n+\t[GCC_PCIE0_PIPE_ARES] = { 0x75040, 0 },\n+\t[GCC_PCIE0_SLEEP_ARES] = { 0x75040, 1 },\n+\t[GCC_PCIE0_CORE_STICKY_ARES] = { 0x75040, 2 },\n+\t[GCC_PCIE0_AXI_MASTER_ARES] = { 0x75040, 3 },\n+\t[GCC_PCIE0_AXI_SLAVE_ARES] = { 0x75040, 4 },\n+\t[GCC_PCIE0_AHB_ARES] = { 0x75040, 5 },\n+\t[GCC_PCIE0_AXI_MASTER_STICKY_ARES] = { 0x75040, 6 },\n+\t[GCC_PCIE0_AXI_SLAVE_STICKY_ARES] = { 0x75040, 7 },\n+\t[GCC_PCIE1_BCR] = { 0x76004, 0 },\n+\t[GCC_PCIE1_LINK_DOWN_BCR] = { 0x76044, 0 },\n+\t[GCC_PCIE1_PHY_BCR] = { 0x76038, 0 },\n+\t[GCC_PCIE1PHY_PHY_BCR] = { 0x7603c, 0 },\n+\t[GCC_PCIE1_PIPE_ARES] = { 0x76040, 0 },\n+\t[GCC_PCIE1_SLEEP_ARES] = { 0x76040, 1 },\n+\t[GCC_PCIE1_CORE_STICKY_ARES] = { 0x76040, 2 },\n+\t[GCC_PCIE1_AXI_MASTER_ARES] = { 0x76040, 3 },\n+\t[GCC_PCIE1_AXI_SLAVE_ARES] = { 0x76040, 4 },\n+\t[GCC_PCIE1_AHB_ARES] = { 0x76040, 5 },\n+\t[GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 },\n+\t[GCC_PCIE1_AXI_SLAVE_STICKY_ARES] = { 0x76040, 7 },\n+\t[GCC_PCNOC_BCR] = { 0x27018, 0 },\n+\t[GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x48000, 0 },\n+\t[GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x48008, 0 },\n+\t[GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x48010, 0 },\n+\t[GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x48018, 0 },\n+\t[GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x48020, 0 },\n+\t[GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x48028, 0 },\n+\t[GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x48030, 0 },\n+\t[GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x48038, 0 },\n+\t[GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x48040, 0 },\n+\t[GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x48048, 0 },\n+\t[GCC_PCNOC_BUS_TIMEOUT10_BCR] = { 0x48050, 0 },\n+\t[GCC_PCNOC_BUS_TIMEOUT11_BCR] = { 0x48058, 0 },\n+\t[GCC_PRNG_BCR] = { 0x13000, 0 },\n+\t[GCC_Q6SS_DBG_ARES] = { 0x59110, 0 },\n+\t[GCC_Q6_AHB_S_ARES] = { 0x59110, 1 },\n+\t[GCC_Q6_AHB_ARES] = { 0x59110, 2 },\n+\t[GCC_Q6_AXIM2_ARES] = { 0x59110, 3 },\n+\t[GCC_Q6_AXIM_ARES] = { 0x59110, 4 },\n+\t[GCC_Q6_AXIS_ARES] = { 0x59158, 0 },\n+\t[GCC_QDSS_BCR] = { 0x29000, 0 },\n+\t[GCC_QPIC_BCR] = { 0x57018, 0 },\n+\t[GCC_QUSB2_0_PHY_BCR] = { 0x41030, 0 },\n+\t[GCC_SDCC1_BCR] = { 0x42000, 0 },\n+\t[GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },\n+\t[GCC_SPDM_BCR] = { 0x2f000, 0 },\n+\t[GCC_SYSTEM_NOC_BCR] = { 0x26000, 0 },\n+\t[GCC_TCSR_BCR] = { 0x28000, 0 },\n+\t[GCC_TLMM_BCR] = { 0x34000, 0 },\n+\t[GCC_UBI0_AXI_ARES] = { 0x680},\n+\t[GCC_UBI0_AHB_ARES] = { 0x68010, 1 },\n+\t[GCC_UBI0_NC_AXI_ARES] = { 0x68010, 2 },\n+\t[GCC_UBI0_DBG_ARES] = { 0x68010, 3 },\n+\t[GCC_UBI0_UTCM_ARES] = { 0x68010, 6 },\n+\t[GCC_UBI0_CORE_ARES] = { 0x68010, 7 },\n+\t[GCC_UBI32_BCR] = { 0x19064, 0 },\n+\t[GCC_UNIPHY_BCR] = { 0x56100, 0 },\n+\t[GCC_UNIPHY_AHB_ARES] = { 0x56104, 0 },\n+\t[GCC_UNIPHY_SYS_ARES] = { 0x56104, 1 },\n+\t[GCC_UNIPHY_RX_ARES] = { 0x56104, 4 },\n+\t[GCC_UNIPHY_TX_ARES] = { 0x56104, 5 },\n+\t[GCC_UNIPHY_SOFT_RESET] = {0x56104, 0 },\n+\t[GCC_USB0_BCR] = { 0x3e070, 0 },\n+\t[GCC_USB0_PHY_BCR] = { 0x3e034, 0 },\n+\t[GCC_WCSS_BCR] = { 0x18000, 0 },\n+\t[GCC_WCSS_DBG_ARES] = { 0x59008, 0 },\n+\t[GCC_WCSS_ECAHB_ARES] = { 0x59008, 1 },\n+\t[GCC_WCSS_ACMT_ARES] = { 0x59008, 2 },\n+\t[GCC_WCSS_DBG_BDG_ARES] = { 0x59008, 3 },\n+\t[GCC_WCSS_AHB_S_ARES] = { 0x59008, 4 },\n+\t[GCC_WCSS_AXI_M_ARES] = { 0x59008, 5 },\n+\t[GCC_WCSS_AXI_S_ARES] = { 0x59008, 6 },\n+\t[GCC_WCSS_Q6_BCR] = { 0x18004, 0 },\n+\t[GCC_WCSSAON_RESET] = { 0x59010, 0},\n+\t[GCC_GEPHY_MISC_ARES] = { 0x56004, 0 },\n+};\n+\n+static const struct of_device_id gcc_ipq5018_match_table[] = {\n+\t{ .compatible = \"qcom,gcc-ipq5018\" },\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(of, gcc_ipq5018_match_table);\n+\n+static const struct regmap_config gcc_ipq5018_regmap_config = {\n+\t.reg_bits = 32,\n+\t.reg_stride = 4,\n+\t.val_bits = 32,\n+\t.max_register = 0x7fffc,\n+\t.fast_io = true,\n+};\n+\n+static const struct qcom_cc_desc gcc_ipq5018_desc = {\n+\t.config = &gcc_ipq5018_regmap_config,\n+\t.clks = gcc_ipq5018_clks,\n+\t.num_clks = ARRAY_SIZE(gcc_ipq5018_clks),\n+\t.resets = gcc_ipq5018_resets,\n+\t.num_resets = ARRAY_SIZE(gcc_ipq5018_resets),\n+\t.clk_hws = gcc_ipq5018_hws,\n+\t.num_clk_hws = ARRAY_SIZE(gcc_ipq5018_hws),\n+};\n+\n+static int gcc_ipq5018_probe(struct platform_device *pdev)\n+{\n+\tstruct regmap *regmap;\n+\tstruct qcom_cc_desc ipq5018_desc = gcc_ipq5018_desc;\n+\n+\tregmap = qcom_cc_map(pdev, &ipq5018_desc);\n+\tif (IS_ERR(regmap))\n+\t\treturn PTR_ERR(regmap);\n+\n+\tclk_alpha_pll_configure(&ubi32_pll_main, regmap, &ubi32_pll_config);\n+\n+\treturn qcom_cc_really_probe(pdev, &ipq5018_desc, regmap);\n+}\n+\n+static struct platform_driver gcc_ipq5018_driver = {\n+\t.probe = gcc_ipq5018_probe,\n+\t.driver = {\n+\t\t.name = \"qcom,gcc-ipq5018\",\n+\t\t.of_match_table = gcc_ipq5018_match_table,\n+\t},\n+};\n+\n+static int __init gcc_ipq5018_init(void)\n+{\n+\treturn platform_driver_register(&gcc_ipq5018_driver);\n+}\n+core_initcall(gcc_ipq5018_init);\n+\n+static void __exit gcc_ipq5018_exit(void)\n+{\n+\tplatform_driver_unregister(&gcc_ipq5018_driver);\n+}\n+module_exit(gcc_ipq5018_exit);\n+\n+MODULE_DESCRIPTION(\"Qualcomm Technologies, Inc. GCC IPQ5018 Driver\");\n+MODULE_LICENSE(\"GPL\");\n",
    "prefixes": [
        "V12",
        "2/6"
    ]
}