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GET /api/patches/1814125/?format=api
{ "id": 1814125, "url": "http://patchwork.ozlabs.org/api/patches/1814125/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1690533192-22220-2-git-send-email-quic_srichara@quicinc.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1690533192-22220-2-git-send-email-quic_srichara@quicinc.com>", "list_archive_url": null, "date": "2023-07-28T08:33:07", "name": "[V12,1/6] dt-bindings: clock: Add IPQ5018 clock and reset", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ac87bff55dcbd00014e950bf35ab915067e6107d", "submitter": { "id": 84297, "url": "http://patchwork.ozlabs.org/api/people/84297/?format=api", "name": "Sricharan Ramabadhran", "email": "quic_srichara@quicinc.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1690533192-22220-2-git-send-email-quic_srichara@quicinc.com/mbox/", "series": [ { "id": 366189, "url": "http://patchwork.ozlabs.org/api/series/366189/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=366189", "date": "2023-07-28T08:33:06", "name": "Add minimal boot support for IPQ5018", "version": 12, "mbox": "http://patchwork.ozlabs.org/series/366189/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1814125/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1814125/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-gpio-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) 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Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.1118.30; Fri, 28 Jul 2023 01:33:29 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=qcppdkim1;\n bh=Sr9wQx7IWcA3DvmVLuh3eqXLLR6NCvdszcrx9CuCKBo=;\n b=fb38ykE21LPhKFYMrn/Z/oOlQyYSb8v0gwRyvUj/xkrN1UW/U2sSxY46KBKhcAqSZl59\n 8VUsXJGDP4TjUv/xKC1w/UeXL1xKncgWRxWc6HIlUIkhkoyLdi4Qh9OVfR2kXPoyFSLT\n Z9Z+4PR92RZ9Adw/E5PCFGpIu6Zd/YXRtW9nnsiPmi/ccK6bfErY6ZVb4a8TpF6Wfm18\n dHOr48Y+kTwkAFfrzTYdqH8nsOgmLHPs2Ky4qCuMItaMoy4r2ly97iFyjf6KrcKcD7KH\n wie6PXU2w2A6T/Fy/eT3m2n3H1RuFk975Q22dzq0G1mAbVxR0m3MEGXzOiZmas5SnTjv Fg==", "From": "Sricharan Ramabadhran <quic_srichara@quicinc.com>", "To": "<agross@kernel.org>, <andersson@kernel.org>,\n <konrad.dybcio@linaro.org>, <robh+dt@kernel.org>,\n <krzysztof.kozlowski+dt@linaro.org>, <mturquette@baylibre.com>,\n <sboyd@kernel.org>, <ulf.hansson@linaro.org>,\n <linus.walleij@linaro.org>, <catalin.marinas@arm.com>,\n <will@kernel.org>, <p.zabel@pengutronix.de>,\n <linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>,\n <linux-kernel@vger.kernel.org>, <linux-mmc@vger.kernel.org>,\n <linux-gpio@vger.kernel.org>,\n <linux-arm-kernel@lists.infradead.org>, <robimarko@gmail.com>,\n <krzysztof.kozlowski@linaro.org>, <andy.shevchenko@gmail.com>", "CC": "<quic_srichara@quicinc.com>", "Subject": "[PATCH V12 1/6] dt-bindings: clock: Add IPQ5018 clock and reset", "Date": "Fri, 28 Jul 2023 14:03:07 +0530", "Message-ID": "<1690533192-22220-2-git-send-email-quic_srichara@quicinc.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1690533192-22220-1-git-send-email-quic_srichara@quicinc.com>", "References": "<1690533192-22220-1-git-send-email-quic_srichara@quicinc.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.80.80.8]", "X-ClientProxiedBy": "nasanex01a.na.qualcomm.com (10.52.223.231) To\n nalasex01c.na.qualcomm.com (10.47.97.35)", "X-QCInternal": "smtphost", "X-Proofpoint-Virus-Version": [ "vendor=nai engine=6200 definitions=5800\n signatures=585085", "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26\n definitions=2023-07-27_10,2023-07-26_01,2023-05-22_02" ], "X-Proofpoint-GUID": "RmBcDyG8WxrYjzb3-z8Fakxcpg9FLhgG", "X-Proofpoint-ORIG-GUID": "RmBcDyG8WxrYjzb3-z8Fakxcpg9FLhgG", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n spamscore=0\n lowpriorityscore=0 impostorscore=0 bulkscore=0 mlxlogscore=999 mlxscore=0\n clxscore=1015 priorityscore=1501 adultscore=0 phishscore=0 suspectscore=0\n malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1\n engine=8.12.0-2306200000 definitions=main-2307280077", "X-Spam-Status": "No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,\n SPF_PASS,T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham\n autolearn_force=no version=3.4.6", "X-Spam-Checker-Version": "SpamAssassin 3.4.6 (2021-04-09) on\n lindbergh.monkeyblade.net", "Precedence": "bulk", "List-ID": "<linux-gpio.vger.kernel.org>", "X-Mailing-List": "linux-gpio@vger.kernel.org" }, "content": "This patch adds support for the global clock controller found on\nthe IPQ5018 based devices.\n\nReviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>\nCo-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>\nSigned-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>\nSigned-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>\n---\n [v12] Fixed subject\n\n .../bindings/clock/qcom,ipq5018-gcc.yaml | 63 +++++++\n include/dt-bindings/clock/qcom,gcc-ipq5018.h | 183 +++++++++++++++++++++\n include/dt-bindings/reset/qcom,gcc-ipq5018.h | 122 ++++++++++++++\n 3 files changed, 368 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml\n create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq5018.h\n create mode 100644 include/dt-bindings/reset/qcom,gcc-ipq5018.h", "diff": "diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml\nnew file mode 100644\nindex 0000000..ef84a0c\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/clock/qcom,ipq5018-gcc.yaml\n@@ -0,0 +1,63 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/clock/qcom,ipq5018-gcc.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Qualcomm Global Clock & Reset Controller on IPQ5018\n+\n+maintainers:\n+ - Sricharan Ramabadhran <quic_srichara@quicinc.com>\n+\n+description: |\n+ Qualcomm global clock control module provides the clocks, resets and power\n+ domains on IPQ5018\n+\n+ See also::\n+ include/dt-bindings/clock/qcom,ipq5018-gcc.h\n+ include/dt-bindings/reset/qcom,ipq5018-gcc.h\n+\n+properties:\n+ compatible:\n+ const: qcom,gcc-ipq5018\n+\n+ clocks:\n+ items:\n+ - description: Board XO source\n+ - description: Sleep clock source\n+ - description: PCIE20 PHY0 pipe clock source\n+ - description: PCIE20 PHY1 pipe clock source\n+ - description: USB3 PHY pipe clock source\n+ - description: GEPHY RX clock source\n+ - description: GEPHY TX clock source\n+ - description: UNIPHY RX clock source\n+ - description: UNIPHY TX clk source\n+\n+required:\n+ - compatible\n+ - clocks\n+\n+allOf:\n+ - $ref: qcom,gcc.yaml#\n+\n+unevaluatedProperties: false\n+\n+examples:\n+ - |\n+ clock-controller@1800000 {\n+ compatible = \"qcom,gcc-ipq5018\";\n+ reg = <0x01800000 0x80000>;\n+ clocks = <&xo_board_clk>,\n+ <&sleep_clk>,\n+ <&pcie20_phy0_pipe_clk>,\n+ <&pcie20_phy1_pipe_clk>,\n+ <&usb3_phy0_pipe_clk>,\n+ <&gephy_rx_clk>,\n+ <&gephy_tx_clk>,\n+ <&uniphy_rx_clk>,\n+ <&uniphy_tx_clk>;\n+ #clock-cells = <1>;\n+ #reset-cells = <1>;\n+ #power-domain-cells = <1>;\n+ };\n+...\ndiff --git a/include/dt-bindings/clock/qcom,gcc-ipq5018.h b/include/dt-bindings/clock/qcom,gcc-ipq5018.h\nnew file mode 100644\nindex 0000000..f3de2fd\n--- /dev/null\n+++ b/include/dt-bindings/clock/qcom,gcc-ipq5018.h\n@@ -0,0 +1,183 @@\n+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */\n+/*\n+ * Copyright (c) 2023, The Linux Foundation. All rights reserved.\n+ */\n+\n+#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_5018_H\n+#define _DT_BINDINGS_CLOCK_IPQ_GCC_5018_H\n+\n+#define GPLL0_MAIN\t\t\t\t\t0\n+#define GPLL0\t\t\t\t\t\t1\n+#define GPLL2_MAIN\t\t\t\t\t2\n+#define GPLL2\t\t\t\t\t\t3\n+#define GPLL4_MAIN\t\t\t\t\t4\n+#define GPLL4\t\t\t\t\t\t5\n+#define UBI32_PLL_MAIN\t\t\t\t\t6\n+#define UBI32_PLL\t\t\t\t\t7\n+#define ADSS_PWM_CLK_SRC\t\t\t\t8\n+#define BLSP1_QUP1_I2C_APPS_CLK_SRC\t\t\t9\n+#define BLSP1_QUP1_SPI_APPS_CLK_SRC\t\t\t10\n+#define BLSP1_QUP2_I2C_APPS_CLK_SRC\t\t\t11\n+#define BLSP1_QUP2_SPI_APPS_CLK_SRC\t\t\t12\n+#define BLSP1_QUP3_I2C_APPS_CLK_SRC\t\t\t13\n+#define BLSP1_QUP3_SPI_APPS_CLK_SRC\t\t\t14\n+#define BLSP1_UART1_APPS_CLK_SRC\t\t\t15\n+#define BLSP1_UART2_APPS_CLK_SRC\t\t\t16\n+#define CRYPTO_CLK_SRC\t\t\t\t\t17\n+#define GCC_ADSS_PWM_CLK\t\t\t\t18\n+#define GCC_BLSP1_AHB_CLK\t\t\t\t19\n+#define GCC_BLSP1_QUP1_I2C_APPS_CLK\t\t\t20\n+#define GCC_BLSP1_QUP1_SPI_APPS_CLK\t\t\t21\n+#define GCC_BLSP1_QUP2_I2C_APPS_CLK\t\t\t22\n+#define GCC_BLSP1_QUP2_SPI_APPS_CLK\t\t\t23\n+#define GCC_BLSP1_QUP3_I2C_APPS_CLK\t\t\t24\n+#define GCC_BLSP1_QUP3_SPI_APPS_CLK\t\t\t25\n+#define GCC_BLSP1_UART1_APPS_CLK\t\t\t26\n+#define GCC_BLSP1_UART2_APPS_CLK\t\t\t27\n+#define GCC_BTSS_LPO_CLK\t\t\t\t28\n+#define GCC_CMN_BLK_AHB_CLK\t\t\t\t29\n+#define GCC_CMN_BLK_SYS_CLK\t\t\t\t30\n+#define GCC_CRYPTO_AHB_CLK\t\t\t\t31\n+#define GCC_CRYPTO_AXI_CLK\t\t\t\t32\n+#define GCC_CRYPTO_CLK\t\t\t\t\t33\n+#define GCC_CRYPTO_PPE_CLK\t\t\t\t34\n+#define GCC_DCC_CLK\t\t\t\t\t35\n+#define GCC_GEPHY_RX_CLK\t\t\t\t36\n+#define GCC_GEPHY_TX_CLK\t\t\t\t37\n+#define GCC_GMAC0_CFG_CLK\t\t\t\t38\n+#define GCC_GMAC0_PTP_CLK\t\t\t\t39\n+#define GCC_GMAC0_RX_CLK\t\t\t\t40\n+#define GCC_GMAC0_SYS_CLK\t\t\t\t41\n+#define GCC_GMAC0_TX_CLK\t\t\t\t42\n+#define GCC_GMAC1_CFG_CLK\t\t\t\t43\n+#define GCC_GMAC1_PTP_CLK\t\t\t\t44\n+#define GCC_GMAC1_RX_CLK\t\t\t\t45\n+#define GCC_GMAC1_SYS_CLK\t\t\t\t46\n+#define GCC_GMAC1_TX_CLK\t\t\t\t47\n+#define GCC_GP1_CLK\t\t\t\t\t48\n+#define GCC_GP2_CLK\t\t\t\t\t49\n+#define GCC_GP3_CLK\t\t\t\t\t50\n+#define GCC_LPASS_CORE_AXIM_CLK\t\t\t\t51\n+#define GCC_LPASS_SWAY_CLK\t\t\t\t52\n+#define GCC_MDIO0_AHB_CLK\t\t\t\t53\n+#define GCC_MDIO1_AHB_CLK\t\t\t\t54\n+#define GCC_PCIE0_AHB_CLK\t\t\t\t55\n+#define GCC_PCIE0_AUX_CLK\t\t\t\t56\n+#define GCC_PCIE0_AXI_M_CLK\t\t\t\t57\n+#define GCC_PCIE0_AXI_S_BRIDGE_CLK\t\t\t58\n+#define GCC_PCIE0_AXI_S_CLK\t\t\t\t59\n+#define GCC_PCIE0_PIPE_CLK\t\t\t\t60\n+#define GCC_PCIE1_AHB_CLK\t\t\t\t61\n+#define GCC_PCIE1_AUX_CLK\t\t\t\t62\n+#define GCC_PCIE1_AXI_M_CLK\t\t\t\t63\n+#define GCC_PCIE1_AXI_S_BRIDGE_CLK\t\t\t64\n+#define GCC_PCIE1_AXI_S_CLK\t\t\t\t65\n+#define GCC_PCIE1_PIPE_CLK\t\t\t\t66\n+#define GCC_PRNG_AHB_CLK\t\t\t\t67\n+#define GCC_Q6_AXIM_CLK\t\t\t\t\t68\n+#define GCC_Q6_AXIM2_CLK\t\t\t\t69\n+#define GCC_Q6_AXIS_CLK\t\t\t\t\t70\n+#define GCC_Q6_AHB_CLK\t\t\t\t\t71\n+#define GCC_Q6_AHB_S_CLK\t\t\t\t72\n+#define GCC_Q6_TSCTR_1TO2_CLK\t\t\t\t73\n+#define GCC_Q6SS_ATBM_CLK\t\t\t\t74\n+#define GCC_Q6SS_PCLKDBG_CLK\t\t\t\t75\n+#define GCC_Q6SS_TRIG_CLK\t\t\t\t76\n+#define GCC_QDSS_AT_CLK\t\t\t\t\t77\n+#define GCC_QDSS_CFG_AHB_CLK\t\t\t\t78\n+#define GCC_QDSS_DAP_AHB_CLK\t\t\t\t79\n+#define GCC_QDSS_DAP_CLK\t\t\t\t80\n+#define GCC_QDSS_ETR_USB_CLK\t\t\t\t81\n+#define GCC_QDSS_EUD_AT_CLK\t\t\t\t82\n+#define GCC_QDSS_STM_CLK\t\t\t\t83\n+#define GCC_QDSS_TRACECLKIN_CLK\t\t\t\t84\n+#define GCC_QDSS_TSCTR_DIV8_CLK\t\t\t\t85\n+#define GCC_QPIC_AHB_CLK\t\t\t\t86\n+#define GCC_QPIC_CLK\t\t\t\t\t87\n+#define GCC_QPIC_IO_MACRO_CLK\t\t\t\t88\n+#define GCC_SDCC1_AHB_CLK\t\t\t\t89\n+#define GCC_SDCC1_APPS_CLK\t\t\t\t90\n+#define GCC_SLEEP_CLK_SRC\t\t\t\t91\n+#define GCC_SNOC_GMAC0_AHB_CLK\t\t\t\t92\n+#define GCC_SNOC_GMAC0_AXI_CLK\t\t\t\t93\n+#define GCC_SNOC_GMAC1_AHB_CLK\t\t\t\t94\n+#define GCC_SNOC_GMAC1_AXI_CLK\t\t\t\t95\n+#define GCC_SNOC_LPASS_AXIM_CLK\t\t\t\t96\n+#define GCC_SNOC_LPASS_SWAY_CLK\t\t\t\t97\n+#define GCC_SNOC_UBI0_AXI_CLK\t\t\t\t98\n+#define GCC_SYS_NOC_PCIE0_AXI_CLK\t\t\t99\n+#define GCC_SYS_NOC_PCIE1_AXI_CLK\t\t\t100\n+#define GCC_SYS_NOC_QDSS_STM_AXI_CLK\t\t\t101\n+#define GCC_SYS_NOC_USB0_AXI_CLK\t\t\t102\n+#define GCC_SYS_NOC_WCSS_AHB_CLK\t\t\t103\n+#define GCC_UBI0_AXI_CLK\t\t\t\t104\n+#define GCC_UBI0_CFG_CLK\t\t\t\t105\n+#define GCC_UBI0_CORE_CLK\t\t\t\t106\n+#define GCC_UBI0_DBG_CLK\t\t\t\t107\n+#define GCC_UBI0_NC_AXI_CLK\t\t\t\t108\n+#define GCC_UBI0_UTCM_CLK\t\t\t\t109\n+#define GCC_UNIPHY_AHB_CLK\t\t\t\t110\n+#define GCC_UNIPHY_RX_CLK\t\t\t\t111\n+#define GCC_UNIPHY_SYS_CLK\t\t\t\t112\n+#define GCC_UNIPHY_TX_CLK\t\t\t\t113\n+#define GCC_USB0_AUX_CLK\t\t\t\t114\n+#define GCC_USB0_EUD_AT_CLK\t\t\t\t115\n+#define GCC_USB0_LFPS_CLK\t\t\t\t116\n+#define GCC_USB0_MASTER_CLK\t\t\t\t117\n+#define GCC_USB0_MOCK_UTMI_CLK\t\t\t\t118\n+#define GCC_USB0_PHY_CFG_AHB_CLK\t\t\t119\n+#define GCC_USB0_SLEEP_CLK\t\t\t\t120\n+#define GCC_WCSS_ACMT_CLK\t\t\t\t121\n+#define GCC_WCSS_AHB_S_CLK\t\t\t\t122\n+#define GCC_WCSS_AXI_M_CLK\t\t\t\t123\n+#define GCC_WCSS_AXI_S_CLK\t\t\t\t124\n+#define GCC_WCSS_DBG_IFC_APB_BDG_CLK\t\t\t125\n+#define GCC_WCSS_DBG_IFC_APB_CLK\t\t\t126\n+#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK\t\t\t127\n+#define GCC_WCSS_DBG_IFC_ATB_CLK\t\t\t128\n+#define GCC_WCSS_DBG_IFC_DAPBUS_BDG_CLK\t\t\t129\n+#define GCC_WCSS_DBG_IFC_DAPBUS_CLK\t\t\t130\n+#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK\t\t\t131\n+#define GCC_WCSS_DBG_IFC_NTS_CLK\t\t\t132\n+#define GCC_WCSS_ECAHB_CLK\t\t\t\t133\n+#define GCC_XO_CLK\t\t\t\t\t134\n+#define GCC_XO_CLK_SRC\t\t\t\t\t135\n+#define GMAC0_RX_CLK_SRC\t\t\t\t136\n+#define GMAC0_TX_CLK_SRC\t\t\t\t137\n+#define GMAC1_RX_CLK_SRC\t\t\t\t138\n+#define GMAC1_TX_CLK_SRC\t\t\t\t139\n+#define GMAC_CLK_SRC\t\t\t\t\t140\n+#define GP1_CLK_SRC\t\t\t\t\t141\n+#define GP2_CLK_SRC\t\t\t\t\t142\n+#define GP3_CLK_SRC\t\t\t\t\t143\n+#define LPASS_AXIM_CLK_SRC\t\t\t\t144\n+#define LPASS_SWAY_CLK_SRC\t\t\t\t145\n+#define PCIE0_AUX_CLK_SRC\t\t\t\t146\n+#define PCIE0_AXI_CLK_SRC\t\t\t\t147\n+#define PCIE1_AUX_CLK_SRC\t\t\t\t148\n+#define PCIE1_AXI_CLK_SRC\t\t\t\t149\n+#define PCNOC_BFDCD_CLK_SRC\t\t\t\t150\n+#define Q6_AXI_CLK_SRC\t\t\t\t\t151\n+#define QDSS_AT_CLK_SRC\t\t\t\t\t152\n+#define QDSS_STM_CLK_SRC\t\t\t\t153\n+#define QDSS_TSCTR_CLK_SRC\t\t\t\t154\n+#define QDSS_TRACECLKIN_CLK_SRC\t\t\t\t155\n+#define QPIC_IO_MACRO_CLK_SRC\t\t\t\t156\n+#define SDCC1_APPS_CLK_SRC\t\t\t\t157\n+#define SYSTEM_NOC_BFDCD_CLK_SRC\t\t\t158\n+#define UBI0_AXI_CLK_SRC\t\t\t\t159\n+#define UBI0_CORE_CLK_SRC\t\t\t\t160\n+#define USB0_AUX_CLK_SRC\t\t\t\t161\n+#define USB0_LFPS_CLK_SRC\t\t\t\t162\n+#define USB0_MASTER_CLK_SRC\t\t\t\t163\n+#define USB0_MOCK_UTMI_CLK_SRC\t\t\t\t164\n+#define WCSS_AHB_CLK_SRC\t\t\t\t165\n+#define PCIE0_PIPE_CLK_SRC\t\t\t\t166\n+#define PCIE1_PIPE_CLK_SRC\t\t\t\t167\n+#define USB0_PIPE_CLK_SRC\t\t\t\t168\n+#define GCC_USB0_PIPE_CLK\t\t\t\t169\n+#define GMAC0_RX_DIV_CLK_SRC\t\t\t\t170\n+#define GMAC0_TX_DIV_CLK_SRC\t\t\t\t171\n+#define GMAC1_RX_DIV_CLK_SRC\t\t\t\t172\n+#define GMAC1_TX_DIV_CLK_SRC\t\t\t\t173\n+#endif\ndiff --git a/include/dt-bindings/reset/qcom,gcc-ipq5018.h b/include/dt-bindings/reset/qcom,gcc-ipq5018.h\nnew file mode 100644\nindex 0000000..8f03c92\n--- /dev/null\n+++ b/include/dt-bindings/reset/qcom,gcc-ipq5018.h\n@@ -0,0 +1,122 @@\n+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */\n+/*\n+ * Copyright (c) 2023, The Linux Foundation. All rights reserved.\n+ */\n+\n+#ifndef _DT_BINDINGS_RESET_IPQ_GCC_5018_H\n+#define _DT_BINDINGS_RESET_IPQ_GCC_5018_H\n+\n+#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR\t0\n+#define GCC_BLSP1_BCR\t\t\t\t1\n+#define GCC_BLSP1_QUP1_BCR\t\t\t2\n+#define GCC_BLSP1_QUP2_BCR\t\t\t3\n+#define GCC_BLSP1_QUP3_BCR\t\t\t4\n+#define GCC_BLSP1_UART1_BCR\t\t\t5\n+#define GCC_BLSP1_UART2_BCR\t\t\t6\n+#define GCC_BOOT_ROM_BCR\t\t\t7\n+#define GCC_BTSS_BCR\t\t\t\t8\n+#define GCC_CMN_BLK_BCR\t\t\t\t9\n+#define GCC_CMN_LDO_BCR\t\t\t\t10\n+#define GCC_CE_BCR\t\t\t\t11\n+#define GCC_CRYPTO_BCR\t\t\t\t12\n+#define GCC_DCC_BCR\t\t\t\t13\n+#define GCC_DCD_BCR\t\t\t\t14\n+#define GCC_DDRSS_BCR\t\t\t\t15\n+#define GCC_EDPD_BCR\t\t\t\t16\n+#define GCC_GEPHY_BCR\t\t\t\t17\n+#define GCC_GEPHY_MDC_SW_ARES\t\t\t18\n+#define GCC_GEPHY_DSP_HW_ARES\t\t\t19\n+#define GCC_GEPHY_RX_ARES\t\t\t20\n+#define GCC_GEPHY_TX_ARES\t\t\t21\n+#define GCC_GMAC0_BCR\t\t\t\t22\n+#define GCC_GMAC0_CFG_ARES\t\t\t23\n+#define GCC_GMAC0_SYS_ARES\t\t\t24\n+#define GCC_GMAC1_BCR\t\t\t\t25\n+#define GCC_GMAC1_CFG_ARES\t\t\t26\n+#define GCC_GMAC1_SYS_ARES\t\t\t27\n+#define GCC_IMEM_BCR\t\t\t\t28\n+#define GCC_LPASS_BCR\t\t\t\t29\n+#define GCC_MDIO0_BCR\t\t\t\t30\n+#define GCC_MDIO1_BCR\t\t\t\t31\n+#define GCC_MPM_BCR\t\t\t\t32\n+#define GCC_PCIE0_BCR\t\t\t\t33\n+#define GCC_PCIE0_LINK_DOWN_BCR\t\t\t34\n+#define GCC_PCIE0_PHY_BCR\t\t\t35\n+#define GCC_PCIE0PHY_PHY_BCR\t\t\t36\n+#define GCC_PCIE0_PIPE_ARES\t\t\t37\n+#define GCC_PCIE0_SLEEP_ARES\t\t\t38\n+#define GCC_PCIE0_CORE_STICKY_ARES\t\t39\n+#define GCC_PCIE0_AXI_MASTER_ARES\t\t40\n+#define GCC_PCIE0_AXI_SLAVE_ARES\t\t41\n+#define GCC_PCIE0_AHB_ARES\t\t\t42\n+#define GCC_PCIE0_AXI_MASTER_STICKY_ARES\t43\n+#define GCC_PCIE0_AXI_SLAVE_STICKY_ARES\t\t44\n+#define GCC_PCIE1_BCR\t\t\t\t45\n+#define GCC_PCIE1_LINK_DOWN_BCR\t\t\t46\n+#define GCC_PCIE1_PHY_BCR\t\t\t47\n+#define GCC_PCIE1PHY_PHY_BCR\t\t\t48\n+#define GCC_PCIE1_PIPE_ARES\t\t\t49\n+#define GCC_PCIE1_SLEEP_ARES\t\t\t50\n+#define GCC_PCIE1_CORE_STICKY_ARES\t\t51\n+#define GCC_PCIE1_AXI_MASTER_ARES\t\t52\n+#define GCC_PCIE1_AXI_SLAVE_ARES\t\t53\n+#define GCC_PCIE1_AHB_ARES\t\t\t54\n+#define GCC_PCIE1_AXI_MASTER_STICKY_ARES\t55\n+#define GCC_PCIE1_AXI_SLAVE_STICKY_ARES\t\t56\n+#define GCC_PCNOC_BCR\t\t\t\t57\n+#define GCC_PCNOC_BUS_TIMEOUT0_BCR\t\t58\n+#define GCC_PCNOC_BUS_TIMEOUT1_BCR\t\t59\n+#define GCC_PCNOC_BUS_TIMEOUT2_BCR\t\t60\n+#define GCC_PCNOC_BUS_TIMEOUT3_BCR\t\t61\n+#define GCC_PCNOC_BUS_TIMEOUT4_BCR\t\t62\n+#define GCC_PCNOC_BUS_TIMEOUT5_BCR\t\t63\n+#define GCC_PCNOC_BUS_TIMEOUT6_BCR\t\t64\n+#define GCC_PCNOC_BUS_TIMEOUT7_BCR\t\t65\n+#define GCC_PCNOC_BUS_TIMEOUT8_BCR\t\t66\n+#define GCC_PCNOC_BUS_TIMEOUT9_BCR\t\t67\n+#define GCC_PCNOC_BUS_TIMEOUT10_BCR\t\t68\n+#define GCC_PCNOC_BUS_TIMEOUT11_BCR\t\t69\n+#define GCC_PRNG_BCR\t\t\t\t70\n+#define GCC_Q6SS_DBG_ARES\t\t\t71\n+#define GCC_Q6_AHB_S_ARES\t\t\t72\n+#define GCC_Q6_AHB_ARES\t\t\t\t73\n+#define GCC_Q6_AXIM2_ARES\t\t\t74\n+#define GCC_Q6_AXIM_ARES\t\t\t75\n+#define GCC_Q6_AXIS_ARES\t\t\t76\n+#define GCC_QDSS_BCR\t\t\t\t77\n+#define GCC_QPIC_BCR\t\t\t\t78\n+#define GCC_QUSB2_0_PHY_BCR\t\t\t79\n+#define GCC_SDCC1_BCR\t\t\t\t80\n+#define GCC_SEC_CTRL_BCR\t\t\t81\n+#define GCC_SPDM_BCR\t\t\t\t82\n+#define GCC_SYSTEM_NOC_BCR\t\t\t83\n+#define GCC_TCSR_BCR\t\t\t\t84\n+#define GCC_TLMM_BCR\t\t\t\t85\n+#define GCC_UBI0_AXI_ARES\t\t\t86\n+#define GCC_UBI0_AHB_ARES\t\t\t87\n+#define GCC_UBI0_NC_AXI_ARES\t\t\t88\n+#define GCC_UBI0_DBG_ARES\t\t\t89\n+#define GCC_UBI0_UTCM_ARES\t\t\t90\n+#define GCC_UBI0_CORE_ARES\t\t\t91\n+#define GCC_UBI32_BCR\t\t\t\t92\n+#define GCC_UNIPHY_BCR\t\t\t\t93\n+#define GCC_UNIPHY_AHB_ARES\t\t\t94\n+#define GCC_UNIPHY_SYS_ARES\t\t\t95\n+#define GCC_UNIPHY_RX_ARES\t\t\t96\n+#define GCC_UNIPHY_TX_ARES\t\t\t97\n+#define GCC_USB0_BCR\t\t\t\t98\n+#define GCC_USB0_PHY_BCR\t\t\t99\n+#define GCC_WCSS_BCR\t\t\t\t100\n+#define GCC_WCSS_DBG_ARES\t\t\t101\n+#define GCC_WCSS_ECAHB_ARES\t\t\t102\n+#define GCC_WCSS_ACMT_ARES\t\t\t103\n+#define GCC_WCSS_DBG_BDG_ARES\t\t\t104\n+#define GCC_WCSS_AHB_S_ARES\t\t\t105\n+#define GCC_WCSS_AXI_M_ARES\t\t\t106\n+#define GCC_WCSS_AXI_S_ARES\t\t\t107\n+#define GCC_WCSS_Q6_BCR\t\t\t\t108\n+#define GCC_WCSSAON_RESET\t\t\t109\n+#define GCC_UNIPHY_SOFT_RESET\t\t\t110\n+#define GCC_GEPHY_MISC_ARES\t\t\t111\n+\n+#endif\n", "prefixes": [ "V12", "1/6" ] }