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GET /api/patches/1768903/?format=api
{ "id": 1768903, "url": "http://patchwork.ozlabs.org/api/patches/1768903/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1681468167-11689-9-git-send-email-quic_srichara@quicinc.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1681468167-11689-9-git-send-email-quic_srichara@quicinc.com>", "list_archive_url": null, "date": "2023-04-14T10:29:26", "name": "[V3,8/9] arm64: dts: Add ipq5018 SoC and rdp432-c2 board support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "af55b5594b58d5feb2e8f015fc5b4706ec0c0fd2", "submitter": { "id": 84297, "url": "http://patchwork.ozlabs.org/api/people/84297/?format=api", "name": "Sricharan Ramabadhran", "email": "quic_srichara@quicinc.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1681468167-11689-9-git-send-email-quic_srichara@quicinc.com/mbox/", "series": [ { "id": 350830, "url": "http://patchwork.ozlabs.org/api/series/350830/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=350830", "date": "2023-04-14T10:29:18", "name": "Add minimal boot support for IPQ5018", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/350830/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1768903/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1768903/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-gpio-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", 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srichara-linux.qualcomm.com (10.80.80.8) by\n nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.986.42; Fri, 14 Apr 2023 03:35:16 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=qcppdkim1;\n bh=gfGWbpMk+N0R3Qthn+z2a8vP6dZaG1JYL5BSM2F6s4I=;\n b=RrBovD/DdzsGym2Od05MW0knFhaoO+6/0/EJQIDbO6xB/weGiHDYg8MakQT0qwNpQRPK\n dJwVV5E7L03oNTOQMAsl5OZXsIbwuCXvQ+Z5A8JZm3kdvfQEAMIrrUQyb0YH9eGs8ssA\n 87jQvq56E90Vl7ZAYwfo7/8+bz58fwP5ZIHYduqfHEKIvYQ1JSHedbPxCD5VxuRvjTjY\n fl+qQyA9voDDwwlOMX2VeC0Ki0Y5HivypgMzfeqnmRic2lnNMw/oaK/I9WVKg/CVwbSM\n SF9YDDAMPe6blHArFsRpNB/dbaJn6rzzhJChZfTHuQjZzcDufXZ9s+ssE3ohbhMYnioA Rw==", "From": "Sricharan Ramabadhran <quic_srichara@quicinc.com>", "To": "<agross@kernel.org>, <andersson@kernel.org>,\n <konrad.dybcio@linaro.org>, <robh+dt@kernel.org>,\n <krzysztof.kozlowski+dt@linaro.org>, <mturquette@baylibre.com>,\n <sboyd@kernel.org>, <ulf.hansson@linaro.org>,\n <linus.walleij@linaro.org>, <catalin.marinas@arm.com>,\n <will@kernel.org>, <p.zabel@pengutronix.de>,\n <linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>,\n <linux-kernel@vger.kernel.org>, <linux-mmc@vger.kernel.org>,\n <linux-gpio@vger.kernel.org>,\n <linux-arm-kernel@lists.infradead.org>, <quic_srichara@quicinc.com>", "CC": "Varadarajan Narayanan <quic_varada@quicinc.com>,\n Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>", "Subject": "[PATCH V3 8/9] arm64: dts: Add ipq5018 SoC and rdp432-c2 board\n support", "Date": "Fri, 14 Apr 2023 15:59:26 +0530", "Message-ID": "<1681468167-11689-9-git-send-email-quic_srichara@quicinc.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1681468167-11689-1-git-send-email-quic_srichara@quicinc.com>", "References": "<1681468167-11689-1-git-send-email-quic_srichara@quicinc.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.80.80.8]", "X-ClientProxiedBy": "nasanex01a.na.qualcomm.com (10.52.223.231) To\n nalasex01c.na.qualcomm.com (10.47.97.35)", "X-QCInternal": "smtphost", "X-Proofpoint-Virus-Version": [ "vendor=nai engine=6200 definitions=5800\n signatures=585085", "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22\n definitions=2023-04-14_04,2023-04-14_01,2023-02-09_01" ], "X-Proofpoint-GUID": "M0Od4aE0xpB252p2GyPjQLmsZuVWGcoR", "X-Proofpoint-ORIG-GUID": "M0Od4aE0xpB252p2GyPjQLmsZuVWGcoR", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n impostorscore=0\n mlxlogscore=999 malwarescore=0 bulkscore=0 phishscore=0 suspectscore=0\n adultscore=0 mlxscore=0 clxscore=1015 lowpriorityscore=0\n priorityscore=1501 spamscore=0 classifier=spam adjust=0 reason=mlx\n scancount=1 engine=8.12.0-2303200000 definitions=main-2304140096", "X-Spam-Status": "No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,\n SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no\n version=3.4.6", "X-Spam-Checker-Version": "SpamAssassin 3.4.6 (2021-04-09) on\n lindbergh.monkeyblade.net", "Precedence": "bulk", "List-ID": "<linux-gpio.vger.kernel.org>", "X-Mailing-List": "linux-gpio@vger.kernel.org" }, "content": "Add initial device tree support for the Qualcomm IPQ5018 SoC and\nrdp432-c2 board.\n\nCo-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>\nSigned-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>\nCo-developed-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>\nSigned-off-by: Gokul Sriram Palanisamy <quic_gokulsri@quicinc.com>\nSigned-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>\n---\n [v3] Fixed all review comments and DTS schema warnings\n\n arch/arm64/boot/dts/qcom/Makefile | 1 +\n arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts | 72 +++++++\n arch/arm64/boot/dts/qcom/ipq5018.dtsi | 248 +++++++++++++++++++++++++\n 3 files changed, 321 insertions(+)\n create mode 100644 arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts\n create mode 100644 arch/arm64/boot/dts/qcom/ipq5018.dtsi", "diff": "diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile\nindex e0e2def..bdb4234 100644\n--- a/arch/arm64/boot/dts/qcom/Makefile\n+++ b/arch/arm64/boot/dts/qcom/Makefile\n@@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_QCOM)\t+= apq8016-sbc.dtb\n dtb-$(CONFIG_ARCH_QCOM)\t+= apq8094-sony-xperia-kitakami-karin_windy.dtb\n dtb-$(CONFIG_ARCH_QCOM)\t+= apq8096-db820c.dtb\n dtb-$(CONFIG_ARCH_QCOM)\t+= apq8096-ifc6640.dtb\n+dtb-$(CONFIG_ARCH_QCOM)\t+= ipq5018-rdp432-c2.dtb\n dtb-$(CONFIG_ARCH_QCOM)\t+= ipq5332-mi01.2.dtb\n dtb-$(CONFIG_ARCH_QCOM)\t+= ipq5332-rdp468.dtb\n dtb-$(CONFIG_ARCH_QCOM)\t+= ipq6018-cp01-c1.dtb\ndiff --git a/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts\nnew file mode 100644\nindex 0000000..1f3f39f\n--- /dev/null\n+++ b/arch/arm64/boot/dts/qcom/ipq5018-rdp432-c2.dts\n@@ -0,0 +1,72 @@\n+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause\n+/*\n+ * IPQ5018 MP03.1-C2 board device tree source\n+ *\n+ * Copyright (c) 2023 The Linux Foundation. All rights reserved.\n+ */\n+\n+/dts-v1/;\n+\n+#include \"ipq5018.dtsi\"\n+\n+/ {\n+\tmodel = \"Qualcomm Technologies, Inc. IPQ5018/AP-RDP432.1-C2\";\n+\tcompatible = \"qcom,ipq5018-rdp432-c1\", \"qcom,ipq5018\";\n+\n+\taliases {\n+\t\tserial0 = &blsp1_uart1;\n+\t};\n+\n+\tchosen {\n+\t\tstdout-path = \"serial0:115200n8\";\n+\t};\n+};\n+\n+&blsp1_uart1 {\n+\tpinctrl-0 = <&uart1_pins>;\n+\tpinctrl-names = \"default\";\n+\tstatus = \"okay\";\n+};\n+\n+&sdhc_1 {\n+\tpinctrl-0 = <&sdc_default_state>;\n+\tpinctrl-names = \"default\";\n+\tmmc-ddr-1_8v;\n+\tmmc-hs200-1_8v;\n+\tmax-frequency = <192000000>;\n+\tbus-width = <4>;\n+\tstatus = \"okay\";\n+};\n+\n+&sleep_clk {\n+\tclock-frequency = <32000>;\n+};\n+\n+&tlmm {\n+\tsdc_default_state: sdc-default-state {\n+\t\tclk-pins {\n+\t\t\tpins = \"gpio9\";\n+\t\t\tfunction = \"sdc1_clk\";\n+\t\t\tdrive-strength = <8>;\n+\t\t\tbias-disable;\n+\t\t};\n+\n+\t\tcmd-pins {\n+\t\t\tpins = \"gpio8\";\n+\t\t\tfunction = \"sdc1_cmd\";\n+\t\t\tdrive-strength = <8>;\n+\t\t\tbias-pull-up;\n+\t\t};\n+\n+\t\tdata-pins {\n+\t\t\tpins = \"gpio4\", \"gpio5\", \"gpio6\", \"gpio7\";\n+\t\t\tfunction = \"sdc1_data\";\n+\t\t\tdrive-strength = <8>;\n+\t\t\tbias-disable;\n+\t\t};\n+\t};\n+};\n+\n+&xo_board_clk {\n+\tclock-frequency = <24000000>;\n+};\ndiff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qcom/ipq5018.dtsi\nnew file mode 100644\nindex 0000000..5e1e31f\n--- /dev/null\n+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi\n@@ -0,0 +1,248 @@\n+// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause\n+/*\n+ * IPQ5018 SoC device tree source\n+ *\n+ * Copyright (c) 2023 The Linux Foundation. All rights reserved.\n+ */\n+\n+#include <dt-bindings/interrupt-controller/arm-gic.h>\n+#include <dt-bindings/clock/qcom,gcc-ipq5018.h>\n+#include <dt-bindings/reset/qcom,gcc-ipq5018.h>\n+\n+/ {\n+\tinterrupt-parent = <&intc>;\n+\t#address-cells = <2>;\n+\t#size-cells = <2>;\n+\n+\tclocks {\n+\t\tsleep_clk: sleep-clk {\n+\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t#clock-cells = <0>;\n+\t\t};\n+\n+\t\txo_board_clk: xo-board-clk {\n+\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t#clock-cells = <0>;\n+\t\t};\n+\t};\n+\n+\tcpus {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tCPU0: cpu@0 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a53\";\n+\t\t\treg = <0x0>;\n+\t\t\tenable-method = \"psci\";\n+\t\t\tnext-level-cache = <&L2_0>;\n+\t\t};\n+\n+\t\tCPU1: cpu@1 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a53\";\n+\t\t\treg = <0x1>;\n+\t\t\tenable-method = \"psci\";\n+\t\t\tnext-level-cache = <&L2_0>;\n+\t\t};\n+\n+\t\tL2_0: l2-cache {\n+\t\t\tcompatible = \"cache\";\n+\t\t\tcache-level = <2>;\n+\t\t};\n+\t};\n+\n+\tfirmware {\n+\t\tscm {\n+\t\t\tcompatible = \"qcom,scm-ipq5018\", \"qcom,scm\";\n+\t\t};\n+\t};\n+\n+\tmemory@40000000 {\n+\t\tdevice_type = \"memory\";\n+\t\t/* We expect the bootloader to fill in the size */\n+\t\treg = <0x0 0x40000000 0x0 0x0>;\n+\t};\n+\n+\tpmu {\n+\t\tcompatible = \"arm,cortex-a53-pmu\";\n+\t\tinterrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n+\t};\n+\n+\tpsci {\n+\t\tcompatible = \"arm,psci-1.0\";\n+\t\tmethod = \"smc\";\n+\t};\n+\n+\treserved-memory {\n+\t\t#address-cells = <2>;\n+\t\t#size-cells = <2>;\n+\t\tranges;\n+\n+\t\ttz_region: tz@4ac00000 {\n+\t\t\treg = <0x0 0x4ac00000 0x0 0x400000>;\n+\t\t\tno-map;\n+\t\t};\n+\t};\n+\n+\tsoc: soc@0 {\n+\t\tcompatible = \"simple-bus\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tranges = <0 0 0 0xffffffff>;\n+\n+\t\ttlmm: pinctrl@1000000 {\n+\t\t\tcompatible = \"qcom,ipq5018-tlmm\";\n+\t\t\treg = <0x01000000 0x300000>;\n+\t\t\tinterrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tgpio-controller;\n+\t\t\t#gpio-cells = <2>;\n+\t\t\tgpio-ranges = <&tlmm 0 0 47>;\n+\t\t\tinterrupt-controller;\n+\t\t\t#interrupt-cells = <2>;\n+\n+\t\t\tuart1_pins: uart1-state {\n+\t\t\t\tpins = \"gpio31\", \"gpio32\", \"gpio33\", \"gpio34\";\n+\t\t\t\tfunction = \"blsp1_uart1\";\n+\t\t\t\tdrive-strength = <8>;\n+\t\t\t\tbias-pull-down;\n+\t\t\t};\n+\t\t};\n+\n+\t\tgcc: clock-controller@1800000 {\n+\t\t\tcompatible = \"qcom,ipq5018-gcc\";\n+\t\t\treg = <0x01800000 0x80000>;\n+\t\t\tclocks = <&xo_board_clk>,\n+\t\t\t\t <&sleep_clk>,\n+\t\t\t\t <0>,\n+\t\t\t\t <0>,\n+\t\t\t\t <0>,\n+\t\t\t\t <0>,\n+\t\t\t\t <0>,\n+\t\t\t\t <0>,\n+\t\t\t\t <0>;\n+\t\t\t#clock-cells = <1>;\n+\t\t\t#reset-cells = <1>;\n+\t\t\t#power-domain-cells = <1>;\n+\t\t};\n+\n+\t\tsdhc_1: mmc@7804000 {\n+\t\t\tcompatible = \"qcom,ipq5018-sdhci\", \"qcom,sdhci-msm-v5\";\n+\t\t\treg = <0x7804000 0x1000>;\n+\t\t\treg-names = \"hc\";\n+\n+\t\t\tinterrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tinterrupt-names = \"hc_irq\", \"pwr_irq\";\n+\n+\t\t\tclocks = <&gcc GCC_SDCC1_AHB_CLK>,\n+\t\t\t\t <&gcc GCC_SDCC1_APPS_CLK>,\n+\t\t\t\t <&xo_board_clk>;\n+\t\t\tclock-names = \"iface\", \"core\", \"xo\";\n+\t\t\tnon-removable;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tblsp1_uart1: serial@78af000 {\n+\t\t\tcompatible = \"qcom,msm-uartdm-v1.4\", \"qcom,msm-uartdm\";\n+\t\t\treg = <0x078af000 0x200>;\n+\t\t\tinterrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,\n+\t\t\t\t <&gcc GCC_BLSP1_AHB_CLK>;\n+\t\t\tclock-names = \"core\", \"iface\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tintc: interrupt-controller@b000000 {\n+\t\t\tcompatible = \"qcom,msm-qgic2\";\n+\t\t\treg = <0x0b000000 0x1000>, /* GICD */\n+\t\t\t <0x0b002000 0x2000>, /* GICC */\n+\t\t\t <0x0b001000 0x1000>, /* GICH */\n+\t\t\t <0x0b004000 0x2000>; /* GICV */\n+\t\t\tinterrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n+\t\t\tinterrupt-controller;\n+\t\t\t#interrupt-cells = <3>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tranges = <0 0x0b00a000 0x1ffa>;\n+\n+\t\t\tv2m0: v2m@0 {\n+\t\t\t\tcompatible = \"arm,gic-v2m-frame\";\n+\t\t\t\treg = <0x00000000 0xffd>;\n+\t\t\t\tmsi-controller;\n+\t\t\t};\n+\n+\t\t\tv2m1: v2m@1000 {\n+\t\t\t\tcompatible = \"arm,gic-v2m-frame\";\n+\t\t\t\treg = <0x00001000 0xffd>;\n+\t\t\t\tmsi-controller;\n+\t\t\t};\n+\t\t};\n+\n+\t\ttimer@b120000 {\n+\t\t\tcompatible = \"arm,armv7-timer-mem\";\n+\t\t\treg = <0x0b120000 0x1000>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tranges;\n+\n+\t\t\tframe@b120000 {\n+\t\t\t\treg = <0x0b121000 0x1000>,\n+\t\t\t\t <0x0b122000 0x1000>;\n+\t\t\t\tinterrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tframe-number = <0>;\n+\t\t\t};\n+\n+\t\t\tframe@b123000 {\n+\t\t\t\treg = <0xb123000 0x1000>;\n+\t\t\t\tinterrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tframe-number = <1>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tframe@b124000 {\n+\t\t\t\tframe-number = <2>;\n+\t\t\t\tinterrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\treg = <0x0b124000 0x1000>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tframe@b125000 {\n+\t\t\t\treg = <0x0b125000 0x1000>;\n+\t\t\t\tinterrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tframe-number = <3>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tframe@b126000 {\n+\t\t\t\treg = <0x0b126000 0x1000>;\n+\t\t\t\tinterrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tframe-number = <4>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tframe@b127000 {\n+\t\t\t\treg = <0x0b127000 0x1000>;\n+\t\t\t\tinterrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tframe-number = <5>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tframe@b128000 {\n+\t\t\t\treg = <0x0b128000 0x1000>;\n+\t\t\t\tinterrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tframe-number = <6>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\ttimer {\n+\t\tcompatible = \"arm,armv8-timer\";\n+\t\tinterrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,\n+\t\t\t <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,\n+\t\t\t <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,\n+\t\t\t <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;\n+\t};\n+};\n", "prefixes": [ "V3", "8/9" ] }