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GET /api/patches/1768898/?format=api
{ "id": 1768898, "url": "http://patchwork.ozlabs.org/api/patches/1768898/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1681468167-11689-5-git-send-email-quic_srichara@quicinc.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1681468167-11689-5-git-send-email-quic_srichara@quicinc.com>", "list_archive_url": null, "date": "2023-04-14T10:29:22", "name": "[V3,4/9] pinctrl: qcom: Add IPQ5018 pinctrl driver", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "379bd1ac104b5fe572e1442a8ed0575665597f89", "submitter": { "id": 84297, "url": "http://patchwork.ozlabs.org/api/people/84297/?format=api", "name": "Sricharan Ramabadhran", "email": "quic_srichara@quicinc.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/1681468167-11689-5-git-send-email-quic_srichara@quicinc.com/mbox/", "series": [ { "id": 350830, "url": "http://patchwork.ozlabs.org/api/series/350830/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=350830", "date": "2023-04-14T10:29:18", "name": "Add minimal boot support for IPQ5018", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/350830/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1768898/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1768898/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-gpio-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2620:137:e000::1:20; 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Fri, 14 Apr 2023 03:34:51 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=qcppdkim1;\n bh=A/e9gjI36eM9/0JYpWApUyLVBeF8sV/ynmjCJrc2VBI=;\n b=knzsGgGoFI6fcTnwd0giTIK/OOHAiDgFwU8QE5ltsxMza3edqoFUKwCU+EZO6q4uX5T2\n IqLzdiFAs5kCW2KvChhyYxp99hdShQwLDune92yU4MaoRaqZL+wD8pw3xw35v3wwLCVr\n zPc74/TBFBWihb/8EI6jlrqG0TPqlaNoeevipE8vKNfrJMrvI8jlqRTEsnqZaxYt0KoP\n DIu7eScuUzy01O6EemF9aR2wdvzikpni8NKAjomJoqn8opO27VBoWZKAUHoH79q55qTi\n bdSchtnVj4hDajsPPj416w3wE657Dt4lW3aOXRIXyT+uRh8g/FvqHyxFs7ZaCAM86KgJ cg==", "From": "Sricharan Ramabadhran <quic_srichara@quicinc.com>", "To": "<agross@kernel.org>, <andersson@kernel.org>,\n <konrad.dybcio@linaro.org>, <robh+dt@kernel.org>,\n <krzysztof.kozlowski+dt@linaro.org>, <mturquette@baylibre.com>,\n <sboyd@kernel.org>, <ulf.hansson@linaro.org>,\n <linus.walleij@linaro.org>, <catalin.marinas@arm.com>,\n <will@kernel.org>, <p.zabel@pengutronix.de>,\n <linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>,\n <linux-kernel@vger.kernel.org>, <linux-mmc@vger.kernel.org>,\n <linux-gpio@vger.kernel.org>,\n <linux-arm-kernel@lists.infradead.org>, <quic_srichara@quicinc.com>", "CC": "Nitheesh Sekar <quic_nsekar@quicinc.com>,\n Varadarajan Narayanan <quic_varada@quicinc.com>", "Subject": "[PATCH V3 4/9] pinctrl: qcom: Add IPQ5018 pinctrl driver", "Date": "Fri, 14 Apr 2023 15:59:22 +0530", "Message-ID": "<1681468167-11689-5-git-send-email-quic_srichara@quicinc.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1681468167-11689-1-git-send-email-quic_srichara@quicinc.com>", "References": "<1681468167-11689-1-git-send-email-quic_srichara@quicinc.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.80.80.8]", "X-ClientProxiedBy": "nasanex01a.na.qualcomm.com (10.52.223.231) To\n nalasex01c.na.qualcomm.com (10.47.97.35)", "X-QCInternal": "smtphost", "X-Proofpoint-Virus-Version": [ "vendor=nai engine=6200 definitions=5800\n signatures=585085", "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22\n definitions=2023-04-14_04,2023-04-14_01,2023-02-09_01" ], "X-Proofpoint-ORIG-GUID": "OqVsTJdpnGexJ2sdAclAiSNSkWuKz136", "X-Proofpoint-GUID": "OqVsTJdpnGexJ2sdAclAiSNSkWuKz136", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n lowpriorityscore=0\n bulkscore=0 priorityscore=1501 adultscore=0 phishscore=0 clxscore=1015\n impostorscore=0 mlxlogscore=999 spamscore=0 suspectscore=0 mlxscore=0\n malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1\n engine=8.12.0-2303200000 definitions=main-2304140095", "X-Spam-Status": "No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS,\n T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6", "X-Spam-Checker-Version": "SpamAssassin 3.4.6 (2021-04-09) on\n lindbergh.monkeyblade.net", "Precedence": "bulk", "List-ID": "<linux-gpio.vger.kernel.org>", "X-Mailing-List": "linux-gpio@vger.kernel.org" }, "content": "Add pinctrl definitions for the TLMM of IPQ5018.\n\nCo-developed-by: Nitheesh Sekar <quic_nsekar@quicinc.com>\nSigned-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>\nCo-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>\nSigned-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>\nSigned-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>\nReviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>\nReported-by: kernel test robot <lkp@intel.com>\n---\n [v3] Picked up Bjorn's reviewed tag\n\n drivers/pinctrl/qcom/Kconfig | 10 +\n drivers/pinctrl/qcom/Makefile | 1 +\n drivers/pinctrl/qcom/pinctrl-ipq5018.c | 791 +++++++++++++++++++++++++++++++++\n 3 files changed, 802 insertions(+)\n create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq5018.c", "diff": "diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig\nindex e52cfab..00f9100 100644\n--- a/drivers/pinctrl/qcom/Kconfig\n+++ b/drivers/pinctrl/qcom/Kconfig\n@@ -39,6 +39,16 @@ config PINCTRL_IPQ4019\n \t This is the pinctrl, pinmux, pinconf and gpiolib driver for the\n \t Qualcomm TLMM block found in the Qualcomm IPQ4019 platform.\n \n+config PINCTRL_IPQ5018\n+\ttristate \"Qualcomm Technologies, Inc. IPQ5018 pin controller driver\"\n+\tdepends on GPIOLIB && OF\n+\tselect PINCTRL_MSM\n+\thelp\n+\t This is the pinctrl, pinmux, pinconf and gpiolib driver for\n+\t the Qualcomm Technologies Inc. TLMM block found on the\n+\t Qualcomm Technologies Inc. IPQ5018 platform. Select this for\n+\t IPQ5018.\n+\n config PINCTRL_IPQ8064\n \ttristate \"Qualcomm IPQ8064 pin controller driver\"\n \tdepends on OF\ndiff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile\nindex 521b021..be91b62 100644\n--- a/drivers/pinctrl/qcom/Makefile\n+++ b/drivers/pinctrl/qcom/Makefile\n@@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_MSM)\t+= pinctrl-msm.o\n obj-$(CONFIG_PINCTRL_APQ8064)\t+= pinctrl-apq8064.o\n obj-$(CONFIG_PINCTRL_APQ8084)\t+= pinctrl-apq8084.o\n obj-$(CONFIG_PINCTRL_IPQ4019)\t+= pinctrl-ipq4019.o\n+obj-$(CONFIG_PINCTRL_IPQ5018)\t+= pinctrl-ipq5018.o\n obj-$(CONFIG_PINCTRL_IPQ8064)\t+= pinctrl-ipq8064.o\n obj-$(CONFIG_PINCTRL_IPQ5332)\t+= pinctrl-ipq5332.o\n obj-$(CONFIG_PINCTRL_IPQ8074)\t+= pinctrl-ipq8074.o\ndiff --git a/drivers/pinctrl/qcom/pinctrl-ipq5018.c b/drivers/pinctrl/qcom/pinctrl-ipq5018.c\nnew file mode 100644\nindex 0000000..f544651\n--- /dev/null\n+++ b/drivers/pinctrl/qcom/pinctrl-ipq5018.c\n@@ -0,0 +1,791 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Copyright (c) 2019-2021, 2023 The Linux Foundation. All rights reserved.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/platform_device.h>\n+#include <linux/pinctrl/pinctrl.h>\n+\n+#include \"pinctrl-msm.h\"\n+\n+#define FUNCTION(fname)\t\t\t \\\n+\t[msm_mux_##fname] = {\t\t \\\n+\t\t.name = #fname,\t\t\t\t\\\n+\t\t.groups = fname##_groups, \\\n+\t\t.ngroups = ARRAY_SIZE(fname##_groups),\t\\\n+\t}\n+\n+#define REG_SIZE 0x1000\n+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9)\t\\\n+\t{\t\t\t\t\t \\\n+\t\t.name = \"gpio\" #id,\t\t\t\\\n+\t\t.pins = gpio##id##_pins,\t\t\\\n+\t\t.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins),\t\\\n+\t\t.funcs = (int[]){\t\t\t\\\n+\t\t\tmsm_mux_gpio, /* gpio mode */\t\\\n+\t\t\tmsm_mux_##f1,\t\t\t\\\n+\t\t\tmsm_mux_##f2,\t\t\t\\\n+\t\t\tmsm_mux_##f3,\t\t\t\\\n+\t\t\tmsm_mux_##f4,\t\t\t\\\n+\t\t\tmsm_mux_##f5,\t\t\t\\\n+\t\t\tmsm_mux_##f6,\t\t\t\\\n+\t\t\tmsm_mux_##f7,\t\t\t\\\n+\t\t\tmsm_mux_##f8,\t\t\t\\\n+\t\t\tmsm_mux_##f9\t\t\t\\\n+\t\t},\t\t\t\t \\\n+\t\t.nfuncs = 10,\t\t\t\t\\\n+\t\t.ctl_reg = REG_SIZE * id,\t\t\\\n+\t\t.io_reg = 0x4 + REG_SIZE * id,\t\t\\\n+\t\t.intr_cfg_reg = 0x8 + REG_SIZE * id,\t\\\n+\t\t.intr_status_reg = 0xc + REG_SIZE * id,\t\\\n+\t\t.intr_target_reg = 0x8 + REG_SIZE * id,\t\\\n+\t\t.mux_bit = 2,\t\t\t\\\n+\t\t.pull_bit = 0,\t\t\t\\\n+\t\t.drv_bit = 6,\t\t\t\\\n+\t\t.oe_bit = 9,\t\t\t\\\n+\t\t.in_bit = 0,\t\t\t\\\n+\t\t.out_bit = 1,\t\t\t\\\n+\t\t.intr_enable_bit = 0,\t\t\\\n+\t\t.intr_status_bit = 0,\t\t\\\n+\t\t.intr_target_bit = 5,\t\t\\\n+\t\t.intr_target_kpss_val = 3,\t\\\n+\t\t.intr_raw_status_bit = 4,\t\\\n+\t\t.intr_polarity_bit = 1,\t\t\\\n+\t\t.intr_detection_bit = 2,\t\\\n+\t\t.intr_detection_width = 2,\t\\\n+\t}\n+\n+static const struct pinctrl_pin_desc ipq5018_pins[] = {\n+\tPINCTRL_PIN(0, \"GPIO_0\"),\n+\tPINCTRL_PIN(1, \"GPIO_1\"),\n+\tPINCTRL_PIN(2, \"GPIO_2\"),\n+\tPINCTRL_PIN(3, \"GPIO_3\"),\n+\tPINCTRL_PIN(4, \"GPIO_4\"),\n+\tPINCTRL_PIN(5, \"GPIO_5\"),\n+\tPINCTRL_PIN(6, \"GPIO_6\"),\n+\tPINCTRL_PIN(7, \"GPIO_7\"),\n+\tPINCTRL_PIN(8, \"GPIO_8\"),\n+\tPINCTRL_PIN(9, \"GPIO_9\"),\n+\tPINCTRL_PIN(10, \"GPIO_10\"),\n+\tPINCTRL_PIN(11, \"GPIO_11\"),\n+\tPINCTRL_PIN(12, \"GPIO_12\"),\n+\tPINCTRL_PIN(13, \"GPIO_13\"),\n+\tPINCTRL_PIN(14, \"GPIO_14\"),\n+\tPINCTRL_PIN(15, \"GPIO_15\"),\n+\tPINCTRL_PIN(16, \"GPIO_16\"),\n+\tPINCTRL_PIN(17, \"GPIO_17\"),\n+\tPINCTRL_PIN(18, \"GPIO_18\"),\n+\tPINCTRL_PIN(19, \"GPIO_19\"),\n+\tPINCTRL_PIN(20, \"GPIO_20\"),\n+\tPINCTRL_PIN(21, \"GPIO_21\"),\n+\tPINCTRL_PIN(22, \"GPIO_22\"),\n+\tPINCTRL_PIN(23, \"GPIO_23\"),\n+\tPINCTRL_PIN(24, \"GPIO_24\"),\n+\tPINCTRL_PIN(25, \"GPIO_25\"),\n+\tPINCTRL_PIN(26, \"GPIO_26\"),\n+\tPINCTRL_PIN(27, \"GPIO_27\"),\n+\tPINCTRL_PIN(28, \"GPIO_28\"),\n+\tPINCTRL_PIN(29, \"GPIO_29\"),\n+\tPINCTRL_PIN(30, \"GPIO_30\"),\n+\tPINCTRL_PIN(31, \"GPIO_31\"),\n+\tPINCTRL_PIN(32, \"GPIO_32\"),\n+\tPINCTRL_PIN(33, \"GPIO_33\"),\n+\tPINCTRL_PIN(34, \"GPIO_34\"),\n+\tPINCTRL_PIN(35, \"GPIO_35\"),\n+\tPINCTRL_PIN(36, \"GPIO_36\"),\n+\tPINCTRL_PIN(37, \"GPIO_37\"),\n+\tPINCTRL_PIN(38, \"GPIO_38\"),\n+\tPINCTRL_PIN(39, \"GPIO_39\"),\n+\tPINCTRL_PIN(40, \"GPIO_40\"),\n+\tPINCTRL_PIN(41, \"GPIO_41\"),\n+\tPINCTRL_PIN(42, \"GPIO_42\"),\n+\tPINCTRL_PIN(43, \"GPIO_43\"),\n+\tPINCTRL_PIN(44, \"GPIO_44\"),\n+\tPINCTRL_PIN(45, \"GPIO_45\"),\n+\tPINCTRL_PIN(46, \"GPIO_46\"),\n+};\n+\n+#define DECLARE_MSM_GPIO_PINS(pin) \\\n+\tstatic const unsigned int gpio##pin##_pins[] = { pin }\n+DECLARE_MSM_GPIO_PINS(0);\n+DECLARE_MSM_GPIO_PINS(1);\n+DECLARE_MSM_GPIO_PINS(2);\n+DECLARE_MSM_GPIO_PINS(3);\n+DECLARE_MSM_GPIO_PINS(4);\n+DECLARE_MSM_GPIO_PINS(5);\n+DECLARE_MSM_GPIO_PINS(6);\n+DECLARE_MSM_GPIO_PINS(7);\n+DECLARE_MSM_GPIO_PINS(8);\n+DECLARE_MSM_GPIO_PINS(9);\n+DECLARE_MSM_GPIO_PINS(10);\n+DECLARE_MSM_GPIO_PINS(11);\n+DECLARE_MSM_GPIO_PINS(12);\n+DECLARE_MSM_GPIO_PINS(13);\n+DECLARE_MSM_GPIO_PINS(14);\n+DECLARE_MSM_GPIO_PINS(15);\n+DECLARE_MSM_GPIO_PINS(16);\n+DECLARE_MSM_GPIO_PINS(17);\n+DECLARE_MSM_GPIO_PINS(18);\n+DECLARE_MSM_GPIO_PINS(19);\n+DECLARE_MSM_GPIO_PINS(20);\n+DECLARE_MSM_GPIO_PINS(21);\n+DECLARE_MSM_GPIO_PINS(22);\n+DECLARE_MSM_GPIO_PINS(23);\n+DECLARE_MSM_GPIO_PINS(24);\n+DECLARE_MSM_GPIO_PINS(25);\n+DECLARE_MSM_GPIO_PINS(26);\n+DECLARE_MSM_GPIO_PINS(27);\n+DECLARE_MSM_GPIO_PINS(28);\n+DECLARE_MSM_GPIO_PINS(29);\n+DECLARE_MSM_GPIO_PINS(30);\n+DECLARE_MSM_GPIO_PINS(31);\n+DECLARE_MSM_GPIO_PINS(32);\n+DECLARE_MSM_GPIO_PINS(33);\n+DECLARE_MSM_GPIO_PINS(34);\n+DECLARE_MSM_GPIO_PINS(35);\n+DECLARE_MSM_GPIO_PINS(36);\n+DECLARE_MSM_GPIO_PINS(37);\n+DECLARE_MSM_GPIO_PINS(38);\n+DECLARE_MSM_GPIO_PINS(39);\n+DECLARE_MSM_GPIO_PINS(40);\n+DECLARE_MSM_GPIO_PINS(41);\n+DECLARE_MSM_GPIO_PINS(42);\n+DECLARE_MSM_GPIO_PINS(43);\n+DECLARE_MSM_GPIO_PINS(44);\n+DECLARE_MSM_GPIO_PINS(45);\n+DECLARE_MSM_GPIO_PINS(46);\n+\n+enum ipq5018_functions {\n+\tmsm_mux_atest_char,\n+\tmsm_mux_audio_pdm0,\n+\tmsm_mux_audio_pdm1,\n+\tmsm_mux_audio_rxbclk,\n+\tmsm_mux_audio_rxd,\n+\tmsm_mux_audio_rxfsync,\n+\tmsm_mux_audio_rxmclk,\n+\tmsm_mux_audio_txbclk,\n+\tmsm_mux_audio_txd,\n+\tmsm_mux_audio_txfsync,\n+\tmsm_mux_audio_txmclk,\n+\tmsm_mux_blsp0_i2c,\n+\tmsm_mux_blsp0_spi,\n+\tmsm_mux_blsp0_uart0,\n+\tmsm_mux_blsp0_uart1,\n+\tmsm_mux_blsp1_i2c0,\n+\tmsm_mux_blsp1_i2c1,\n+\tmsm_mux_blsp1_spi0,\n+\tmsm_mux_blsp1_spi1,\n+\tmsm_mux_blsp1_uart0,\n+\tmsm_mux_blsp1_uart1,\n+\tmsm_mux_blsp1_uart2,\n+\tmsm_mux_blsp2_i2c0,\n+\tmsm_mux_blsp2_i2c1,\n+\tmsm_mux_blsp2_spi,\n+\tmsm_mux_blsp2_spi0,\n+\tmsm_mux_blsp2_spi1,\n+\tmsm_mux_btss,\n+\tmsm_mux_burn0,\n+\tmsm_mux_burn1,\n+\tmsm_mux_cri_trng,\n+\tmsm_mux_cri_trng0,\n+\tmsm_mux_cri_trng1,\n+\tmsm_mux_cxc_clk,\n+\tmsm_mux_cxc_data,\n+\tmsm_mux_dbg_out,\n+\tmsm_mux_eud_gpio,\n+\tmsm_mux_gcc_plltest,\n+\tmsm_mux_gcc_tlmm,\n+\tmsm_mux_gpio,\n+\tmsm_mux_led0,\n+\tmsm_mux_led2,\n+\tmsm_mux_mac0,\n+\tmsm_mux_mac1,\n+\tmsm_mux_mdc,\n+\tmsm_mux_mdio,\n+\tmsm_mux_pcie0_clk,\n+\tmsm_mux_pcie0_wake,\n+\tmsm_mux_pcie1_clk,\n+\tmsm_mux_pcie1_wake,\n+\tmsm_mux_pll_test,\n+\tmsm_mux_prng_rosc,\n+\tmsm_mux_pwm0,\n+\tmsm_mux_pwm1,\n+\tmsm_mux_pwm2,\n+\tmsm_mux_pwm3,\n+\tmsm_mux_qdss_cti_trig_in_a0,\n+\tmsm_mux_qdss_cti_trig_in_a1,\n+\tmsm_mux_qdss_cti_trig_in_b0,\n+\tmsm_mux_qdss_cti_trig_in_b1,\n+\tmsm_mux_qdss_cti_trig_out_a0,\n+\tmsm_mux_qdss_cti_trig_out_a1,\n+\tmsm_mux_qdss_cti_trig_out_b0,\n+\tmsm_mux_qdss_cti_trig_out_b1,\n+\tmsm_mux_qdss_traceclk_a,\n+\tmsm_mux_qdss_traceclk_b,\n+\tmsm_mux_qdss_tracectl_a,\n+\tmsm_mux_qdss_tracectl_b,\n+\tmsm_mux_qdss_tracedata_a,\n+\tmsm_mux_qdss_tracedata_b,\n+\tmsm_mux_qspi_clk,\n+\tmsm_mux_qspi_cs,\n+\tmsm_mux_qspi_data,\n+\tmsm_mux_reset_out,\n+\tmsm_mux_sdc1_clk,\n+\tmsm_mux_sdc1_cmd,\n+\tmsm_mux_sdc1_data,\n+\tmsm_mux_wci_txd,\n+\tmsm_mux_wci_rxd,\n+\tmsm_mux_wsa_swrm,\n+\tmsm_mux_wsi_clk3,\n+\tmsm_mux_wsi_data3,\n+\tmsm_mux_wsis_reset,\n+\tmsm_mux_xfem,\n+\tmsm_mux__,\n+};\n+\n+static const char * const atest_char_groups[] = {\n+\t\"gpio0\", \"gpio1\", \"gpio2\", \"gpio3\", \"gpio37\",\n+};\n+\n+static const char * const _groups[] = {\n+\t\"gpio0\", \"gpio1\", \"gpio2\", \"gpio3\", \"gpio4\", \"gpio5\", \"gpio6\", \"gpio7\",\n+\t\"gpio8\", \"gpio9\", \"gpio10\", \"gpio11\", \"gpio12\", \"gpio13\", \"gpio14\",\n+\t\"gpio15\", \"gpio16\", \"gpio17\", \"gpio18\", \"gpio19\", \"gpio20\", \"gpio21\",\n+\t\"gpio22\", \"gpio23\", \"gpio24\", \"gpio25\", \"gpio26\", \"gpio27\", \"gpio28\",\n+\t\"gpio29\", \"gpio30\", \"gpio31\", \"gpio32\", \"gpio33\", \"gpio34\", \"gpio35\",\n+\t\"gpio36\", \"gpio37\", \"gpio38\", \"gpio39\", \"gpio40\", \"gpio41\", \"gpio42\",\n+\t\"gpio43\", \"gpio44\", \"gpio45\", \"gpio46\",\n+};\n+\n+static const char * const wci_txd_groups[] = {\n+\t\"gpio0\", \"gpio1\", \"gpio2\", \"gpio3\",\n+\t\"gpio42\", \"gpio43\", \"gpio44\", \"gpio45\",\n+};\n+\n+static const char * const wci_rxd_groups[] = {\n+\t\"gpio0\", \"gpio1\", \"gpio2\", \"gpio3\",\n+\t\"gpio42\", \"gpio43\", \"gpio44\", \"gpio45\",\n+};\n+\n+static const char * const xfem_groups[] = {\n+\t\"gpio0\", \"gpio1\", \"gpio2\", \"gpio3\",\n+\t\"gpio42\", \"gpio43\", \"gpio44\", \"gpio45\",\n+};\n+\n+static const char * const qdss_cti_trig_out_a0_groups[] = {\n+\t\"gpio0\",\n+};\n+\n+static const char * const qdss_cti_trig_in_a0_groups[] = {\n+\t\"gpio1\",\n+};\n+\n+static const char * const qdss_cti_trig_out_a1_groups[] = {\n+\t\"gpio2\",\n+};\n+\n+static const char * const qdss_cti_trig_in_a1_groups[] = {\n+\t\"gpio3\",\n+};\n+\n+static const char * const sdc1_data_groups[] = {\n+\t\"gpio4\", \"gpio5\", \"gpio6\", \"gpio7\",\n+};\n+\n+static const char * const qspi_data_groups[] = {\n+\t\"gpio4\",\n+\t\"gpio5\",\n+\t\"gpio6\",\n+\t\"gpio7\",\n+};\n+\n+static const char * const blsp1_spi1_groups[] = {\n+\t\"gpio4\", \"gpio5\", \"gpio6\", \"gpio7\",\n+};\n+\n+static const char * const btss_groups[] = {\n+\t\"gpio4\", \"gpio5\", \"gpio6\", \"gpio7\", \"gpio8\", \"gpio17\", \"gpio18\",\n+\t\"gpio19\", \"gpio23\", \"gpio24\", \"gpio25\", \"gpio26\", \"gpio27\", \"gpio28\",\n+};\n+\n+static const char * const dbg_out_groups[] = {\n+\t\"gpio4\",\n+};\n+\n+static const char * const qdss_traceclk_a_groups[] = {\n+\t\"gpio4\",\n+};\n+\n+static const char * const burn0_groups[] = {\n+\t\"gpio4\",\n+};\n+\n+static const char * const cxc_clk_groups[] = {\n+\t\"gpio5\",\n+};\n+\n+static const char * const blsp1_i2c1_groups[] = {\n+\t\"gpio5\", \"gpio6\",\n+};\n+\n+static const char * const qdss_tracectl_a_groups[] = {\n+\t\"gpio5\",\n+};\n+\n+static const char * const burn1_groups[] = {\n+\t\"gpio5\",\n+};\n+\n+static const char * const cxc_data_groups[] = {\n+\t\"gpio6\",\n+};\n+\n+static const char * const qdss_tracedata_a_groups[] = {\n+\t\"gpio6\", \"gpio7\", \"gpio8\", \"gpio9\", \"gpio10\", \"gpio11\", \"gpio12\",\n+\t\"gpio13\", \"gpio14\", \"gpio15\", \"gpio16\", \"gpio17\", \"gpio18\", \"gpio19\",\n+\t\"gpio20\", \"gpio21\",\n+};\n+\n+static const char * const mac0_groups[] = {\n+\t\"gpio7\",\n+};\n+\n+static const char * const sdc1_cmd_groups[] = {\n+\t\"gpio8\",\n+};\n+\n+static const char * const qspi_cs_groups[] = {\n+\t\"gpio8\",\n+};\n+\n+static const char * const mac1_groups[] = {\n+\t\"gpio8\",\n+};\n+\n+static const char * const sdc1_clk_groups[] = {\n+\t\"gpio9\",\n+};\n+\n+static const char * const qspi_clk_groups[] = {\n+\t\"gpio9\",\n+};\n+\n+static const char * const blsp0_spi_groups[] = {\n+\t\"gpio10\", \"gpio11\", \"gpio12\", \"gpio13\",\n+};\n+\n+static const char * const blsp1_uart0_groups[] = {\n+\t\"gpio10\", \"gpio11\", \"gpio12\", \"gpio13\",\n+};\n+\n+static const char * const gcc_plltest_groups[] = {\n+\t\"gpio10\", \"gpio12\",\n+};\n+\n+static const char * const gcc_tlmm_groups[] = {\n+\t\"gpio11\",\n+};\n+\n+static const char * const blsp0_i2c_groups[] = {\n+\t\"gpio12\", \"gpio13\",\n+};\n+\n+static const char * const pcie0_clk_groups[] = {\n+\t\"gpio14\",\n+};\n+\n+static const char * const cri_trng0_groups[] = {\n+\t\"gpio14\",\n+};\n+\n+static const char * const cri_trng1_groups[] = {\n+\t\"gpio15\",\n+};\n+\n+static const char * const pcie0_wake_groups[] = {\n+\t\"gpio16\",\n+};\n+\n+static const char * const cri_trng_groups[] = {\n+\t\"gpio16\",\n+};\n+\n+static const char * const pcie1_clk_groups[] = {\n+\t\"gpio17\",\n+};\n+\n+static const char * const prng_rosc_groups[] = {\n+\t\"gpio17\",\n+};\n+\n+static const char * const blsp1_spi0_groups[] = {\n+\t\"gpio18\", \"gpio19\", \"gpio20\", \"gpio21\",\n+};\n+\n+static const char * const pcie1_wake_groups[] = {\n+\t\"gpio19\",\n+};\n+\n+static const char * const blsp1_i2c0_groups[] = {\n+\t\"gpio19\", \"gpio20\",\n+};\n+\n+static const char * const blsp0_uart0_groups[] = {\n+\t\"gpio20\", \"gpio21\",\n+};\n+\n+static const char * const pll_test_groups[] = {\n+\t\"gpio22\",\n+};\n+\n+static const char * const eud_gpio_groups[] = {\n+\t\"gpio22\", \"gpio31\", \"gpio32\", \"gpio33\", \"gpio34\", \"gpio35\",\n+};\n+\n+static const char * const audio_rxmclk_groups[] = {\n+\t\"gpio23\", \"gpio23\",\n+};\n+\n+static const char * const audio_pdm0_groups[] = {\n+\t\"gpio23\", \"gpio24\",\n+};\n+\n+static const char * const blsp2_spi1_groups[] = {\n+\t\"gpio23\", \"gpio24\", \"gpio25\", \"gpio26\",\n+};\n+\n+static const char * const blsp1_uart2_groups[] = {\n+\t\"gpio23\", \"gpio24\", \"gpio25\", \"gpio26\",\n+};\n+\n+static const char * const qdss_tracedata_b_groups[] = {\n+\t\"gpio23\", \"gpio24\", \"gpio25\", \"gpio26\", \"gpio27\", \"gpio28\", \"gpio29\",\n+\t\"gpio30\", \"gpio31\", \"gpio32\", \"gpio33\", \"gpio34\", \"gpio35\", \"gpio36\",\n+\t\"gpio37\", \"gpio38\",\n+};\n+\n+static const char * const audio_rxbclk_groups[] = {\n+\t\"gpio24\",\n+};\n+\n+static const char * const audio_rxfsync_groups[] = {\n+\t\"gpio25\",\n+};\n+\n+static const char * const audio_pdm1_groups[] = {\n+\t\"gpio25\", \"gpio26\",\n+};\n+\n+static const char * const blsp2_i2c1_groups[] = {\n+\t\"gpio25\", \"gpio26\",\n+};\n+\n+static const char * const audio_rxd_groups[] = {\n+\t\"gpio26\",\n+};\n+\n+static const char * const audio_txmclk_groups[] = {\n+\t\"gpio27\", \"gpio27\",\n+};\n+\n+static const char * const wsa_swrm_groups[] = {\n+\t\"gpio27\", \"gpio28\",\n+};\n+\n+static const char * const blsp2_spi_groups[] = {\n+\t\"gpio27\",\n+};\n+\n+static const char * const audio_txbclk_groups[] = {\n+\t\"gpio28\",\n+};\n+\n+static const char * const blsp0_uart1_groups[] = {\n+\t\"gpio28\", \"gpio29\",\n+};\n+\n+static const char * const audio_txfsync_groups[] = {\n+\t\"gpio29\",\n+};\n+\n+static const char * const audio_txd_groups[] = {\n+\t\"gpio30\",\n+};\n+\n+static const char * const wsis_reset_groups[] = {\n+\t\"gpio30\",\n+};\n+\n+static const char * const blsp2_spi0_groups[] = {\n+\t\"gpio31\", \"gpio32\", \"gpio33\", \"gpio34\",\n+};\n+\n+static const char * const blsp1_uart1_groups[] = {\n+\t\"gpio31\", \"gpio32\", \"gpio33\", \"gpio34\",\n+};\n+\n+static const char * const blsp2_i2c0_groups[] = {\n+\t\"gpio33\", \"gpio34\",\n+};\n+\n+static const char * const mdc_groups[] = {\n+\t\"gpio36\",\n+};\n+\n+static const char * const wsi_clk3_groups[] = {\n+\t\"gpio36\",\n+};\n+\n+static const char * const mdio_groups[] = {\n+\t\"gpio37\",\n+};\n+\n+static const char * const wsi_data3_groups[] = {\n+\t\"gpio37\",\n+};\n+\n+static const char * const qdss_traceclk_b_groups[] = {\n+\t\"gpio39\",\n+};\n+\n+static const char * const reset_out_groups[] = {\n+\t\"gpio40\",\n+};\n+\n+static const char * const qdss_tracectl_b_groups[] = {\n+\t\"gpio40\",\n+};\n+\n+static const char * const pwm0_groups[] = {\n+\t\"gpio42\",\n+};\n+\n+static const char * const qdss_cti_trig_out_b0_groups[] = {\n+\t\"gpio42\",\n+};\n+\n+static const char * const pwm1_groups[] = {\n+\t\"gpio43\",\n+};\n+\n+static const char * const qdss_cti_trig_in_b0_groups[] = {\n+\t\"gpio43\",\n+};\n+\n+static const char * const pwm2_groups[] = {\n+\t\"gpio44\",\n+};\n+\n+static const char * const qdss_cti_trig_out_b1_groups[] = {\n+\t\"gpio44\",\n+};\n+\n+static const char * const pwm3_groups[] = {\n+\t\"gpio45\",\n+};\n+\n+static const char * const qdss_cti_trig_in_b1_groups[] = {\n+\t\"gpio45\",\n+};\n+\n+static const char * const led0_groups[] = {\n+\t\"gpio46\", \"gpio30\", \"gpio10\",\n+};\n+\n+static const char * const led2_groups[] = {\n+\t\"gpio30\",\n+};\n+\n+static const char * const gpio_groups[] = {\n+\t\"gpio0\", \"gpio1\", \"gpio2\", \"gpio3\", \"gpio4\", \"gpio5\", \"gpio6\", \"gpio7\",\n+\t\"gpio8\", \"gpio9\", \"gpio10\", \"gpio11\", \"gpio12\", \"gpio13\", \"gpio14\",\n+\t\"gpio15\", \"gpio16\", \"gpio17\", \"gpio18\", \"gpio19\", \"gpio20\", \"gpio21\",\n+\t\"gpio22\", \"gpio23\", \"gpio24\", \"gpio25\", \"gpio26\", \"gpio27\", \"gpio28\",\n+\t\"gpio29\", \"gpio30\", \"gpio31\", \"gpio32\", \"gpio33\", \"gpio34\", \"gpio35\",\n+\t\"gpio36\", \"gpio37\", \"gpio38\", \"gpio39\", \"gpio40\", \"gpio41\", \"gpio42\",\n+\t\"gpio43\", \"gpio44\", \"gpio45\", \"gpio46\",\n+};\n+\n+static const struct msm_function ipq5018_functions[] = {\n+\tFUNCTION(atest_char),\n+\tFUNCTION(audio_pdm0),\n+\tFUNCTION(audio_pdm1),\n+\tFUNCTION(audio_rxbclk),\n+\tFUNCTION(audio_rxd),\n+\tFUNCTION(audio_rxfsync),\n+\tFUNCTION(audio_rxmclk),\n+\tFUNCTION(audio_txbclk),\n+\tFUNCTION(audio_txd),\n+\tFUNCTION(audio_txfsync),\n+\tFUNCTION(audio_txmclk),\n+\tFUNCTION(blsp0_i2c),\n+\tFUNCTION(blsp0_spi),\n+\tFUNCTION(blsp0_uart0),\n+\tFUNCTION(blsp0_uart1),\n+\tFUNCTION(blsp1_i2c0),\n+\tFUNCTION(blsp1_i2c1),\n+\tFUNCTION(blsp1_spi0),\n+\tFUNCTION(blsp1_spi1),\n+\tFUNCTION(blsp1_uart0),\n+\tFUNCTION(blsp1_uart1),\n+\tFUNCTION(blsp1_uart2),\n+\tFUNCTION(blsp2_i2c0),\n+\tFUNCTION(blsp2_i2c1),\n+\tFUNCTION(blsp2_spi),\n+\tFUNCTION(blsp2_spi0),\n+\tFUNCTION(blsp2_spi1),\n+\tFUNCTION(btss),\n+\tFUNCTION(burn0),\n+\tFUNCTION(burn1),\n+\tFUNCTION(cri_trng),\n+\tFUNCTION(cri_trng0),\n+\tFUNCTION(cri_trng1),\n+\tFUNCTION(cxc_clk),\n+\tFUNCTION(cxc_data),\n+\tFUNCTION(dbg_out),\n+\tFUNCTION(eud_gpio),\n+\tFUNCTION(gcc_plltest),\n+\tFUNCTION(gcc_tlmm),\n+\tFUNCTION(gpio),\n+\tFUNCTION(led0),\n+\tFUNCTION(led2),\n+\tFUNCTION(mac0),\n+\tFUNCTION(mac1),\n+\tFUNCTION(mdc),\n+\tFUNCTION(mdio),\n+\tFUNCTION(pcie0_clk),\n+\tFUNCTION(pcie0_wake),\n+\tFUNCTION(pcie1_clk),\n+\tFUNCTION(pcie1_wake),\n+\tFUNCTION(pll_test),\n+\tFUNCTION(prng_rosc),\n+\tFUNCTION(pwm0),\n+\tFUNCTION(pwm1),\n+\tFUNCTION(pwm2),\n+\tFUNCTION(pwm3),\n+\tFUNCTION(qdss_cti_trig_in_a0),\n+\tFUNCTION(qdss_cti_trig_in_a1),\n+\tFUNCTION(qdss_cti_trig_in_b0),\n+\tFUNCTION(qdss_cti_trig_in_b1),\n+\tFUNCTION(qdss_cti_trig_out_a0),\n+\tFUNCTION(qdss_cti_trig_out_a1),\n+\tFUNCTION(qdss_cti_trig_out_b0),\n+\tFUNCTION(qdss_cti_trig_out_b1),\n+\tFUNCTION(qdss_traceclk_a),\n+\tFUNCTION(qdss_traceclk_b),\n+\tFUNCTION(qdss_tracectl_a),\n+\tFUNCTION(qdss_tracectl_b),\n+\tFUNCTION(qdss_tracedata_a),\n+\tFUNCTION(qdss_tracedata_b),\n+\tFUNCTION(qspi_clk),\n+\tFUNCTION(qspi_cs),\n+\tFUNCTION(qspi_data),\n+\tFUNCTION(reset_out),\n+\tFUNCTION(sdc1_clk),\n+\tFUNCTION(sdc1_cmd),\n+\tFUNCTION(sdc1_data),\n+\tFUNCTION(wci_txd),\n+\tFUNCTION(wci_rxd),\n+\tFUNCTION(wsa_swrm),\n+\tFUNCTION(wsi_clk3),\n+\tFUNCTION(wsi_data3),\n+\tFUNCTION(wsis_reset),\n+\tFUNCTION(xfem),\n+};\n+\n+static const struct msm_pingroup ipq5018_groups[] = {\n+\tPINGROUP(0, atest_char, _, qdss_cti_trig_out_a0, wci_txd, wci_rxd, xfem, _, _, _),\n+\tPINGROUP(1, atest_char, _, qdss_cti_trig_in_a0, wci_txd, wci_rxd, xfem, _, _, _),\n+\tPINGROUP(2, atest_char, _, qdss_cti_trig_out_a1, wci_txd, wci_rxd, xfem, _, _, _),\n+\tPINGROUP(3, atest_char, _, qdss_cti_trig_in_a1, wci_txd, wci_rxd, xfem, _, _, _),\n+\tPINGROUP(4, sdc1_data, qspi_data, blsp1_spi1, btss, dbg_out, qdss_traceclk_a, _, burn0, _),\n+\tPINGROUP(5, sdc1_data, qspi_data, cxc_clk, blsp1_spi1, blsp1_i2c1, btss, _, qdss_tracectl_a, _),\n+\tPINGROUP(6, sdc1_data, qspi_data, cxc_data, blsp1_spi1, blsp1_i2c1, btss, _, qdss_tracedata_a, _),\n+\tPINGROUP(7, sdc1_data, qspi_data, mac0, blsp1_spi1, btss, _, qdss_tracedata_a, _, _),\n+\tPINGROUP(8, sdc1_cmd, qspi_cs, mac1, btss, _, qdss_tracedata_a, _, _, _),\n+\tPINGROUP(9, sdc1_clk, qspi_clk, _, qdss_tracedata_a, _, _, _, _, _),\n+\tPINGROUP(10, blsp0_spi, blsp1_uart0, led0, gcc_plltest, qdss_tracedata_a, _, _, _, _),\n+\tPINGROUP(11, blsp0_spi, blsp1_uart0, _, gcc_tlmm, qdss_tracedata_a, _, _, _, _),\n+\tPINGROUP(12, blsp0_spi, blsp0_i2c, blsp1_uart0, _, gcc_plltest, qdss_tracedata_a, _, _, _),\n+\tPINGROUP(13, blsp0_spi, blsp0_i2c, blsp1_uart0, _, qdss_tracedata_a, _, _, _, _),\n+\tPINGROUP(14, pcie0_clk, _, _, cri_trng0, qdss_tracedata_a, _, _, _, _),\n+\tPINGROUP(15, _, _, cri_trng1, qdss_tracedata_a, _, _, _, _, _),\n+\tPINGROUP(16, pcie0_wake, _, _, cri_trng, qdss_tracedata_a, _, _, _, _),\n+\tPINGROUP(17, pcie1_clk, btss, _, prng_rosc, qdss_tracedata_a, _, _, _, _),\n+\tPINGROUP(18, blsp1_spi0, btss, _, qdss_tracedata_a, _, _, _, _, _),\n+\tPINGROUP(19, pcie1_wake, blsp1_spi0, blsp1_i2c0, btss, _, qdss_tracedata_a, _, _, _),\n+\tPINGROUP(20, blsp0_uart0, blsp1_spi0, blsp1_i2c0, _, qdss_tracedata_a, _, _, _, _),\n+\tPINGROUP(21, blsp0_uart0, blsp1_spi0, _, qdss_tracedata_a, _, _, _, _, _),\n+\tPINGROUP(22, _, pll_test, eud_gpio, _, _, _, _, _, _),\n+\tPINGROUP(23, audio_rxmclk, audio_pdm0, audio_rxmclk, blsp2_spi1, blsp1_uart2, btss, _, qdss_tracedata_b, _),\n+\tPINGROUP(24, audio_rxbclk, audio_pdm0, blsp2_spi1, blsp1_uart2, btss, _, qdss_tracedata_b, _, _),\n+\tPINGROUP(25, audio_rxfsync, audio_pdm1, blsp2_i2c1, blsp2_spi1, blsp1_uart2, btss, _, qdss_tracedata_b, _),\n+\tPINGROUP(26, audio_rxd, audio_pdm1, blsp2_i2c1, blsp2_spi1, blsp1_uart2, btss, _, qdss_tracedata_b, _),\n+\tPINGROUP(27, audio_txmclk, wsa_swrm, audio_txmclk, blsp2_spi, btss, _, qdss_tracedata_b, _, _),\n+\tPINGROUP(28, audio_txbclk, wsa_swrm, blsp0_uart1, btss, qdss_tracedata_b, _, _, _, _),\n+\tPINGROUP(29, audio_txfsync, _, blsp0_uart1, _, qdss_tracedata_b, _, _, _, _),\n+\tPINGROUP(30, audio_txd, led2, led0, _, _, _, _, _, _),\n+\tPINGROUP(31, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio, _, _, _, _),\n+\tPINGROUP(32, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio, _, _, _, _),\n+\tPINGROUP(33, blsp2_i2c0, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio, _, _, _),\n+\tPINGROUP(34, blsp2_i2c0, blsp2_spi0, blsp1_uart1, _, qdss_tracedata_b, eud_gpio, _, _, _),\n+\tPINGROUP(35, _, qdss_tracedata_b, eud_gpio, _, _, _, _, _, _),\n+\tPINGROUP(36, mdc, qdss_tracedata_b, _, wsi_clk3, _, _, _, _, _),\n+\tPINGROUP(37, mdio, atest_char, qdss_tracedata_b, _, wsi_data3, _, _, _, _),\n+\tPINGROUP(38, qdss_tracedata_b, _, _, _, _, _, _, _, _),\n+\tPINGROUP(39, qdss_traceclk_b, _, _, _, _, _, _, _, _),\n+\tPINGROUP(40, reset_out, qdss_tracectl_b, _, _, _, _, _, _, _),\n+\tPINGROUP(41, _, _, _, _, _, _, _, _, _),\n+\tPINGROUP(42, pwm0, qdss_cti_trig_out_b0, wci_txd, wci_rxd, xfem, _, _, _, _),\n+\tPINGROUP(43, pwm1, qdss_cti_trig_in_b0, wci_txd, wci_rxd, xfem, _, _, _, _),\n+\tPINGROUP(44, pwm2, qdss_cti_trig_out_b1, wci_txd, wci_rxd, xfem, _, _, _, _),\n+\tPINGROUP(45, pwm3, qdss_cti_trig_in_b1, wci_txd, wci_rxd, xfem, _, _, _, _),\n+\tPINGROUP(46, led0, _, _, _, _, _, _, _, _),\n+};\n+\n+static const struct msm_pinctrl_soc_data ipq5018_pinctrl = {\n+\t.pins = ipq5018_pins,\n+\t.npins = ARRAY_SIZE(ipq5018_pins),\n+\t.functions = ipq5018_functions,\n+\t.nfunctions = ARRAY_SIZE(ipq5018_functions),\n+\t.groups = ipq5018_groups,\n+\t.ngroups = ARRAY_SIZE(ipq5018_groups),\n+\t.ngpios = 47,\n+};\n+\n+static int ipq5018_pinctrl_probe(struct platform_device *pdev)\n+{\n+\treturn msm_pinctrl_probe(pdev, &ipq5018_pinctrl);\n+}\n+\n+static const struct of_device_id ipq5018_pinctrl_of_match[] = {\n+\t{ .compatible = \"qcom,ipq5018-tlmm\", },\n+\t{ },\n+};\n+\n+static struct platform_driver ipq5018_pinctrl_driver = {\n+\t.driver = {\n+\t\t.name = \"ipq5018-tlmm\",\n+\t\t.of_match_table = ipq5018_pinctrl_of_match,\n+\t},\n+\t.probe = ipq5018_pinctrl_probe,\n+\t.remove = msm_pinctrl_remove,\n+};\n+\n+static int __init ipq5018_pinctrl_init(void)\n+{\n+\treturn platform_driver_register(&ipq5018_pinctrl_driver);\n+}\n+arch_initcall(ipq5018_pinctrl_init);\n+\n+static void __exit ipq5018_pinctrl_exit(void)\n+{\n+\tplatform_driver_unregister(&ipq5018_pinctrl_driver);\n+}\n+module_exit(ipq5018_pinctrl_exit);\n+\n+MODULE_DESCRIPTION(\"Qualcomm Technologies Inc ipq5018 pinctrl driver\");\n+MODULE_LICENSE(\"GPL v2\");\n+MODULE_DEVICE_TABLE(of, ipq5018_pinctrl_of_match);\n", "prefixes": [ "V3", "4/9" ] }