Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 1767874,
    "url": "http://patchwork.ozlabs.org/api/patches/1767874/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20230411182510.22158-11-afd@ti.com/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20230411182510.22158-11-afd@ti.com>",
    "list_archive_url": null,
    "date": "2023-04-11T18:25:03",
    "name": "[10/17] arm: dts: am3x: Update IOPAD to PADCONF to sync with v6.3-rc6",
    "commit_ref": "2657c52e08872f3c726185ecc5e8e6064ffbc3d5",
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "2aff726d88263980fa46a6745e44b32dea13bd19",
    "submitter": {
        "id": 67226,
        "url": "http://patchwork.ozlabs.org/api/people/67226/?format=api",
        "name": "Andrew Davis",
        "email": "afd@ti.com"
    },
    "delegate": {
        "id": 3651,
        "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api",
        "username": "trini",
        "first_name": "Tom",
        "last_name": "Rini",
        "email": "trini@ti.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20230411182510.22158-11-afd@ti.com/mbox/",
    "series": [
        {
            "id": 350384,
            "url": "http://patchwork.ozlabs.org/api/series/350384/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=350384",
            "date": "2023-04-11T18:24:56",
            "name": "Sync TI Device Trees with Linux v6.3-rc6",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/350384/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/1767874/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/1767874/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<u-boot-bounces@lists.denx.de>",
        "X-Original-To": "incoming@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming@legolas.ozlabs.org",
        "Authentication-Results": [
            "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)",
            "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256\n header.s=ti-com-17Q1 header.b=YPP0SkAI;\n\tdkim-atps=neutral",
            "phobos.denx.de;\n dmarc=pass (p=quarantine dis=none) header.from=ti.com",
            "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de",
            "phobos.denx.de;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=ti.com header.i=@ti.com header.b=\"YPP0SkAI\";\n\tdkim-atps=neutral",
            "phobos.denx.de;\n dmarc=pass (p=quarantine dis=none) header.from=ti.com",
            "phobos.denx.de; spf=pass smtp.mailfrom=afd@ti.com"
        ],
        "Received": [
            "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature ECDSA (P-384) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4Px2kz62mlz1yZZ\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 12 Apr 2023 09:54:51 +1000 (AEST)",
            "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id CBD5085F50;\n\tWed, 12 Apr 2023 01:54:43 +0200 (CEST)",
            "by phobos.denx.de (Postfix, from userid 109)\n id 4DA5985F52; Tue, 11 Apr 2023 20:26:42 +0200 (CEST)",
            "from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id EB89585F6D\n for <u-boot@lists.denx.de>; Tue, 11 Apr 2023 20:25:22 +0200 (CEST)",
            "from lelv0266.itg.ti.com ([10.180.67.225])\n by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 33BIPHvK091005;\n Tue, 11 Apr 2023 13:25:17 -0500",
            "from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32])\n by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 33BIPHY6075480\n (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL);\n Tue, 11 Apr 2023 13:25:17 -0500",
            "from DFLE100.ent.ti.com (10.64.6.21) by DFLE111.ent.ti.com\n (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 11\n Apr 2023 13:25:16 -0500",
            "from fllv0040.itg.ti.com (10.64.41.20) by DFLE100.ent.ti.com\n (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via\n Frontend Transport; Tue, 11 Apr 2023 13:25:16 -0500",
            "from ula0226330.dal.design.ti.com (ileaxei01-snat.itg.ti.com\n [10.180.69.5])\n by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 33BIPAC4109488;\n Tue, 11 Apr 2023 13:25:15 -0500"
        ],
        "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de",
        "X-Spam-Level": "",
        "X-Spam-Status": "No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,\n DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,\n SPF_PASS,UPPERCASE_50_75 autolearn=no autolearn_force=no version=3.4.2",
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com;\n s=ti-com-17Q1; t=1681237517;\n bh=rTOcjAHX+n/Yqsd0Wsft1HfzjxDoCOUjsiIdi83Kyo8=;\n h=From:To:CC:Subject:Date:In-Reply-To:References;\n b=YPP0SkAIYPWybZixf66b+gGb0xZjQ8bVcpFZcL0bdDdd05fFAcfyaM4AsbJ2cBmFG\n in6KcLcXKM4MPiNPJpgzVmVHShbtFgB5VkuuTrEAqFTrKcr2Uta1BKCGbF+/jmCqH2\n ApHIKAF+KIALJkgm7BDnX5iecsDvNZPuXO3jyR1U=",
        "From": "Andrew Davis <afd@ti.com>",
        "To": "Simon Glass <sjg@chromium.org>, Tom Rini <trini@konsulko.com>, Nishanth\n Menon <nm@ti.com>, Vignesh Raghavendra <vigneshr@ti.com>,\n <u-boot@lists.denx.de>",
        "CC": "Andrew Davis <afd@ti.com>",
        "Subject": "[PATCH 10/17] arm: dts: am3x: Update IOPAD to PADCONF to sync with\n v6.3-rc6",
        "Date": "Tue, 11 Apr 2023 13:25:03 -0500",
        "Message-ID": "<20230411182510.22158-11-afd@ti.com>",
        "X-Mailer": "git-send-email 2.39.2",
        "In-Reply-To": "<20230411182510.22158-1-afd@ti.com>",
        "References": "<20230411182510.22158-1-afd@ti.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-EXCLAIMER-MD-CONFIG": "e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180",
        "X-Mailman-Approved-At": "Wed, 12 Apr 2023 01:54:41 +0200",
        "X-BeenThere": "u-boot@lists.denx.de",
        "X-Mailman-Version": "2.1.39",
        "Precedence": "list",
        "List-Id": "U-Boot discussion <u-boot.lists.denx.de>",
        "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>",
        "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>",
        "List-Post": "<mailto:u-boot@lists.denx.de>",
        "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>",
        "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>",
        "Errors-To": "u-boot-bounces@lists.denx.de",
        "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>",
        "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de",
        "X-Virus-Status": "Clean"
    },
    "content": "Several DTS files have been updated in the Linux kernel with a new\nPADCONF macro replacing the IOPAD version. Sync for the same here.\n\nSigned-off-by: Andrew Davis <afd@ti.com>\n---\n arch/arm/dts/am335x-base0033.dts        |  48 ++--\n arch/arm/dts/am335x-chiliboard.dts      |  66 +++---\n arch/arm/dts/am335x-chilisom.dtsi       |  34 +--\n arch/arm/dts/am335x-evm.dts             | 212 +++++++++---------\n arch/arm/dts/am335x-evmsk.dts           | 278 ++++++++++++------------\n arch/arm/dts/am335x-icev2.dts           | 104 ++++-----\n arch/arm/dts/am335x-igep0033.dtsi       |  40 ++--\n arch/arm/dts/am335x-osd335x-common.dtsi |   4 +-\n arch/arm/dts/am335x-pdu001.dts          | 170 +++++++--------\n arch/arm/dts/am335x-phycore-som.dtsi    |  60 ++---\n arch/arm/dts/am335x-pocketbeagle.dts    |  54 ++---\n arch/arm/dts/am335x-regor.dtsi          |  80 +++----\n arch/arm/dts/am335x-shc.dts             | 226 ++++++++++---------\n arch/arm/dts/am335x-sl50.dts            | 132 +++++------\n arch/arm/dts/am335x-wega.dtsi           |  68 +++---\n 15 files changed, 787 insertions(+), 789 deletions(-)",
    "diff": "diff --git a/arch/arm/dts/am335x-base0033.dts b/arch/arm/dts/am335x-base0033.dts\nindex 0f5f2dea898..89c00ce42c2 100644\n--- a/arch/arm/dts/am335x-base0033.dts\n+++ b/arch/arm/dts/am335x-base0033.dts\n@@ -43,39 +43,39 @@\n &am33xx_pinmux {\n \tnxp_hdmi_pins: pinmux_nxp_hdmi_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE3)\t/* xdma_event_intr0.clkout1 */\n-\t\t\tAM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0)\t/* lcd_data0 */\n-\t\t\tAM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0)\t/* lcd_data1 */\n-\t\t\tAM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0)\t/* lcd_data2 */\n-\t\t\tAM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0)\t/* lcd_data3 */\n-\t\t\tAM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0)\t/* lcd_data4 */\n-\t\t\tAM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0)\t/* lcd_data5 */\n-\t\t\tAM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0)\t/* lcd_data6 */\n-\t\t\tAM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0)\t/* lcd_data7 */\n-\t\t\tAM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0)\t/* lcd_data8 */\n-\t\t\tAM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0)\t/* lcd_data9 */\n-\t\t\tAM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0)\t/* lcd_data10 */\n-\t\t\tAM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0)\t/* lcd_data11 */\n-\t\t\tAM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0)\t/* lcd_data12 */\n-\t\t\tAM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0)\t/* lcd_data13 */\n-\t\t\tAM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0)\t/* lcd_data14 */\n-\t\t\tAM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0)\t/* lcd_data15 */\n-\t\t\tAM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0)\t/* lcd_vsync */\n-\t\t\tAM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0)\t/* lcd_hsync */\n-\t\t\tAM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0)\t/* lcd_pclk */\n-\t\t\tAM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0)\t/* lcd_ac_bias_en */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3)\t/* xdma_event_intr0.clkout1 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)\n \t\t>;\n \t};\n \tnxp_hdmi_off_pins: pinmux_nxp_hdmi_off_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE3)\t/* xdma_event_intr0.clkout1 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE3)\t/* xdma_event_intr0.clkout1 */\n \t\t>;\n \t};\n \n \tleds_base_pins: pinmux_leds_base_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE7)\t/* gpmc_a5.gpio1_21 */\n-\t\t\tAM33XX_IOPAD(0x888, PIN_OUTPUT_PULLDOWN | MUX_MODE7)\t/* gpmc_csn3.gpio2_0 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_a5.gpio1_21 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_OUTPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_csn3.gpio2_0 */\n \t\t>;\n \t};\n };\ndiff --git a/arch/arm/dts/am335x-chiliboard.dts b/arch/arm/dts/am335x-chiliboard.dts\nindex 862cacceb62..129a02b597c 100644\n--- a/arch/arm/dts/am335x-chiliboard.dts\n+++ b/arch/arm/dts/am335x-chiliboard.dts\n@@ -34,79 +34,79 @@\n &am33xx_pinmux {\n \tuart0_pins: pinmux_uart0_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)\t/* uart0_rxd.uart0_rxd */\n-\t\t\tAM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)\t/* uart0_txd.uart0_txd */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)\n \t\t>;\n \t};\n \n \tcpsw_default: cpsw_default {\n \t\tpinctrl-single,pins = <\n \t\t\t/* Slave 1 */\n-\t\t\tAM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1)  /* mii1_crs.rmii1_crs */\n-\t\t\tAM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE1)\t/* mii1_rxerr.rmii1_rxerr */\n-\t\t\tAM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE1)\t/* mii1_txen.rmii1_txen */\n-\t\t\tAM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE1)\t/* mii1_txd1.rmii1_txd1 */\n-\t\t\tAM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE1)\t/* mii1_txd0.rmii1_txd0 */\n-\t\t\tAM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE1)\t/* mii1_rxd1.rmii1_rxd1 */\n-\t\t\tAM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE1)\t/* mii1_rxd0.rmii1_rxd0 */\n-\t\t\tAM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0)\t/* rmii1_ref_clk.rmii_ref_clk */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)\n \t\t>;\n \t};\n \n \tcpsw_sleep: cpsw_sleep {\n \t\tpinctrl-single,pins = <\n \t\t\t/* Slave 1 reset value */\n-\t\t\tAM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)\n \t\t>;\n \t};\n \n \tdavinci_mdio_default: davinci_mdio_default {\n \t\tpinctrl-single,pins = <\n \t\t\t/* mdio_data.mdio_data */\n-\t\t\tAM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)\n \t\t\t/* mdio_clk.mdio_clk */\n-\t\t\tAM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)\n \t\t>;\n \t};\n \n \tdavinci_mdio_sleep: davinci_mdio_sleep {\n \t\tpinctrl-single,pins = <\n \t\t\t/* MDIO reset value */\n-\t\t\tAM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)\n \t\t>;\n \t};\n \n \tusb1_drvvbus: usb1_drvvbus {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0xa34, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* usb1_drvvbus.usb1_drvvbus */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_USB1_DRVVBUS, PIN_OUTPUT_PULLDOWN, MUX_MODE0)\n \t\t>;\n \t};\n \n \tsd_pins: pinmux_sd_card {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x8f0, PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */\n-\t\t\tAM33XX_IOPAD(0x8f4, PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */\n-\t\t\tAM33XX_IOPAD(0x8f8, PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */\n-\t\t\tAM33XX_IOPAD(0x8fc, PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */\n-\t\t\tAM33XX_IOPAD(0x900, PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */\n-\t\t\tAM33XX_IOPAD(0x904, PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */\n-\t\t\tAM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) /* spi0_cs1.gpio0_6 */\n \t\t>;\n \t};\n \n \tled_gpio_pins: led_gpio_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x9e4, PIN_OUTPUT | MUX_MODE7) /* emu0.gpio3_7 */\n-\t\t\tAM33XX_IOPAD(0x9e8, PIN_OUTPUT | MUX_MODE7) /* emu1.gpio3_8 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_EMU0, PIN_OUTPUT, MUX_MODE7) /* emu0.gpio3_7 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_EMU1, PIN_OUTPUT, MUX_MODE7) /* emu1.gpio3_8 */\n \t\t>;\n \t};\n };\ndiff --git a/arch/arm/dts/am335x-chilisom.dtsi b/arch/arm/dts/am335x-chilisom.dtsi\nindex 3f2cb5ec962..43b61e43ed1 100644\n--- a/arch/arm/dts/am335x-chilisom.dtsi\n+++ b/arch/arm/dts/am335x-chilisom.dtsi\n@@ -27,28 +27,28 @@\n \n \ti2c0_pins: pinmux_i2c0_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)\t/* i2c0_sda.i2c0_sda */\n-\t\t\tAM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)\t/* i2c0_scl.i2c0_scl */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)\n \t\t>;\n \t};\n \n \tnandflash_pins: nandflash_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x800, PIN_INPUT_PULLDOWN | MUX_MODE0)\t/* gpmc_ad0.gpmc_ad0 */\n-\t\t\tAM33XX_IOPAD(0x804, PIN_INPUT_PULLDOWN | MUX_MODE0)\t/* gpmc_ad1.gpmc_ad1 */\n-\t\t\tAM33XX_IOPAD(0x808, PIN_INPUT_PULLDOWN | MUX_MODE0)\t/* gpmc_ad2.gpmc_ad2 */\n-\t\t\tAM33XX_IOPAD(0x80c, PIN_INPUT_PULLDOWN | MUX_MODE0)\t/* gpmc_ad3.gpmc_ad3 */\n-\t\t\tAM33XX_IOPAD(0x810, PIN_INPUT_PULLDOWN | MUX_MODE0)\t/* gpmc_ad4.gpmc_ad4 */\n-\t\t\tAM33XX_IOPAD(0x814, PIN_INPUT_PULLDOWN | MUX_MODE0)\t/* gpmc_ad5.gpmc_ad5 */\n-\t\t\tAM33XX_IOPAD(0x818, PIN_INPUT_PULLDOWN | MUX_MODE0)\t/* gpmc_ad6.gpmc_ad6 */\n-\t\t\tAM33XX_IOPAD(0x81c, PIN_INPUT_PULLDOWN | MUX_MODE0)\t/* gpmc_ad7.gpmc_ad7 */\n-\n-\t\t\tAM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)\t/* gpmc_wait0.gpmc_wait0 */\n-\t\t\tAM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE0)\t/* gpmc_csn0.gpmc_csn0 */\n-\t\t\tAM33XX_IOPAD(0x890, PIN_OUTPUT_PULLUP | MUX_MODE0)\t/* gpmc_advn_ale.gpmc_advn_ale */\n-\t\t\tAM33XX_IOPAD(0x894, PIN_OUTPUT_PULLUP | MUX_MODE0)\t/* gpmc_oen_ren.gpmc_oen_ren */\n-\t\t\tAM33XX_IOPAD(0x898, PIN_OUTPUT_PULLUP | MUX_MODE0)\t/* gpmc_wen.gpmc_wen */\n-\t\t\tAM33XX_IOPAD(0x89c, PIN_OUTPUT_PULLUP | MUX_MODE0)\t/* gpmc_be0n_cle.gpmc_be0n_cle */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLDOWN, MUX_MODE0)\n+\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT_PULLUP, MUX_MODE0)\n \t\t>;\n \t};\n };\ndiff --git a/arch/arm/dts/am335x-evm.dts b/arch/arm/dts/am335x-evm.dts\nindex 5b756d40d73..737460eb867 100644\n--- a/arch/arm/dts/am335x-evm.dts\n+++ b/arch/arm/dts/am335x-evm.dts\n@@ -155,206 +155,206 @@\n \n \tmatrix_keypad_s0: matrix_keypad_s0 {\n \t\tpinctrl-single,pins = <\n-\t\t\t0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)\t/* gpmc_a5.gpio1_21 */\n-\t\t\t0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)\t/* gpmc_a6.gpio1_22 */\n-\t\t\t0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)\t/* gpmc_a9.gpio1_25 */\n-\t\t\t0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)\t/* gpmc_a10.gpio1_26 */\n-\t\t\t0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)\t/* gpmc_a11.gpio1_27 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_a5.gpio1_21 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_a6.gpio1_22 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_a9.gpio1_25 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_a10.gpio1_26 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_a11.gpio1_27 */\n \t\t>;\n \t};\n \n \tvolume_keys_s0: volume_keys_s0 {\n \t\tpinctrl-single,pins = <\n-\t\t\t0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7)\t/* spi0_sclk.gpio0_2 */\n-\t\t\t0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7)\t/* spi0_d0.gpio0_3 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* spi0_sclk.gpio0_2 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* spi0_d0.gpio0_3 */\n \t\t>;\n \t};\n \n \ti2c0_pins: pinmux_i2c0_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\t0x188 (PIN_INPUT_PULLUP | MUX_MODE0)\t/* i2c0_sda.i2c0_sda */\n-\t\t\t0x18c (PIN_INPUT_PULLUP | MUX_MODE0)\t/* i2c0_scl.i2c0_scl */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)\t/* i2c0_sda.i2c0_sda */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)\t/* i2c0_scl.i2c0_scl */\n \t\t>;\n \t};\n \n \ti2c1_pins: pinmux_i2c1_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\t0x158 (PIN_INPUT_PULLUP | MUX_MODE2)\t/* spi0_d1.i2c1_sda */\n-\t\t\t0x15c (PIN_INPUT_PULLUP | MUX_MODE2)\t/* spi0_cs0.i2c1_scl */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2)\t/* spi0_d1.i2c1_sda */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2)\t/* spi0_cs0.i2c1_scl */\n \t\t>;\n \t};\n \n \tuart0_pins: pinmux_uart0_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\t0x170 (PIN_INPUT_PULLUP | MUX_MODE0)\t/* uart0_rxd.uart0_rxd */\n-\t\t\t0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)\t/* uart0_txd.uart0_txd */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)\n \t\t>;\n \t};\n \n \tuart1_pins: pinmux_uart1_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\t0x178 (PIN_INPUT | MUX_MODE0)\t\t/* uart1_ctsn.uart1_ctsn */\n-\t\t\t0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0)\t/* uart1_rtsn.uart1_rtsn */\n-\t\t\t0x180 (PIN_INPUT_PULLUP | MUX_MODE0)\t/* uart1_rxd.uart1_rxd */\n-\t\t\t0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0)\t/* uart1_txd.uart1_txd */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)\n \t\t>;\n \t};\n \n \tclkout2_pin: pinmux_clkout2_pin {\n \t\tpinctrl-single,pins = <\n-\t\t\t0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3)\t/* xdma_event_intr1.clkout2 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3)\t/* xdma_event_intr1.clkout2 */\n \t\t>;\n \t};\n \n \tnandflash_pins_s0: nandflash_pins_s0 {\n \t\tpinctrl-single,pins = <\n-\t\t\t0x0 (PIN_INPUT_PULLUP | MUX_MODE0)\t/* gpmc_ad0.gpmc_ad0 */\n-\t\t\t0x4 (PIN_INPUT_PULLUP | MUX_MODE0)\t/* gpmc_ad1.gpmc_ad1 */\n-\t\t\t0x8 (PIN_INPUT_PULLUP | MUX_MODE0)\t/* gpmc_ad2.gpmc_ad2 */\n-\t\t\t0xc (PIN_INPUT_PULLUP | MUX_MODE0)\t/* gpmc_ad3.gpmc_ad3 */\n-\t\t\t0x10 (PIN_INPUT_PULLUP | MUX_MODE0)\t/* gpmc_ad4.gpmc_ad4 */\n-\t\t\t0x14 (PIN_INPUT_PULLUP | MUX_MODE0)\t/* gpmc_ad5.gpmc_ad5 */\n-\t\t\t0x18 (PIN_INPUT_PULLUP | MUX_MODE0)\t/* gpmc_ad6.gpmc_ad6 */\n-\t\t\t0x1c (PIN_INPUT_PULLUP | MUX_MODE0)\t/* gpmc_ad7.gpmc_ad7 */\n-\t\t\t0x70 (PIN_INPUT_PULLUP | MUX_MODE0)\t/* gpmc_wait0.gpmc_wait0 */\n-\t\t\t0x74 (PIN_INPUT_PULLUP | MUX_MODE7)\t/* gpmc_wpn.gpio0_30 */\n-\t\t\t0x7c (PIN_OUTPUT | MUX_MODE0)\t\t/* gpmc_csn0.gpmc_csn0  */\n-\t\t\t0x90 (PIN_OUTPUT | MUX_MODE0)\t\t/* gpmc_advn_ale.gpmc_advn_ale */\n-\t\t\t0x94 (PIN_OUTPUT | MUX_MODE0)\t\t/* gpmc_oen_ren.gpmc_oen_ren */\n-\t\t\t0x98 (PIN_OUTPUT | MUX_MODE0)\t\t/* gpmc_wen.gpmc_wen */\n-\t\t\t0x9c (PIN_OUTPUT | MUX_MODE0)\t\t/* gpmc_be0n_cle.gpmc_be0n_cle */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7)\t/* gpmc_wpn.gpio0_31 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)\n \t\t>;\n \t};\n \n \tecap0_pins: backlight_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\t0x164 0x0\t/* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, 0x0, MUX_MODE0)\n \t\t>;\n \t};\n \n \tcpsw_default: cpsw_default {\n \t\tpinctrl-single,pins = <\n \t\t\t/* Slave 1 */\n-\t\t\t0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)\t/* mii1_txen.rgmii1_tctl */\n-\t\t\t0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2)\t/* mii1_rxdv.rgmii1_rctl */\n-\t\t\t0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2)\t/* mii1_txd3.rgmii1_td3 */\n-\t\t\t0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)\t/* mii1_txd2.rgmii1_td2 */\n-\t\t\t0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)\t/* mii1_txd1.rgmii1_td1 */\n-\t\t\t0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2)\t/* mii1_txd0.rgmii1_td0 */\n-\t\t\t0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2)\t/* mii1_txclk.rgmii1_tclk */\n-\t\t\t0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2)\t/* mii1_rxclk.rgmii1_rclk */\n-\t\t\t0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2)\t/* mii1_rxd3.rgmii1_rd3 */\n-\t\t\t0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2)\t/* mii1_rxd2.rgmii1_rd2 */\n-\t\t\t0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2)\t/* mii1_rxd1.rgmii1_rd1 */\n-\t\t\t0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2)\t/* mii1_rxd0.rgmii1_rd0 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* mii1_txen.rgmii1_tctl */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* mii1_rxdv.rgmii1_rctl */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* mii1_txd3.rgmii1_td3 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* mii1_txd2.rgmii1_td2 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* mii1_txd1.rgmii1_td1 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* mii1_txd0.rgmii1_td0 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* mii1_txclk.rgmii1_tclk */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* mii1_rxclk.rgmii1_rclk */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* mii1_rxd3.rgmii1_rd3 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* mii1_rxd2.rgmii1_rd2 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* mii1_rxd1.rgmii1_rd1 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* mii1_rxd0.rgmii1_rd0 */\n \t\t>;\n \t};\n \n \tcpsw_sleep: cpsw_sleep {\n \t\tpinctrl-single,pins = <\n \t\t\t/* Slave 1 reset value */\n-\t\t\t0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\t0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\t0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\t0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\t0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\t0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\t0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\t0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\t0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\t0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\t0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\t0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)\n \t\t>;\n \t};\n \n \tdavinci_mdio_default: davinci_mdio_default {\n \t\tpinctrl-single,pins = <\n \t\t\t/* MDIO */\n-\t\t\t0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)\t/* mdio_data.mdio_data */\n-\t\t\t0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0)\t\t\t/* mdio_clk.mdio_clk */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)\n \t\t>;\n \t};\n \n \tdavinci_mdio_sleep: davinci_mdio_sleep {\n \t\tpinctrl-single,pins = <\n \t\t\t/* MDIO reset value */\n-\t\t\t0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\t0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)\n \t\t>;\n \t};\n \n \tmmc1_pins: pinmux_mmc1_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\t0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7)\t\t/* spi0_cs1.gpio0_6 */\n \t\t>;\n \t};\n \n \tmmc3_pins: pinmux_mmc3_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\t0x44 (PIN_INPUT_PULLUP | MUX_MODE3)\t/* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */\n-\t\t\t0x48 (PIN_INPUT_PULLUP | MUX_MODE3)\t/* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */\n-\t\t\t0x4C (PIN_INPUT_PULLUP | MUX_MODE3)\t/* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */\n-\t\t\t0x78 (PIN_INPUT_PULLUP | MUX_MODE3)\t/* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */\n-\t\t\t0x88 (PIN_INPUT_PULLUP | MUX_MODE3)\t/* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */\n-\t\t\t0x8C (PIN_INPUT_PULLUP | MUX_MODE3)\t/* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE3)\t/* gpmc_a1.mmc2_dat0, INPUT_PULLUP | MODE3 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLUP, MUX_MODE3)\t/* gpmc_a2.mmc2_dat1, INPUT_PULLUP | MODE3 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLUP, MUX_MODE3)\t/* gpmc_a3.mmc2_dat2, INPUT_PULLUP | MODE3 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLUP, MUX_MODE3)\t/* gpmc_ben1.mmc2_dat3, INPUT_PULLUP | MODE3 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT_PULLUP, MUX_MODE3)\t/* gpmc_csn3.mmc2_cmd, INPUT_PULLUP | MODE3 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT_PULLUP, MUX_MODE3)\t/* gpmc_clk.mmc2_clk, INPUT_PULLUP | MODE3 */\n \t\t>;\n \t};\n \n \twlan_pins: pinmux_wlan_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\t0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7)\t/* gpmc_a0.gpio1_16 */\n-\t\t\t0x19C (PIN_INPUT | MUX_MODE7)\t\t/* mcasp0_ahclkr.gpio3_17 */\n-\t\t\t0x1AC (PIN_OUTPUT_PULLDOWN | MUX_MODE7)\t/* mcasp0_ahclkx.gpio3_21 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_a0.gpio1_16 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_INPUT, MUX_MODE7)\t\t/* mcasp0_ahclkr.gpio3_17 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE7)\t/* mcasp0_ahclkx.gpio3_21 */\n \t\t>;\n \t};\n \n \tlcd_pins_s0: lcd_pins_s0 {\n \t\tpinctrl-single,pins = <\n-\t\t\t0x20 (PIN_OUTPUT | MUX_MODE1)\t\t/* gpmc_ad8.lcd_data23 */\n-\t\t\t0x24 (PIN_OUTPUT | MUX_MODE1)\t\t/* gpmc_ad9.lcd_data22 */\n-\t\t\t0x28 (PIN_OUTPUT | MUX_MODE1)\t\t/* gpmc_ad10.lcd_data21 */\n-\t\t\t0x2c (PIN_OUTPUT | MUX_MODE1)\t\t/* gpmc_ad11.lcd_data20 */\n-\t\t\t0x30 (PIN_OUTPUT | MUX_MODE1)\t\t/* gpmc_ad12.lcd_data19 */\n-\t\t\t0x34 (PIN_OUTPUT | MUX_MODE1)\t\t/* gpmc_ad13.lcd_data18 */\n-\t\t\t0x38 (PIN_OUTPUT | MUX_MODE1)\t\t/* gpmc_ad14.lcd_data17 */\n-\t\t\t0x3c (PIN_OUTPUT | MUX_MODE1)\t\t/* gpmc_ad15.lcd_data16 */\n-\t\t\t0xa0 (PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_data0.lcd_data0 */\n-\t\t\t0xa4 (PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_data1.lcd_data1 */\n-\t\t\t0xa8 (PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_data2.lcd_data2 */\n-\t\t\t0xac (PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_data3.lcd_data3 */\n-\t\t\t0xb0 (PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_data4.lcd_data4 */\n-\t\t\t0xb4 (PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_data5.lcd_data5 */\n-\t\t\t0xb8 (PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_data6.lcd_data6 */\n-\t\t\t0xbc (PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_data7.lcd_data7 */\n-\t\t\t0xc0 (PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_data8.lcd_data8 */\n-\t\t\t0xc4 (PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_data9.lcd_data9 */\n-\t\t\t0xc8 (PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_data10.lcd_data10 */\n-\t\t\t0xcc (PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_data11.lcd_data11 */\n-\t\t\t0xd0 (PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_data12.lcd_data12 */\n-\t\t\t0xd4 (PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_data13.lcd_data13 */\n-\t\t\t0xd8 (PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_data14.lcd_data14 */\n-\t\t\t0xdc (PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_data15.lcd_data15 */\n-\t\t\t0xe0 (PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_vsync.lcd_vsync */\n-\t\t\t0xe4 (PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_hsync.lcd_hsync */\n-\t\t\t0xe8 (PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_pclk.lcd_pclk */\n-\t\t\t0xec (PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_ac_bias_en.lcd_ac_bias_en */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1)\t\t/* gpmc_ad8.lcd_data23 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1)\t\t/* gpmc_ad9.lcd_data22 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1)\t\t/* gpmc_ad10.lcd_data21 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1)\t\t/* gpmc_ad11.lcd_data20 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1)\t\t/* gpmc_ad12.lcd_data19 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1)\t\t/* gpmc_ad13.lcd_data18 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1)\t\t/* gpmc_ad14.lcd_data17 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1)\t\t/* gpmc_ad15.lcd_data16 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)\n \t\t>;\n \t};\n \n \tam335x_evm_audio_pins: am335x_evm_audio_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\t0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */\n-\t\t\t0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */\n-\t\t\t0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */\n-\t\t\t0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */\n \t\t>;\n \t};\n \n \tdcan1_pins_default: dcan1_pins_default {\n \t\tpinctrl-single,pins = <\n-\t\t\t0x168 (PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */\n-\t\t\t0x16c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT, MUX_MODE2) /* uart0_ctsn.d_can1_tx */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2) /* uart0_rtsn.d_can1_rx */\n \t\t>;\n \t};\n };\ndiff --git a/arch/arm/dts/am335x-evmsk.dts b/arch/arm/dts/am335x-evmsk.dts\nindex d6b40252118..4890e18c4a9 100644\n--- a/arch/arm/dts/am335x-evmsk.dts\n+++ b/arch/arm/dts/am335x-evmsk.dts\n@@ -204,234 +204,234 @@\n \n \tlcd_pins_default: lcd_pins_default {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1)\t/* gpmc_ad8.lcd_data23 */\n-\t\t\tAM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1)\t/* gpmc_ad9.lcd_data22 */\n-\t\t\tAM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1)\t/* gpmc_ad10.lcd_data21 */\n-\t\t\tAM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1)\t/* gpmc_ad11.lcd_data20 */\n-\t\t\tAM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1)\t/* gpmc_ad12.lcd_data19 */\n-\t\t\tAM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1)\t/* gpmc_ad13.lcd_data18 */\n-\t\t\tAM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1)\t/* gpmc_ad14.lcd_data17 */\n-\t\t\tAM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1)\t/* gpmc_ad15.lcd_data16 */\n-\t\t\tAM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0)\t/* lcd_data0.lcd_data0 */\n-\t\t\tAM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0)\t/* lcd_data1.lcd_data1 */\n-\t\t\tAM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0)\t/* lcd_data2.lcd_data2 */\n-\t\t\tAM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0)\t/* lcd_data3.lcd_data3 */\n-\t\t\tAM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0)\t/* lcd_data4.lcd_data4 */\n-\t\t\tAM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0)\t/* lcd_data5.lcd_data5 */\n-\t\t\tAM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0)\t/* lcd_data6.lcd_data6 */\n-\t\t\tAM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0)\t/* lcd_data7.lcd_data7 */\n-\t\t\tAM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0)\t/* lcd_data8.lcd_data8 */\n-\t\t\tAM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0)\t/* lcd_data9.lcd_data9 */\n-\t\t\tAM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0)\t/* lcd_data10.lcd_data10 */\n-\t\t\tAM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0)\t/* lcd_data11.lcd_data11 */\n-\t\t\tAM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0)\t/* lcd_data12.lcd_data12 */\n-\t\t\tAM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0)\t/* lcd_data13.lcd_data13 */\n-\t\t\tAM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0)\t/* lcd_data14.lcd_data14 */\n-\t\t\tAM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0)\t/* lcd_data15.lcd_data15 */\n-\t\t\tAM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0)\t/* lcd_vsync.lcd_vsync */\n-\t\t\tAM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0)\t/* lcd_hsync.lcd_hsync */\n-\t\t\tAM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0)\t/* lcd_pclk.lcd_pclk */\n-\t\t\tAM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0)\t/* lcd_ac_bias_en.lcd_ac_bias_en */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE1)\t/* gpmc_ad8.lcd_data23 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE1)\t/* gpmc_ad9.lcd_data22 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE1)\t/* gpmc_ad10.lcd_data21 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE1)\t/* gpmc_ad11.lcd_data20 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE1)\t/* gpmc_ad12.lcd_data19 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE1)\t/* gpmc_ad13.lcd_data18 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE1)\t/* gpmc_ad14.lcd_data17 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE1)\t/* gpmc_ad15.lcd_data16 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)\n \t\t>;\n \t};\n \n \tlcd_pins_sleep: lcd_pins_sleep {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x820, PIN_INPUT_PULLDOWN | MUX_MODE7)\t/* gpmc_ad8.lcd_data23 */\n-\t\t\tAM33XX_IOPAD(0x824, PIN_INPUT_PULLDOWN | MUX_MODE7)\t/* gpmc_ad9.lcd_data22 */\n-\t\t\tAM33XX_IOPAD(0x828, PIN_INPUT_PULLDOWN | MUX_MODE7)\t/* gpmc_ad10.lcd_data21 */\n-\t\t\tAM33XX_IOPAD(0x82c, PIN_INPUT_PULLDOWN | MUX_MODE7)\t/* gpmc_ad11.lcd_data20 */\n-\t\t\tAM33XX_IOPAD(0x830, PIN_INPUT_PULLDOWN | MUX_MODE7)\t/* gpmc_ad12.lcd_data19 */\n-\t\t\tAM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7)\t/* gpmc_ad13.lcd_data18 */\n-\t\t\tAM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7)\t/* gpmc_ad14.lcd_data17 */\n-\t\t\tAM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7)\t/* gpmc_ad15.lcd_data16 */\n-\t\t\tAM33XX_IOPAD(0x8a0, PULL_DISABLE | MUX_MODE7)\t/* lcd_data0.lcd_data0 */\n-\t\t\tAM33XX_IOPAD(0x8a4, PULL_DISABLE | MUX_MODE7)\t/* lcd_data1.lcd_data1 */\n-\t\t\tAM33XX_IOPAD(0x8a8, PULL_DISABLE | MUX_MODE7)\t/* lcd_data2.lcd_data2 */\n-\t\t\tAM33XX_IOPAD(0x8ac, PULL_DISABLE | MUX_MODE7)\t/* lcd_data3.lcd_data3 */\n-\t\t\tAM33XX_IOPAD(0x8b0, PULL_DISABLE | MUX_MODE7)\t/* lcd_data4.lcd_data4 */\n-\t\t\tAM33XX_IOPAD(0x8b4, PULL_DISABLE | MUX_MODE7)\t/* lcd_data5.lcd_data5 */\n-\t\t\tAM33XX_IOPAD(0x8b8, PULL_DISABLE | MUX_MODE7)\t/* lcd_data6.lcd_data6 */\n-\t\t\tAM33XX_IOPAD(0x8bc, PULL_DISABLE | MUX_MODE7)\t/* lcd_data7.lcd_data7 */\n-\t\t\tAM33XX_IOPAD(0x8c0, PULL_DISABLE | MUX_MODE7)\t/* lcd_data8.lcd_data8 */\n-\t\t\tAM33XX_IOPAD(0x8c4, PULL_DISABLE | MUX_MODE7)\t/* lcd_data9.lcd_data9 */\n-\t\t\tAM33XX_IOPAD(0x8c8, PULL_DISABLE | MUX_MODE7)\t/* lcd_data10.lcd_data10 */\n-\t\t\tAM33XX_IOPAD(0x8cc, PULL_DISABLE | MUX_MODE7)\t/* lcd_data11.lcd_data11 */\n-\t\t\tAM33XX_IOPAD(0x8d0, PULL_DISABLE | MUX_MODE7)\t/* lcd_data12.lcd_data12 */\n-\t\t\tAM33XX_IOPAD(0x8d4, PULL_DISABLE | MUX_MODE7)\t/* lcd_data13.lcd_data13 */\n-\t\t\tAM33XX_IOPAD(0x8d8, PULL_DISABLE | MUX_MODE7)\t/* lcd_data14.lcd_data14 */\n-\t\t\tAM33XX_IOPAD(0x8dc, PULL_DISABLE | MUX_MODE7)\t/* lcd_data15.lcd_data15 */\n-\t\t\tAM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | MUX_MODE7)\t/* lcd_vsync.lcd_vsync */\n-\t\t\tAM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7)\t/* lcd_hsync.lcd_hsync */\n-\t\t\tAM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7)\t/* lcd_pclk.lcd_pclk */\n-\t\t\tAM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7)\t/* lcd_ac_bias_en.lcd_ac_bias_en */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_ad8.lcd_data23 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_ad9.lcd_data22 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_ad10.lcd_data21 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_ad11.lcd_data20 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_ad12.lcd_data19 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_ad13.lcd_data18 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_ad14.lcd_data17 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_ad15.lcd_data16 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PULL_DISABLE, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PULL_DISABLE, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PULL_DISABLE, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PULL_DISABLE, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PULL_DISABLE, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PULL_DISABLE, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PULL_DISABLE, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PULL_DISABLE, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PULL_DISABLE, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PULL_DISABLE, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PULL_DISABLE, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PULL_DISABLE, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PULL_DISABLE, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PULL_DISABLE, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PULL_DISABLE, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PULL_DISABLE, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)\n \t\t>;\n \t};\n \n \n \tuser_leds_s0: user_leds_s0 {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x810, PIN_OUTPUT_PULLDOWN | MUX_MODE7)\t/* gpmc_ad4.gpio1_4 */\n-\t\t\tAM33XX_IOPAD(0x814, PIN_OUTPUT_PULLDOWN | MUX_MODE7)\t/* gpmc_ad5.gpio1_5 */\n-\t\t\tAM33XX_IOPAD(0x818, PIN_OUTPUT_PULLDOWN | MUX_MODE7)\t/* gpmc_ad6.gpio1_6 */\n-\t\t\tAM33XX_IOPAD(0x81c, PIN_OUTPUT_PULLDOWN | MUX_MODE7)\t/* gpmc_ad7.gpio1_7 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_OUTPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_ad4.gpio1_4 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_OUTPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_ad5.gpio1_5 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_OUTPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_ad6.gpio1_6 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_OUTPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_ad7.gpio1_7 */\n \t\t>;\n \t};\n \n \tgpio_keys_s0: gpio_keys_s0 {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x894, PIN_INPUT_PULLDOWN | MUX_MODE7)\t/* gpmc_oen_ren.gpio2_3 */\n-\t\t\tAM33XX_IOPAD(0x890, PIN_INPUT_PULLDOWN | MUX_MODE7)\t/* gpmc_advn_ale.gpio2_2 */\n-\t\t\tAM33XX_IOPAD(0x870, PIN_INPUT_PULLDOWN | MUX_MODE7)\t/* gpmc_wait0.gpio0_30 */\n-\t\t\tAM33XX_IOPAD(0x89c, PIN_INPUT_PULLDOWN | MUX_MODE7)\t/* gpmc_ben0_cle.gpio2_5 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_oen_ren.gpio2_3 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_advn_ale.gpio2_2 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_wait0.gpio0_30 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_INPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_ben0_cle.gpio2_5 */\n \t\t>;\n \t};\n \n \ti2c0_pins: pinmux_i2c0_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)\t/* i2c0_sda.i2c0_sda */\n-\t\t\tAM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)\t/* i2c0_scl.i2c0_scl */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)\n \t\t>;\n \t};\n \n \tuart0_pins: pinmux_uart0_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)\t/* uart0_rxd.uart0_rxd */\n-\t\t\tAM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)\t/* uart0_txd.uart0_txd */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)\n \t\t>;\n \t};\n \n \tclkout2_pin: pinmux_clkout2_pin {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3)\t/* xdma_event_intr1.clkout2 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3)\t/* xdma_event_intr1.clkout2 */\n \t\t>;\n \t};\n \n \tecap2_pins: backlight_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x99c, MUX_MODE4)\t/* mcasp0_ahclkr.ecap2_in_pwm2_out */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, 0x0, MUX_MODE4)\t/* mcasp0_ahclkr.ecap2_in_pwm2_out */\n \t\t>;\n \t};\n \n \tcpsw_default: cpsw_default {\n \t\tpinctrl-single,pins = <\n \t\t\t/* Slave 1 */\n-\t\t\tAM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE2)\t/* mii1_txen.rgmii1_tctl */\n-\t\t\tAM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE2)\t/* mii1_rxdv.rgmii1_rctl */\n-\t\t\tAM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)\t/* mii1_txd3.rgmii1_td3 */\n-\t\t\tAM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE2)\t/* mii1_txd2.rgmii1_td2 */\n-\t\t\tAM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE2)\t/* mii1_txd1.rgmii1_td1 */\n-\t\t\tAM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE2)\t/* mii1_txd0.rgmii1_td0 */\n-\t\t\tAM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)\t/* mii1_txclk.rgmii1_tclk */\n-\t\t\tAM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE2)\t/* mii1_rxclk.rgmii1_rclk */\n-\t\t\tAM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE2)\t/* mii1_rxd3.rgmii1_rd3 */\n-\t\t\tAM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE2)\t/* mii1_rxd2.rgmii1_rd2 */\n-\t\t\tAM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE2)\t/* mii1_rxd1.rgmii1_rd1 */\n-\t\t\tAM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE2)\t/* mii1_rxd0.rgmii1_rd0 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* mii1_txen.rgmii1_tctl */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* mii1_rxdv.rgmii1_rctl */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* mii1_txd3.rgmii1_td3 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* mii1_txd2.rgmii1_td2 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* mii1_txd1.rgmii1_td1 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* mii1_txd0.rgmii1_td0 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* mii1_txclk.rgmii1_tclk */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* mii1_rxclk.rgmii1_rclk */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* mii1_rxd3.rgmii1_rd3 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* mii1_rxd2.rgmii1_rd2 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* mii1_rxd1.rgmii1_rd1 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* mii1_rxd0.rgmii1_rd0 */\n \n \t\t\t/* Slave 2 */\n-\t\t\tAM33XX_IOPAD(0x840, PIN_OUTPUT_PULLDOWN | MUX_MODE2)\t/* gpmc_a0.rgmii2_tctl */\n-\t\t\tAM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE2)\t/* gpmc_a1.rgmii2_rctl */\n-\t\t\tAM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE2)\t/* gpmc_a2.rgmii2_td3 */\n-\t\t\tAM33XX_IOPAD(0x84c, PIN_OUTPUT_PULLDOWN | MUX_MODE2)\t/* gpmc_a3.rgmii2_td2 */\n-\t\t\tAM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE2)\t/* gpmc_a4.rgmii2_td1 */\n-\t\t\tAM33XX_IOPAD(0x854, PIN_OUTPUT_PULLDOWN | MUX_MODE2)\t/* gpmc_a5.rgmii2_td0 */\n-\t\t\tAM33XX_IOPAD(0x858, PIN_OUTPUT_PULLDOWN | MUX_MODE2)\t/* gpmc_a6.rgmii2_tclk */\n-\t\t\tAM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE2)\t/* gpmc_a7.rgmii2_rclk */\n-\t\t\tAM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE2)\t/* gpmc_a8.rgmii2_rd3 */\n-\t\t\tAM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE2)\t/* gpmc_a9.rgmii2_rd2 */\n-\t\t\tAM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE2)\t/* gpmc_a10.rgmii2_rd1 */\n-\t\t\tAM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE2)\t/* gpmc_a11.rgmii2_rd0 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* gpmc_a0.rgmii2_tctl */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* gpmc_a1.rgmii2_rctl */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* gpmc_a2.rgmii2_td3 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* gpmc_a3.rgmii2_td2 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* gpmc_a4.rgmii2_td1 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* gpmc_a5.rgmii2_td0 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT_PULLDOWN, MUX_MODE2)\t/* gpmc_a6.rgmii2_tclk */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* gpmc_a7.rgmii2_rclk */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* gpmc_a8.rgmii2_rd3 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* gpmc_a9.rgmii2_rd2 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* gpmc_a10.rgmii2_rd1 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* gpmc_a11.rgmii2_rd0 */\n \t\t>;\n \t};\n \n \tcpsw_sleep: cpsw_sleep {\n \t\tpinctrl-single,pins = <\n \t\t\t/* Slave 1 reset value */\n-\t\t\tAM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)\n \n \t\t\t/* Slave 2 reset value*/\n-\t\t\tAM33XX_IOPAD(0x840, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x848, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x84c, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x850, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x854, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)\n \t\t>;\n \t};\n \n \tdavinci_mdio_default: davinci_mdio_default {\n \t\tpinctrl-single,pins = <\n \t\t\t/* MDIO */\n-\t\t\tAM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)\t/* mdio_data.mdio_data */\n-\t\t\tAM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)\t\t\t/* mdio_clk.mdio_clk */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)\n \t\t>;\n \t};\n \n \tdavinci_mdio_sleep: davinci_mdio_sleep {\n \t\tpinctrl-single,pins = <\n \t\t\t/* MDIO reset value */\n-\t\t\tAM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)\n \t\t>;\n \t};\n \n \tmmc1_pins: pinmux_mmc1_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7) \t\t/* spi0_cs1.gpio0_6 */\n \t\t>;\n \t};\n \n \tmcasp1_pins: mcasp1_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */\n-\t\t\tAM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */\n-\t\t\tAM33XX_IOPAD(0x908, PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */\n-\t\t\tAM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_crs.mcasp1_aclkx */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_OUTPUT_PULLDOWN, MUX_MODE4) /* mii1_col.mcasp1_axr2 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */\n \t\t>;\n \t};\n \n \tmcasp1_pins_sleep: mcasp1_pins_sleep {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x908, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)\n \t\t>;\n \t};\n \n \tmmc2_pins: pinmux_mmc2_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */\n-\t\t\tAM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */\n-\t\t\tAM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */\n-\t\t\tAM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */\n-\t\t\tAM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */\n-\t\t\tAM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */\n-\t\t\tAM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7) /* gpmc_wpn.gpio0_31 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn1.mmc1_clk */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2) /* gpmc_csn2.mmc1_cmd */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */\n \t\t>;\n \t};\n \n \twl12xx_gpio: pinmux_wl12xx_gpio {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x87c, PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_csn0.gpio1_29 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT_PULLUP, MUX_MODE7) /* gpmc_csn0.gpio1_29 */\n \t\t>;\n \t};\n };\ndiff --git a/arch/arm/dts/am335x-icev2.dts b/arch/arm/dts/am335x-icev2.dts\nindex 3a1d5a54c55..cd7c4ae0627 100644\n--- a/arch/arm/dts/am335x-icev2.dts\n+++ b/arch/arm/dts/am335x-icev2.dts\n@@ -146,31 +146,31 @@\n &am33xx_pinmux {\n \tuser_leds: user_leds {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */\n-\t\t\tAM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */\n-\t\t\tAM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */\n-\t\t\tAM33XX_IOPAD(0x9b4, PIN_OUTPUT | MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */\n-\t\t\tAM33XX_IOPAD(0x880, PIN_OUTPUT | MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */\n-\t\t\tAM33XX_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_OUTPUT, MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT, MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_OUTPUT, MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT, MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */\n \t\t>;\n \t};\n \n \tmmc0_pins_default: mmc0_pins_default {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* (F17) mmc0_dat3.mmc0_dat3 */\n-\t\t\tAM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* (F18) mmc0_dat2.mmc0_dat2 */\n-\t\t\tAM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* (G15) mmc0_dat1.mmc0_dat1 */\n-\t\t\tAM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */\n-\t\t\tAM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */\n-\t\t\tAM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)\n \t\t\tAM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE5) /* (C15) spi0_cs1.mmc0_sdcd */\n \t\t>;\n \t};\n \n \ti2c0_pins_default: i2c0_pins_default {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */\n-\t\t\tAM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)\n \t\t>;\n \t};\n \n@@ -185,71 +185,71 @@\n \n \tuart3_pins_default: uart3_pins_default {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */\n-\t\t\tAM33XX_IOPAD(0x938, PIN_OUTPUT_PULLUP | MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLUP, MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */\n \t\t>;\n \t};\n \n \tcpsw_default: cpsw_default {\n \t\tpinctrl-single,pins = <\n \t\t\t/* Slave 1, RMII mode */\n-\t\t\tAM33XX_IOPAD(0x90c, (PIN_INPUT_PULLUP | MUX_MODE1))\t/* mii1_crs.rmii1_crs_dv */\n-\t\t\tAM33XX_IOPAD(0x944, (PIN_INPUT_PULLUP | MUX_MODE0))\t/* rmii1_refclk.rmii1_refclk */\n-\t\t\tAM33XX_IOPAD(0x940, (PIN_INPUT_PULLUP | MUX_MODE1))\t/* mii1_rxd0.rmii1_rxd0 */\n-\t\t\tAM33XX_IOPAD(0x93c, (PIN_INPUT_PULLUP | MUX_MODE1))\t/* mii1_rxd1.rmii1_rxd1 */\n-\t\t\tAM33XX_IOPAD(0x910, (PIN_INPUT_PULLUP | MUX_MODE1))\t/* mii1_rxerr.rmii1_rxerr */\n-\t\t\tAM33XX_IOPAD(0x928, (PIN_OUTPUT_PULLDOWN | MUX_MODE1))\t/* mii1_txd0.rmii1_txd0 */\n-\t\t\tAM33XX_IOPAD(0x924, (PIN_OUTPUT_PULLDOWN | MUX_MODE1))\t/* mii1_txd1.rmii1_txd1 */\n-\t\t\tAM33XX_IOPAD(0x914, (PIN_OUTPUT_PULLDOWN | MUX_MODE1))\t/* mii1_txen.rmii1_txen */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLUP, MUX_MODE1)\t/* mii1_crs.rmii1_crs_dv */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE1)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE1)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE1)\t/* mii1_rxerr.rmii1_rxerr */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE1)\t/* mii1_txd0.rmii1_txd0 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE1)\t/* mii1_txd1.rmii1_txd1 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE1)\t/* mii1_txen.rmii1_txen */\n \t\t\t/* Slave 2, RMII mode */\n-\t\t\tAM33XX_IOPAD(0x870, (PIN_INPUT_PULLUP | MUX_MODE3))\t/* gpmc_wait0.rmii2_crs_dv */\n-\t\t\tAM33XX_IOPAD(0x908, (PIN_INPUT_PULLUP | MUX_MODE1))\t/* mii1_col.rmii2_refclk */\n-\t\t\tAM33XX_IOPAD(0x86c, (PIN_INPUT_PULLUP | MUX_MODE3))\t/* gpmc_a11.rmii2_rxd0 */\n-\t\t\tAM33XX_IOPAD(0x868, (PIN_INPUT_PULLUP | MUX_MODE3))\t/* gpmc_a10.rmii2_rxd1 */\n-\t\t\tAM33XX_IOPAD(0x874, (PIN_INPUT_PULLUP | MUX_MODE3))\t/* gpmc_wpn.rmii2_rxerr */\n-\t\t\tAM33XX_IOPAD(0x854, (PIN_OUTPUT_PULLDOWN | MUX_MODE3))\t/* gpmc_a5.rmii2_txd0 */\n-\t\t\tAM33XX_IOPAD(0x850, (PIN_OUTPUT_PULLDOWN | MUX_MODE3))\t/* gpmc_a4.rmii2_txd1 */\n-\t\t\tAM33XX_IOPAD(0x840, (PIN_OUTPUT_PULLDOWN | MUX_MODE3))\t/* gpmc_a0.rmii2_txen */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE3)\t/* gpmc_wait0.rmii2_crs_dv */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE1)\t/* mii1_col.rmii2_refclk */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLUP, MUX_MODE3)\t/* gpmc_a11.rmii2_rxd0 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLUP, MUX_MODE3)\t/* gpmc_a10.rmii2_rxd1 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE3)\t/* gpmc_wpn.rmii2_rxerr */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT_PULLDOWN, MUX_MODE3)\t/* gpmc_a5.rmii2_txd0 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE3)\t/* gpmc_a4.rmii2_txd1 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT_PULLDOWN, MUX_MODE3)\t/* gpmc_a0.rmii2_txen */\n \t\t>;\n \t};\n \n \tcpsw_sleep: cpsw_sleep {\n \t\tpinctrl-single,pins = <\n \t\t\t/* Slave 1 reset value */\n-\t\t\tAM33XX_IOPAD(0x90c, (PIN_INPUT_PULLDOWN | MUX_MODE7))\n-\t\t\tAM33XX_IOPAD(0x944, (PIN_INPUT_PULLDOWN | MUX_MODE7))\n-\t\t\tAM33XX_IOPAD(0x940, (PIN_INPUT_PULLDOWN | MUX_MODE7))\n-\t\t\tAM33XX_IOPAD(0x93c, (PIN_INPUT_PULLDOWN | MUX_MODE7))\n-\t\t\tAM33XX_IOPAD(0x910, (PIN_INPUT_PULLDOWN | MUX_MODE7))\n-\t\t\tAM33XX_IOPAD(0x928, (PIN_INPUT_PULLDOWN | MUX_MODE7))\n-\t\t\tAM33XX_IOPAD(0x924, (PIN_INPUT_PULLDOWN | MUX_MODE7))\n-\t\t\tAM33XX_IOPAD(0x914, (PIN_INPUT_PULLDOWN | MUX_MODE7))\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)\n \n \t\t\t/* Slave 2 reset value */\n-\t\t\tAM33XX_IOPAD(0x870, (PIN_INPUT_PULLDOWN | MUX_MODE7))\n-\t\t\tAM33XX_IOPAD(0x908, (PIN_INPUT_PULLDOWN | MUX_MODE7))\n-\t\t\tAM33XX_IOPAD(0x86c, (PIN_INPUT_PULLDOWN | MUX_MODE7))\n-\t\t\tAM33XX_IOPAD(0x868, (PIN_INPUT_PULLDOWN | MUX_MODE7))\n-\t\t\tAM33XX_IOPAD(0x874, (PIN_INPUT_PULLDOWN | MUX_MODE7))\n-\t\t\tAM33XX_IOPAD(0x854, (PIN_INPUT_PULLDOWN | MUX_MODE7))\n-\t\t\tAM33XX_IOPAD(0x850, (PIN_INPUT_PULLDOWN | MUX_MODE7))\n-\t\t\tAM33XX_IOPAD(0x840, (PIN_INPUT_PULLDOWN | MUX_MODE7))\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLDOWN, MUX_MODE7)\n \t\t>;\n \t};\n \n \tdavinci_mdio_default: davinci_mdio_default {\n \t\tpinctrl-single,pins = <\n \t\t\t/* MDIO */\n-\t\t\tAM33XX_IOPAD(0x948, (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0))\t/* mdio_data.mdio_data */\n-\t\t\tAM33XX_IOPAD(0x94c, (PIN_OUTPUT_PULLUP | MUX_MODE0))\t\t\t/* mdio_clk.mdio_clk */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)\n \t\t>;\n \t};\n \n \tdavinci_mdio_sleep: davinci_mdio_sleep {\n \t\tpinctrl-single,pins = <\n \t\t\t/* MDIO reset value */\n-\t\t\tAM33XX_IOPAD(0x948, (PIN_INPUT_PULLDOWN | MUX_MODE7))\n-\t\t\tAM33XX_IOPAD(0x94c, (PIN_INPUT_PULLDOWN | MUX_MODE7))\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)\n \t\t>;\n \t};\n };\ndiff --git a/arch/arm/dts/am335x-igep0033.dtsi b/arch/arm/dts/am335x-igep0033.dtsi\nindex bf6ec5d1b5e..911b894a683 100644\n--- a/arch/arm/dts/am335x-igep0033.dtsi\n+++ b/arch/arm/dts/am335x-igep0033.dtsi\n@@ -54,41 +54,41 @@\n &am33xx_pinmux {\n \ti2c0_pins: pinmux_i2c0_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)\t/* i2c0_sda.i2c0_sda */\n-\t\t\tAM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)\t/* i2c0_scl.i2c0_scl */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)\n \t\t>;\n \t};\n \n \tnandflash_pins: pinmux_nandflash_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0)\t/* gpmc_ad0.gpmc_ad0 */\n-\t\t\tAM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0)\t/* gpmc_ad1.gpmc_ad1 */\n-\t\t\tAM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0)\t/* gpmc_ad2.gpmc_ad2 */\n-\t\t\tAM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0)\t/* gpmc_ad3.gpmc_ad3 */\n-\t\t\tAM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0)\t/* gpmc_ad4.gpmc_ad4 */\n-\t\t\tAM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0)\t/* gpmc_ad5.gpmc_ad5 */\n-\t\t\tAM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0)\t/* gpmc_ad6.gpmc_ad6 */\n-\t\t\tAM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0)\t/* gpmc_ad7.gpmc_ad7 */\n-\t\t\tAM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)\t/* gpmc_wait0.gpmc_wait0 */\n-\t\t\tAM33XX_IOPAD(0x874, PIN_INPUT_PULLUP | MUX_MODE7)\t/* gpmc_wpn.gpio0_30 */\n-\t\t\tAM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)\t\t/* gpmc_csn0.gpmc_csn0 */\n-\t\t\tAM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)\t\t/* gpmc_advn_ale.gpmc_advn_ale */\n-\t\t\tAM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)\t\t/* gpmc_oen_ren.gpmc_oen_ren */\n-\t\t\tAM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)\t\t/* gpmc_wen.gpmc_wen */\n-\t\t\tAM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)\t\t/* gpmc_be0n_cle.gpmc_be0n_cle */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7)\t/* gpmc_wpn.gpio0_31 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)\n \t\t>;\n \t};\n \n \tuart0_pins: pinmux_uart0_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)\t/* uart0_rxd.uart0_rxd */\n-\t\t\tAM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)\t/* uart0_txd.uart0_txd */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)\n \t\t>;\n \t};\n \n \tleds_pins: pinmux_leds_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLDOWN | MUX_MODE7)\t/* gpmc_a7.gpio1_23 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLDOWN, MUX_MODE7)\t/* gpmc_a7.gpio1_23 */\n \t\t>;\n \t};\n };\ndiff --git a/arch/arm/dts/am335x-osd335x-common.dtsi b/arch/arm/dts/am335x-osd335x-common.dtsi\nindex c3924e1636e..7cf4e9fb39d 100644\n--- a/arch/arm/dts/am335x-osd335x-common.dtsi\n+++ b/arch/arm/dts/am335x-osd335x-common.dtsi\n@@ -36,8 +36,8 @@\n &am33xx_pinmux {\n \ti2c0_pins: pinmux-i2c0-pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)\t/* (C17) I2C0_SDA.I2C0_SDA */\n-\t\t\tAM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)\t/* (C16) I2C0_SCL.I2C0_SCL */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)\n \t\t>;\n \t};\n };\ndiff --git a/arch/arm/dts/am335x-pdu001.dts b/arch/arm/dts/am335x-pdu001.dts\nindex 3567de6a492..fb1f799a9ee 100644\n--- a/arch/arm/dts/am335x-pdu001.dts\n+++ b/arch/arm/dts/am335x-pdu001.dts\n@@ -92,162 +92,162 @@\n \n \ti2c0_pins: pinmux_i2c0_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)\t/* i2c0_sda.i2c0_sda */\n-\t\t\tAM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)\t/* i2c0_scl.i2c0_scl */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)\n \t\t>;\n \t};\n \n \ti2c1_pins: pinmux_i2c1_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE2)\t/* spi0_d1.i2c1_sda */\n-\t\t\tAM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE2)\t/* spi0_cs0.i2c1_scl */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE2)\t/* spi0_d1.i2c1_sda */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE2)\t/* spi0_cs0.i2c1_scl */\n \t\t>;\n \t};\n \n \ti2c2_pins: pinmux_i2c2_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE2)\t/* spi0_clk.i2c2_sda */\n-\t\t\tAM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE2)\t/* spi0_d0.i2c2_scl */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE2)\t/* spi0_clk.i2c2_sda */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE2)\t/* spi0_d0.i2c2_scl */\n \t\t>;\n \t};\n \n \tspi1_pins: pinmux_spi1_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE3)\t\t/* mcasp0_aclkx.spi1_sclk */\n-\t\t\tAM33XX_IOPAD(0x994, PIN_OUTPUT | MUX_MODE3)\t\t/* mcasp0_fsx.spi1_d0 */\n-\t\t\tAM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE3)\t/* mcasp0_axr0.spi1_d1 */\n-\t\t\tAM33XX_IOPAD(0x99C, PIN_OUTPUT | MUX_MODE3)\t\t/* mcasp0_ahclkr.spi1_cs0 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT, MUX_MODE3)\t\t/* mcasp0_aclkx.spi1_sclk */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT, MUX_MODE3)\t\t/* mcasp0_fsx.spi1_d0 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE3)\t/* mcasp0_axr0.spi1_d1 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKR, PIN_OUTPUT, MUX_MODE3)\t\t/* mcasp0_ahclkr.spi1_cs0 */\n \t\t>;\n \t};\n \n \tuart0_pins: pinmux_uart0_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x96C, PIN_OUTPUT | MUX_MODE7)\t\t/* uart0_rtsn.gpio1_9 */\n-\t\t\tAM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)\t/* uart0_rxd.uart0_rxd */\n-\t\t\tAM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)\t/* uart0_txd.uart0_txd */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)\n \t\t>;\n \t};\n \n \tuart1_pins: pinmux_uart1_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0)\t/* uart1_rxd.uart1_rxd */\n-\t\t\tAM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0)\t/* uart1_txd.uart1_txd */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)\n \t\t>;\n \t};\n \n \tuart3_pins: pinmux_uart3_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE1)\t/* spi0_cs1.uart3_rxd */\n-\t\t\tAM33XX_IOPAD(0x964, PIN_OUTPUT_PULLDOWN | MUX_MODE1)\t/* ecap0_in_pwm0_out.uart3_txd */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE1)\t/* spi0_cs1.uart3_rxd */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLDOWN, MUX_MODE1)\t/* ecap0_in_pwm0_out.uart3_txd */\n \t\t>;\n \t};\n \n \tclkout2_pin: pinmux_clkout2_pin {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3)\t/* xdma_event_intr1.clkout2 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3)\t/* xdma_event_intr1.clkout2 */\n \t\t>;\n \t};\n \n \tcpsw_default: cpsw_default {\n \t\tpinctrl-single,pins = <\n \t\t\t/* Port 1 (emac0) */\n-\t\t\tAM33XX_IOPAD(0x908, PIN_INPUT | MUX_MODE0)\t\t/* mii1_col.mii1_col */\n-\t\t\tAM33XX_IOPAD(0x90C, PIN_INPUT | MUX_MODE0)\t\t/* mii1_crs.mii1_crs */\n-\t\t\tAM33XX_IOPAD(0x910, PIN_INPUT | MUX_MODE0)\t\t/* mii1_rxer.mii1_rxer */\n-\t\t\tAM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE0)\t\t/* mii1_txen.mii1_txen */\n-\t\t\tAM33XX_IOPAD(0x918, PIN_INPUT | MUX_MODE0)\t\t/* mii1_rxdv.mii1_rxdv */\n-\t\t\tAM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE0)\t\t/* mii1_txd3.mii1_txd3 */\n-\t\t\tAM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE0)\t\t/* mii1_txd2.mii1_txd2 */\n-\t\t\tAM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE0)\t\t/* mii1_txd1.mii1_txd1 */\n-\t\t\tAM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE0)\t\t/* mii1_txd0.mii1_txd0 */\n-\t\t\tAM33XX_IOPAD(0x92c, PIN_INPUT | MUX_MODE0)\t\t/* mii1_txclk.mii1_txclk */\n-\t\t\tAM33XX_IOPAD(0x930, PIN_INPUT | MUX_MODE0)\t\t/* mii1_rxclk.mii1_rxclk */\n-\t\t\tAM33XX_IOPAD(0x934, PIN_INPUT | MUX_MODE0)\t\t/* mii1_rxd3.mii1_rxd3 */\n-\t\t\tAM33XX_IOPAD(0x938, PIN_INPUT | MUX_MODE0)\t\t/* mii1_rxd2.mii1_rxd2 */\n-\t\t\tAM33XX_IOPAD(0x93c, PIN_INPUT | MUX_MODE0)\t\t/* mii1_rxd1.mii1_rxd1 */\n-\t\t\tAM33XX_IOPAD(0x940, PIN_INPUT | MUX_MODE0)\t\t/* mii1_rxd0.mii1_rxd0 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT, MUX_MODE0)\n \n \t\t\t/* Port 2 (emac1) */\n-\t\t\tAM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1)\t\t/* mii2_txen.gpmc_a0 */\n-\t\t\tAM33XX_IOPAD(0x844, PIN_INPUT | MUX_MODE1)\t\t/* mii2_rxdv.gpmc_a1 */\n-\t\t\tAM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1)\t\t/* mii2_txd3.gpmc_a2 */\n-\t\t\tAM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE1)\t\t/* mii2_txd2.gpmc_a3 */\n-\t\t\tAM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1)\t\t/* mii2_txd1.gpmc_a4 */\n-\t\t\tAM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1)\t\t/* mii2_txd0.gpmc_a5 */\n-\t\t\tAM33XX_IOPAD(0x858, PIN_INPUT | MUX_MODE1)\t\t/* mii2_txclk.gpmc_a6 */\n-\t\t\tAM33XX_IOPAD(0x85c, PIN_INPUT | MUX_MODE1)\t\t/* mii2_rxclk.gpmc_a7 */\n-\t\t\tAM33XX_IOPAD(0x860, PIN_INPUT | MUX_MODE1)\t\t/* mii2_rxd3.gpmc_a8 */\n-\t\t\tAM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE1)\t\t/* mii2_rxd2.gpmc_a9 */\n-\t\t\tAM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE1)\t\t/* mii2_rxd1.gpmc_a10 */\n-\t\t\tAM33XX_IOPAD(0x86C, PIN_INPUT | MUX_MODE1)\t\t/* mii2_rxd0.gpmc_a11 */\n-\t\t\tAM33XX_IOPAD(0x870, PIN_INPUT | MUX_MODE1)\t\t/* mii2_crs.gpmc_wait0 */\n-\t\t\tAM33XX_IOPAD(0x874, PIN_INPUT | MUX_MODE1)\t\t/* mii2_rxer.gpmc_wpn */\n-\t\t\tAM33XX_IOPAD(0x878, PIN_INPUT | MUX_MODE1)\t\t/* mii2_col.gpmc_ben1 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1)\t\t/* mii2_txen.gpmc_a0 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT, MUX_MODE1)\t\t/* mii2_rxdv.gpmc_a1 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1)\t\t/* mii2_txd3.gpmc_a2 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1)\t\t/* mii2_txd2.gpmc_a3 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1)\t\t/* mii2_txd1.gpmc_a4 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1)\t\t/* mii2_txd0.gpmc_a5 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT, MUX_MODE1)\t\t/* mii2_txclk.gpmc_a6 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT, MUX_MODE1)\t\t/* mii2_rxclk.gpmc_a7 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT, MUX_MODE1)\t\t/* mii2_rxd3.gpmc_a8 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE1)\t\t/* mii2_rxd2.gpmc_a9 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE1)\t\t/* mii2_rxd1.gpmc_a10 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT, MUX_MODE1)\t\t/* mii2_rxd0.gpmc_a11 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT, MUX_MODE1)\t\t/* mii2_crs.gpmc_wait0 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT, MUX_MODE1)\t\t/* mii2_rxer.gpmc_wpn */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT, MUX_MODE1)\t\t/* mii2_col.gpmc_ben1 */\n \t\t>;\n \t};\n \n \tdavinci_mdio_default: davinci_mdio_default {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)\t/* mdio_data.mdio_data */\n-\t\t\tAM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)\t\t\t/* mdio_clk.mdio_clk */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)\n \t\t>;\n \t};\n \n \tmmc1_pins: pinmux_mmc1_pins {\n \t\t/* eMMC */\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc0_dat3 */\n-\t\t\tAM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc0_dat2 */\n-\t\t\tAM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc0_dat1 */\n-\t\t\tAM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc0_dat0 */\n-\t\t\tAM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc0_clk */\n-\t\t\tAM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc0_cmd */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)\n \t\t>;\n \t};\n \n \tmmc2_pins: pinmux_mmc2_pins {\n \t\t/* SD cardcage */\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1)\t/* gpmc_ad3.mmc1_dat3 */\n-\t\t\tAM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1)\t/* gpmc_ad2.mmc1_dat2 */\n-\t\t\tAM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1)\t/* gpmc_ad1.mmc1_dat1 */\n-\t\t\tAM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1)\t/* gpmc_ad0.mmc1_dat0 */\n-\t\t\tAM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2)\t/* gpmc_csn1.mmc1_clk */\n-\t\t\tAM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2)\t/* gpmc_csn2.mmc1_cmd */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1)\t/* gpmc_ad3.mmc1_dat3 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1)\t/* gpmc_ad2.mmc1_dat2 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1)\t/* gpmc_ad1.mmc1_dat1 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1)\t/* gpmc_ad0.mmc1_dat0 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2)\t/* gpmc_csn1.mmc1_clk */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2)\t/* gpmc_csn2.mmc1_cmd */\n \t\t\t/* card change signal for frontpanel SD cardcage */\n-\t\t\tAM33XX_IOPAD(0x890, PIN_INPUT | MUX_MODE7)\t\t/* gpmc_advn_ale.gpio2_2 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_INPUT, MUX_MODE7)\t\t/* gpmc_advn_ale.gpio2_2 */\n \t\t>;\n \t};\n \n \tlcd_pins_s0: lcd_pins_s0 {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_data0.lcd_data0 */\n-\t\t\tAM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_data1.lcd_data1 */\n-\t\t\tAM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_data2.lcd_data2 */\n-\t\t\tAM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_data3.lcd_data3 */\n-\t\t\tAM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_data4.lcd_data4 */\n-\t\t\tAM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_data5.lcd_data5 */\n-\t\t\tAM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_data6.lcd_data6 */\n-\t\t\tAM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_data7.lcd_data7 */\n-\t\t\tAM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_data8.lcd_data8 */\n-\t\t\tAM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_data9.lcd_data9 */\n-\t\t\tAM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_data10.lcd_data10 */\n-\t\t\tAM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_data11.lcd_data11 */\n-\t\t\tAM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_data12.lcd_data12 */\n-\t\t\tAM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_data13.lcd_data13 */\n-\t\t\tAM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_data14.lcd_data14 */\n-\t\t\tAM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_data15.lcd_data15 */\n-\t\t\tAM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_vsync.lcd_vsync */\n-\t\t\tAM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_hsync.lcd_hsync */\n-\t\t\tAM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_pclk.lcd_pclk */\n-\t\t\tAM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0)\t\t/* lcd_ac_bias_en.lcd_ac_bias_en */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE0)\n \t\t>;\n \t};\n \n \tdcan0_pins: pinmux_dcan0_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x978, PIN_OUTPUT | MUX_MODE2)\t\t/* uart1_ctsn.d_can0_tx */\n-\t\t\tAM33XX_IOPAD(0x97c, PIN_INPUT_PULLDOWN | MUX_MODE2)\t/* uart1_rtsn.d_can0_rx */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_OUTPUT, MUX_MODE2)\t\t/* uart1_ctsn.d_can0_tx */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLDOWN, MUX_MODE2)\t/* uart1_rtsn.d_can0_rx */\n \t\t>;\n \t};\n };\ndiff --git a/arch/arm/dts/am335x-phycore-som.dtsi b/arch/arm/dts/am335x-phycore-som.dtsi\nindex 3b4b97a941e..ee6b1cb27ce 100644\n--- a/arch/arm/dts/am335x-phycore-som.dtsi\n+++ b/arch/arm/dts/am335x-phycore-som.dtsi\n@@ -54,22 +54,22 @@\n &am33xx_pinmux {\n \tethernet0_pins: pinmux_ethernet0 {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1)\t/* mii1_crs.rmii1_crs_dv */\n-\t\t\tAM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1)\t/* mii1_rxerr.rmii1_rxerr */\n-\t\t\tAM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE1)\t\t/* mii1_txen.rmii1_txen */\n-\t\t\tAM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE1)\t\t/* mii1_txd1.rmii1_txd1 */\n-\t\t\tAM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE1)\t\t/* mii1_txd0.rmii1_txd0 */\n-\t\t\tAM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1)\t/* mii1_rxd1.rmii1_rxd1 */\n-\t\t\tAM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1)\t/* mii1_rxd0.rmii1_rxd0 */\n-\t\t\tAM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0)\t/* rmii1_refclk.rmii1_refclk */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE1)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT, MUX_MODE1)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT, MUX_MODE1)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT, MUX_MODE1)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)\n \t\t>;\n \t};\n \n \tmdio_pins: pinmux_mdio {\n \t\tpinctrl-single,pins = <\n \t\t\t/* MDIO */\n-\t\t\tAM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)\t/* mdio_data.mdio_data */\n-\t\t\tAM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)\t\t\t/* mdio_clk.mdio_clk */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)\n \t\t>;\n \t};\n };\n@@ -101,8 +101,8 @@\n &am33xx_pinmux {\n \ti2c0_pins: pinmux_i2c0 {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0)\t/* i2c0_sda.i2c0_sda */\n-\t\t\tAM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0)\t/* i2c0_scl.i2c0_scl */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)\n \t\t>;\n \t};\n };\n@@ -141,20 +141,20 @@\n &am33xx_pinmux {\n \t\tnandflash_pins: pinmux_nandflash {\n \t\t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0)\t/* gpmc_ad0.gpmc_ad0 */\n-\t\t\tAM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0)\t/* gpmc_ad1.gpmc_ad1 */\n-\t\t\tAM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0)\t/* gpmc_ad2.gpmc_ad2 */\n-\t\t\tAM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0)\t/* gpmc_ad3.gpmc_ad3 */\n-\t\t\tAM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0)\t/* gpmc_ad4.gpmc_ad4 */\n-\t\t\tAM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0)\t/* gpmc_ad5.gpmc_ad5 */\n-\t\t\tAM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0)\t/* gpmc_ad6.gpmc_ad6 */\n-\t\t\tAM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0)\t/* gpmc_ad7.gpmc_ad7 */\n-\t\t\tAM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)\t/* gpmc_wait0.gpmc_wait0 */\n-\t\t\tAM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)\t\t/* gpmc_csn0.gpmc_csn0 */\n-\t\t\tAM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)\t\t/* gpmc_advn_ale.gpmc_advn_ale */\n-\t\t\tAM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)\t\t/* gpmc_oen_ren.gpmc_oen_ren */\n-\t\t\tAM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)\t\t/* gpmc_wen.gpmc_wen */\n-\t\t\tAM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)\t\t/* gpmc_be0n_cle.gpmc_be0n_cle */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)\n \t\t>;\n \t};\n };\n@@ -293,10 +293,10 @@\n &am33xx_pinmux {\n \tspi0_pins: pinmux_spi0 {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE0)\t/* spi0_clk.spi0_clk */\n-\t\t\tAM33XX_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0)\t/* spi0_d0.spi0_d0 */\n-\t\t\tAM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0)\t/* spi0_d1.spi0_d1 */\n-\t\t\tAM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0)\t/* spi0_cs0.spi0_cs0 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)\n \t\t>;\n \t};\n };\ndiff --git a/arch/arm/dts/am335x-pocketbeagle.dts b/arch/arm/dts/am335x-pocketbeagle.dts\nindex 14c68e9e00d..5cfd5731750 100644\n--- a/arch/arm/dts/am335x-pocketbeagle.dts\n+++ b/arch/arm/dts/am335x-pocketbeagle.dts\n@@ -62,74 +62,74 @@\n &am33xx_pinmux {\n \ti2c2_pins: pinmux-i2c2-pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3)\t/* (D17) uart1_rtsn.I2C2_SCL */\n-\t\t\tAM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3)\t/* (D18) uart1_ctsn.I2C2_SDA */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3)\t/* (D17) uart1_rtsn.I2C2_SCL */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3)\t/* (D18) uart1_ctsn.I2C2_SDA */\n \t\t>;\n \t};\n \n \tehrpwm0_pins: pinmux-ehrpwm0-pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x990, PIN_OUTPUT_PULLDOWN | MUX_MODE1)\t/* (A13) mcasp0_aclkx.ehrpwm0A */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE1)\t/* (A13) mcasp0_aclkx.ehrpwm0A */\n \t\t>;\n \t};\n \n \tehrpwm1_pins: pinmux-ehrpwm1-pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x848, PIN_OUTPUT_PULLDOWN | MUX_MODE6)\t/* (U14) gpmc_a2.ehrpwm1A */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT_PULLDOWN, MUX_MODE6)\t/* (U14) gpmc_a2.ehrpwm1A */\n \t\t>;\n \t};\n \n \tmmc0_pins: pinmux-mmc0-pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7)\t\t/* (C15) spi0_cs1.gpio0[6] */\n-\t\t\tAM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)\t/* (G16) mmc0_dat0.mmc0_dat0 */\n-\t\t\tAM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)\t/* (G15) mmc0_dat1.mmc0_dat1 */\n-\t\t\tAM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)\t/* (F18) mmc0_dat2.mmc0_dat2 */\n-\t\t\tAM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)\t/* (F17) mmc0_dat3.mmc0_dat3 */\n-\t\t\tAM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)\t/* (G18) mmc0_cmd.mmc0_cmd */\n-\t\t\tAM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)\t/* (G17) mmc0_clk.mmc0_clk */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE7)\t\t/* (C15) spi0_cs1.gpio0[6] */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)\n \t\t\tAM33XX_IOPAD(0x9a0, PIN_INPUT | MUX_MODE4)\t\t/* (B12) mcasp0_aclkr.mmc0_sdwp */\n \t\t>;\n \t};\n \n \tspi0_pins: pinmux-spi0-pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0)\t/* (A17) spi0_sclk.spi0_sclk */\n-\t\t\tAM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0)\t/* (B17) spi0_d0.spi0_d0 */\n-\t\t\tAM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0)\t/* (B16) spi0_d1.spi0_d1 */\n-\t\t\tAM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0)\t/* (A16) spi0_cs0.spi0_cs0 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)\n \t\t>;\n \t};\n \n \tspi1_pins: pinmux-spi1-pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x964, PIN_INPUT_PULLUP | MUX_MODE4)\t/* (C18) eCAP0_in_PWM0_out.spi1_sclk */\n-\t\t\tAM33XX_IOPAD(0x968, PIN_INPUT_PULLUP | MUX_MODE4)\t/* (E18) uart0_ctsn.spi1_d0 */\n-\t\t\tAM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE4)\t/* (E17) uart0_rtsn.spi1_d1 */\n-\t\t\tAM33XX_IOPAD(0x9b0, PIN_INPUT_PULLUP | MUX_MODE4)\t/* (A15) xdma_event_intr0.spi1_cs1 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_INPUT_PULLUP, MUX_MODE4)\t/* (C18) eCAP0_in_PWM0_out.spi1_sclk */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLUP, MUX_MODE4)\t/* (E18) uart0_ctsn.spi1_d0 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE4)\t/* (E17) uart0_rtsn.spi1_d1 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR0, PIN_INPUT_PULLUP, MUX_MODE4)\t/* (A15) xdma_event_intr0.spi1_cs1 */\n \t\t>;\n \t};\n \n \tusr_leds_pins: pinmux-usr-leds-pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7)\t\t/* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */\n-\t\t\tAM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7)\t\t/* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */\n-\t\t\tAM33XX_IOPAD(0x85c, PIN_OUTPUT | MUX_MODE7)\t\t/* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */\n-\t\t\tAM33XX_IOPAD(0x860, PIN_OUTPUT | MUX_MODE7)\t\t/* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7)\t\t/* (V15) gpmc_a5.gpio1[21] - USR_LED_0 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7)\t\t/* (U15) gpmc_a6.gpio1[22] - USR_LED_1 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7)\t\t/* (T15) gpmc_a7.gpio1[23] - USR_LED_2 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7)\t\t/* (V16) gpmc_a8.gpio1[24] - USR_LED_3 */\n \t\t>;\n \t};\n \n \tuart0_pins: pinmux-uart0-pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)\t/* (E15) uart0_rxd.uart0_rxd */\n-\t\t\tAM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)\t/* (E16) uart0_txd.uart0_txd */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)\n \t\t>;\n \t};\n \n \tuart4_pins: pinmux-uart4-pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6)\t/* (T17) gpmc_wait0.uart4_rxd */\n-\t\t\tAM33XX_IOPAD(0x874, PIN_OUTPUT_PULLDOWN | MUX_MODE6)\t/* (U17) gpmc_wpn.uart4_txd */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6)\t/* (T17) gpmc_wait0.uart4_rxd */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6)\t/* (U17) gpmc_wpn.uart4_txd */\n \t\t>;\n \t};\n };\ndiff --git a/arch/arm/dts/am335x-regor.dtsi b/arch/arm/dts/am335x-regor.dtsi\nindex 86b3f074297..6fbf4ac739e 100644\n--- a/arch/arm/dts/am335x-regor.dtsi\n+++ b/arch/arm/dts/am335x-regor.dtsi\n@@ -41,8 +41,8 @@\n &am33xx_pinmux {\n \tuser_leds_pins: pinmux_user_leds {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x8E0, PIN_OUTPUT_PULLDOWN | MUX_MODE7)\t/* lcd_hsync.gpio2_22 */\n-\t\t\tAM33XX_IOPAD(0x994, PIN_OUTPUT_PULLDOWN | MUX_MODE7)\t/* mcasp0_fsx.gpio3_15 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT_PULLDOWN, MUX_MODE7)\t/* lcd_hsync.gpio2_22 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_OUTPUT_PULLDOWN, MUX_MODE7)\t/* mcasp0_fsx.gpio3_15 */\n \t\t>;\n \t};\n };\n@@ -51,8 +51,8 @@\n &am33xx_pinmux {\n \tdcan1_pins: pinmux_dcan1 {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x968, PIN_OUTPUT_PULLUP | MUX_MODE2)\t/* uart0_ctsn.d_can1_tx */\n-\t\t\tAM33XX_IOPAD(0x96C, PIN_INPUT_PULLUP | MUX_MODE2)\t/* uart0_rtsn.d_can1_rx */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2)\t/* uart0_ctsn.d_can1_tx */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2)\t/* uart0_rtsn.d_can1_rx */\n \t\t>;\n \t};\n };\n@@ -67,20 +67,20 @@\n &am33xx_pinmux {\n \tethernet1_pins: pinmux_ethernet1 {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1)\t\t/* gpmc_a0.mii2_txen */\n-\t\t\tAM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE1)\t/* gpmc_a1.mii2_rxdv */\n-\t\t\tAM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1)\t\t/* gpmc_a2.mii2_txd3 */\n-\t\t\tAM33XX_IOPAD(0x84C, PIN_OUTPUT | MUX_MODE1)\t\t/* gpmc_a3.mii2_txd2 */\n-\t\t\tAM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1)\t\t/* gpmc_a4.mii2_txd1 */\n-\t\t\tAM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1)\t\t/* gpmc_a5.mii2_txd0 */\n-\t\t\tAM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE1)\t/* gpmc_a6.mii2_txclk */\n-\t\t\tAM33XX_IOPAD(0x85C, PIN_INPUT_PULLDOWN | MUX_MODE1)\t/* gpmc_a7.mii2_rxclk */\n-\t\t\tAM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE1)\t/* gpmc_a8.mii2_rxd3 */\n-\t\t\tAM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE1)\t /* gpmc_a9.mii2_rxd2 */\n-\t\t\tAM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE1)\t/* gpmc_a10.mii2_rxd1 */\n-\t\t\tAM33XX_IOPAD(0x86C, PIN_INPUT_PULLDOWN | MUX_MODE1)\t/* gpmc_a11.mii2_rxd0 */\n-\t\t\tAM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE1)\t/* gpmc_wpn.mii2_rxerr */\n-\t\t\tAM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE1)\t/* gpmc_ben1.mii2_col */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1)\t\t/* gpmc_a0.mii2_txen */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1)\t/* gpmc_a1.mii2_rxdv */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1)\t\t/* gpmc_a2.mii2_txd3 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1)\t\t/* gpmc_a3.mii2_txd2 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1)\t\t/* gpmc_a4.mii2_txd1 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1)\t\t/* gpmc_a5.mii2_txd0 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE1)\t/* gpmc_a6.mii2_txclk */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE1)\t/* gpmc_a7.mii2_rxclk */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE1)\t/* gpmc_a8.mii2_rxd3 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE1)\t /* gpmc_a9.mii2_rxd2 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE1)\t/* gpmc_a10.mii2_rxd1 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE1)\t/* gpmc_a11.mii2_rxd0 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE1)\t/* gpmc_wpn.mii2_rxerr */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE1)\t/* gpmc_ben1.mii2_col */\n \t\t>;\n \t};\n };\n@@ -112,15 +112,15 @@\n \tuser_gpios_pins: pinmux_user_gpios {\n \t\tpinctrl-single,pins = <\n \t\t\t/* DIGIN 1-4 */\n-\t\t\tAM33XX_IOPAD(0x82C, PIN_INPUT | MUX_MODE7)\t\t/* gpmc_ad11.gpio0_27 */\n-\t\t\tAM33XX_IOPAD(0x828, PIN_INPUT | MUX_MODE7)\t\t/* gpmc_ad10.gpio0_26 */\n-\t\t\tAM33XX_IOPAD(0x824, PIN_INPUT | MUX_MODE7)\t\t/* gpmc_ad9.gpio0_23 */\n-\t\t\tAM33XX_IOPAD(0x820, PIN_INPUT | MUX_MODE7)\t\t/* gpmc_ad8.gpio0_22 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_INPUT, MUX_MODE7)\t\t/* gpmc_ad11.gpio0_27 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_INPUT, MUX_MODE7)\t\t/* gpmc_ad10.gpio0_26 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_INPUT, MUX_MODE7)\t\t/* gpmc_ad9.gpio0_23 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_INPUT, MUX_MODE7)\t\t/* gpmc_ad8.gpio0_22 */\n \t\t\t/* DIGOUT 1-4 */\n-\t\t\tAM33XX_IOPAD(0x83C, PIN_OUTPUT | MUX_MODE7)\t\t/* gpmc_ad15.gpio1_15 */\n-\t\t\tAM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE7)\t\t/* gpmc_ad14.gpio1_14 */\n-\t\t\tAM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE7)\t\t/* gpmc_ad13.gpio1_13 */\n-\t\t\tAM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE7)\t\t/* gpmc_ad12.gpio1_12 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_OUTPUT, MUX_MODE7)\t\t/* gpmc_ad15.gpio1_15 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_OUTPUT, MUX_MODE7)\t\t/* gpmc_ad14.gpio1_14 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_OUTPUT, MUX_MODE7)\t\t/* gpmc_ad13.gpio1_13 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_OUTPUT, MUX_MODE7)\t\t/* gpmc_ad12.gpio1_12 */\n \t\t>;\n \t};\n };\n@@ -129,13 +129,13 @@\n &am33xx_pinmux {\n \tmmc1_pins: pinmux_mmc1 {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x8F0, PIN_INPUT_PULLUP | MUX_MODE0)\n-\t\t\tAM33XX_IOPAD(0x8F4, PIN_INPUT_PULLUP | MUX_MODE0)\n-\t\t\tAM33XX_IOPAD(0x8F8, PIN_INPUT_PULLUP | MUX_MODE0)\n-\t\t\tAM33XX_IOPAD(0x8FC, PIN_INPUT_PULLUP | MUX_MODE0)\n-\t\t\tAM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)\n-\t\t\tAM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)\n-\t\t\tAM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE7)\t/* spi0_cs1.mmc0_sdcd */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7)\t/* spi0_cs1.mmc0_sdcd */\n \t\t>;\n \t};\n };\n@@ -158,15 +158,15 @@\n &am33xx_pinmux {\n \tuart0_pins: pinmux_uart0 {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)\n-\t\t\tAM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)\n \t\t>;\n \t};\n \n \tuart2_pins: pinmux_uart2 {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x92C, PIN_INPUT_PULLUP | MUX_MODE1)\t/* mii1_tx_clk.uart2_rxd */\n-\t\t\tAM33XX_IOPAD(0x930, PIN_OUTPUT_PULLDOWN | MUX_MODE1)\t/* mii1_rx_clk.uart2_txd */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE1)\t/* mii1_tx_clk.uart2_rxd */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE1)\t/* mii1_rx_clk.uart2_txd */\n \t\t>;\n \t};\n };\n@@ -187,9 +187,9 @@\n &am33xx_pinmux {\n \tuart1_rs485_pins: pinmux_uart1_rs485_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0)\n-\t\t\tAM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0)\n-\t\t\tAM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLUP | MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLUP, MUX_MODE0)\n \t\t>;\n \t};\n };\ndiff --git a/arch/arm/dts/am335x-shc.dts b/arch/arm/dts/am335x-shc.dts\nindex a41a0606b1a..7724428e661 100644\n--- a/arch/arm/dts/am335x-shc.dts\n+++ b/arch/arm/dts/am335x-shc.dts\n@@ -383,193 +383,191 @@\n \tclkout2_pin: pinmux_clkout2_pin {\n \t\tpinctrl-single,pins = <\n \t\t\t/* xdma_event_intr1.clkout2 */\n-\t\t\tAM33XX_IOPAD(0x9b4, PIN_INPUT | MUX_MODE6)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_INPUT, MUX_MODE6)\n \t\t>;\n \t};\n \n \tcpsw_default: cpsw_default {\n \t\tpinctrl-single,pins = <\n \t\t\t/* Slave 1 */\n-\t\t\tAM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE0)\n-\t\t\tAM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0)\n-\t\t\tAM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE0)\n-\t\t\tAM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)\n-\t\t\tAM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0)\n-\t\t\tAM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE0)\n-\t\t\tAM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE0)\n-\t\t\tAM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE0)\n-\t\t\tAM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE0)\n-\t\t\tAM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE0)\n-\t\t\tAM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE0)\n-\t\t\tAM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE0)\n-\t\t\tAM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE0)\n \t\t>;\n \t};\n \n \tcpsw_sleep: cpsw_sleep {\n \t\tpinctrl-single,pins = <\n \t\t\t/* Slave 1 reset value */\n-\t\t\tAM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)\n \t\t>;\n \t};\n \n \tdavinci_mdio_default: davinci_mdio_default {\n \t\tpinctrl-single,pins = <\n-\t\t\t/* mdio_data.mdio_data */\n-\t\t\tAM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)\n-\t\t\t/* mdio_clk.mdio_clk */\n-\t\t\tAM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)\n \t\t>;\n \t};\n \n \tdavinci_mdio_sleep: davinci_mdio_sleep {\n \t\tpinctrl-single,pins = <\n \t\t\t/* MDIO reset value */\n-\t\t\tAM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)\n \t\t>;\n \t};\n \n \tehrpwm1_pins: pinmux_ehrpwm1 {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE6) /* gpmc_a3.gpio1_19 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE6) /* gpmc_a3.gpio1_19 */\n \t\t>;\n \t};\n \n \temmc_pins: pinmux_emmc_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x880, PIN_INPUT | MUX_MODE2)\n-\t\t\tAM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2)\n-\t\t\tAM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1)\n-\t\t\tAM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1)\n-\t\t\tAM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1)\n-\t\t\tAM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1)\n-\t\t\tAM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1)\n-\t\t\tAM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1)\n-\t\t\tAM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1)\n-\t\t\tAM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT, MUX_MODE2)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1)\n \t\t>;\n \t};\n \n \ti2c0_pins: pinmux_i2c0_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0)\n-\t\t\tAM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)\n \t\t>;\n \t};\n \n \tmmc1_pins: pinmux_mmc1_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE5)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE5)\n \t\t>;\n \t};\n \n \tmmc3_pins: pinmux_mmc3_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x830, PIN_INPUT | MUX_MODE3)\n-\t\t\tAM33XX_IOPAD(0x834, PIN_INPUT | MUX_MODE3)\n-\t\t\tAM33XX_IOPAD(0x838, PIN_INPUT | MUX_MODE3)\n-\t\t\tAM33XX_IOPAD(0x83c, PIN_INPUT | MUX_MODE3)\n-\t\t\tAM33XX_IOPAD(0x888, PIN_INPUT | MUX_MODE3)\n-\t\t\tAM33XX_IOPAD(0x88c, PIN_INPUT | MUX_MODE3)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT, MUX_MODE3)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT, MUX_MODE3)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD14, PIN_INPUT, MUX_MODE3)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT, MUX_MODE3)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_CSN3, PIN_INPUT, MUX_MODE3)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_CLK, PIN_INPUT, MUX_MODE3)\n \t\t>;\n \t};\n \n \tuart0_pins: pinmux_uart0_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x968, PIN_INPUT_PULLDOWN | MUX_MODE0)\n-\t\t\tAM33XX_IOPAD(0x96c, PIN_OUTPUT | MUX_MODE0)\n-\t\t\tAM33XX_IOPAD(0x970, PIN_INPUT_PULLDOWN | MUX_MODE0)\n-\t\t\tAM33XX_IOPAD(0x974, PIN_OUTPUT | MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT, MUX_MODE0)\n \t\t>;\n \t};\n \n \tuart1_pins: pinmux_uart1 {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x978, PIN_INPUT_PULLDOWN | MUX_MODE0)\n-\t\t\tAM33XX_IOPAD(0x97C, PIN_OUTPUT | MUX_MODE0)\n-\t\t\tAM33XX_IOPAD(0x980, PIN_INPUT | MUX_MODE0)\n-\t\t\tAM33XX_IOPAD(0x984, PIN_OUTPUT | MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT, MUX_MODE0)\n \t\t>;\n \t};\n \n \tuart2_pins: pinmux_uart2_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x950, PIN_INPUT | MUX_MODE1)\n-\t\t\tAM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE1)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT, MUX_MODE1)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_OUTPUT, MUX_MODE1)\n \t\t>;\n \t};\n \n \tuart4_pins: pinmux_uart4_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6)\n-\t\t\tAM33XX_IOPAD(0x874, PIN_OUTPUT_PULLUP | MUX_MODE6)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLUP, MUX_MODE6)\n \t\t>;\n \t};\n \n \tuser_leds_s0: user_leds_s0 {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x844, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x850, PIN_OUTPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x85c, PIN_OUTPUT_PULLUP | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x860, PIN_INPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x86c, PIN_INPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x878, PIN_OUTPUT_PULLUP | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x87c, PIN_INPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x894, PIN_INPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x958, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x964, PIN_OUTPUT_PULLUP | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x9a0, PIN_OUTPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x9a4, PIN_OUTPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x9a8, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x9ac, PIN_INPUT_PULLUP | MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD8, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD9, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD10, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD11, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT_PULLUP, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_OUTPUT_PULLUP, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_INPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_INPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA0, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA1, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA2, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA3, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA4, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA5, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA6, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA7, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA8, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA9, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA14, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_DATA15, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_VSYNC, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_HSYNC, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_PCLK, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_LCD_AC_BIAS_EN, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_OUTPUT, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT_PULLUP, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKR, PIN_OUTPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MCASP0_FSR, PIN_OUTPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_INPUT_PULLUP, MUX_MODE7)\n \t\t>;\n \t};\n };\ndiff --git a/arch/arm/dts/am335x-sl50.dts b/arch/arm/dts/am335x-sl50.dts\nindex 423f46613bb..644ba4b2c2c 100644\n--- a/arch/arm/dts/am335x-sl50.dts\n+++ b/arch/arm/dts/am335x-sl50.dts\n@@ -119,126 +119,126 @@\n \n \tled_pins: pinmux_led_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE7)\t/* gpmc_a5.gpio1_21 */\n-\t\t\tAM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7)\t/* gpmc_a6.gpio1_22 */\n-\t\t\tAM33XX_IOPAD(0x85c, PIN_OUTPUT | MUX_MODE7)\t/* gpmc_a7.gpio1_23 */\n-\t\t\tAM33XX_IOPAD(0x860, PIN_OUTPUT | MUX_MODE7)\t/* gpmc_a8.gpio1_24 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE7)\t/* gpmc_a5.gpio1_21 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_OUTPUT, MUX_MODE7)\t/* gpmc_a6.gpio1_22 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_OUTPUT, MUX_MODE7)\t/* gpmc_a7.gpio1_23 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_OUTPUT, MUX_MODE7)\t/* gpmc_a8.gpio1_24 */\n \t\t>;\n \t};\n \n \tuart0_pins: pinmux_uart0_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)\t/* uart0_rxd.uart0_rxd */\n-\t\t\tAM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)\t/* uart0_txd.uart0_txd */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)\n \t\t>;\n \t};\n \n \tuart1_pins: pinmux_uart1_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0)\t/* uart1_rxd.uart1_rxd */\n-\t\t\tAM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0)\t/* uart1_txd.uart1_txd */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)\n \t\t>;\n \t};\n \n \tuart4_pins: pinmux_uart4_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE6)\t/* gpmc_wait0.uart4_rxd */\n-\t\t\tAM33XX_IOPAD(0x874, PIN_OUTPUT_PULLDOWN | MUX_MODE6)\t/* gpmc_wpn.uart4_txd */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE6)\t/* gpmc_wait0.uart4_rxd */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_OUTPUT_PULLDOWN, MUX_MODE6)\t/* gpmc_wpn.uart4_txd */\n \t\t>;\n \t};\n \n \ti2c0_pins: pinmux_i2c0_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0)\t/* i2c0_sda.i2c0_sda */\n-\t\t\tAM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0)\t/* i2c0_scl.i2c0_scl */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)\n \t\t>;\n \t};\n \n \ti2c2_pins: pinmux_i2c2_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x978, PIN_INPUT_PULLUP | MUX_MODE3)\t/* uart1_ctsn.i2c2_sda */\n-\t\t\tAM33XX_IOPAD(0x97c, PIN_INPUT_PULLUP | MUX_MODE3)\t/* uart1_rtsn.i2c2_scl */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3)\t/* uart1_ctsn.i2c2_sda */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3)\t/* uart1_rtsn.i2c2_scl */\n \t\t>;\n \t};\n \n \tcpsw_default: cpsw_default {\n \t\tpinctrl-single,pins = <\n \t\t\t/* Slave 1 */\n-\t\t\tAM33XX_IOPAD(0x910, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mii1_rxerr.mii1_rxerr */\n-\t\t\tAM33XX_IOPAD(0x914, PIN_OUTPUT_PULLDOWN | MUX_MODE0)\t/* mii1_txen.mii1_txen */\n-\t\t\tAM33XX_IOPAD(0x918, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mii1_rxdv.mii1_rxdv */\n-\t\t\tAM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)\t/* mii1_txd3.mii1_txd3 */\n-\t\t\tAM33XX_IOPAD(0x920, PIN_OUTPUT_PULLDOWN | MUX_MODE0)\t/* mii1_txd2.mii1_txd2 */\n-\t\t\tAM33XX_IOPAD(0x924, PIN_OUTPUT_PULLDOWN | MUX_MODE0)\t/* mii1_txd1.mii1_txd1 */\n-\t\t\tAM33XX_IOPAD(0x928, PIN_OUTPUT_PULLDOWN | MUX_MODE0)\t/* mii1_txd0.mii1_txd0 */\n-\t\t\tAM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mii1_txclk.mii1_txclk */\n-\t\t\tAM33XX_IOPAD(0x930, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mii1_rxclk.mii1_rxclk */\n-\t\t\tAM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mii1_rxd3.mii1_rxd3 */\n-\t\t\tAM33XX_IOPAD(0x938, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mii1_rxd2.mii1_rxd2 */\n-\t\t\tAM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mii1_rxd1.mii1_rxd1 */\n-\t\t\tAM33XX_IOPAD(0x940, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mii1_rxd0.mii1_rxd0 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLUP, MUX_MODE0)\n \t\t>;\n \t};\n \n \tcpsw_sleep: cpsw_sleep {\n \t\tpinctrl-single,pins = <\n \t\t\t/* Slave 1 reset value */\n-\t\t\tAM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x918, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x91c, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x92c, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x930, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x934, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x938, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)\n \t\t>;\n \t};\n \n \tdavinci_mdio_default: davinci_mdio_default {\n \t\tpinctrl-single,pins = <\n \t\t\t/* MDIO */\n-\t\t\tAM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)\t/* mdio_data.mdio_data */\n-\t\t\tAM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)\t\t\t/* mdio_clk.mdio_clk */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)\n \t\t>;\n \t};\n \n \tdavinci_mdio_sleep: davinci_mdio_sleep {\n \t\tpinctrl-single,pins = <\n \t\t\t/* MDIO reset value */\n-\t\t\tAM33XX_IOPAD(0x948, PIN_INPUT_PULLDOWN | MUX_MODE7)\n-\t\t\tAM33XX_IOPAD(0x94c, PIN_INPUT_PULLDOWN | MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLDOWN, MUX_MODE7)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MDC, PIN_INPUT_PULLDOWN, MUX_MODE7)\n \t\t>;\n \t};\n \n \tmmc1_pins: pinmux_mmc1_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x96c, PIN_INPUT | MUX_MODE7)\t\t/* uart0_rtsn.gpio1_9 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT, MUX_MODE7)\t\t/* uart0_rtsn.gpio1_9 */\n \t\t>;\n \t};\n \n \temmc_pwrseq_pins: pinmux_emmc_pwrseq_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x850, PIN_OUTPUT_PULLUP | MUX_MODE7)\t/* gpmc_a4.gpio1_20 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT_PULLUP, MUX_MODE7)\t/* gpmc_a4.gpio1_20 */\n \t\t>;\n \t};\n \n \temmc_pins: pinmux_emmc_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x880, PIN_INPUT_PULLUP | MUX_MODE2)\t/* gpmc_csn1.mmc1_clk */\n-\t\t\tAM33XX_IOPAD(0x884, PIN_INPUT_PULLUP | MUX_MODE2)\t/* gpmc_csn2.mmc1_cmd */\n-\t\t\tAM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE1)\t/* gpmc_ad0.mmc1_dat0 */\n-\t\t\tAM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE1)\t/* gpmc_ad1.mmc1_dat1 */\n-\t\t\tAM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE1)\t/* gpmc_ad2.mmc1_dat2 */\n-\t\t\tAM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE1)\t/* gpmc_ad3.mmc1_dat3 */\n-\t\t\tAM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE1)\t/* gpmc_ad4.mmc1_dat4 */\n-\t\t\tAM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE1) \t/* gpmc_ad5.mmc1_dat5 */\n-\t\t\tAM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE1)\t/* gpmc_ad6.mmc1_dat6 */\n-\t\t\tAM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE1)\t/* gpmc_ad7.mmc1_dat7 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2)\t/* gpmc_csn1.mmc1_clk */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2)\t/* gpmc_csn2.mmc1_cmd */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1)\t/* gpmc_ad0.mmc1_dat0 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1)\t/* gpmc_ad1.mmc1_dat1 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1)\t/* gpmc_ad2.mmc1_dat2 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1)\t/* gpmc_ad3.mmc1_dat3 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1)\t/* gpmc_ad4.mmc1_dat4 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1) \t/* gpmc_ad5.mmc1_dat5 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1)\t/* gpmc_ad6.mmc1_dat6 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1)\t/* gpmc_ad7.mmc1_dat7 */\n \t\t>;\n \t};\n \n@@ -261,11 +261,11 @@\n \n \tspi0_pins: pinmux_spi0_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0)\t/* SPI0_MOSI - spi0_d0.spi0_d0 */\n-\t\t\tAM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0)\t/* SPI0_MISO - spi0_d1.spi0_d1 */\n-\t\t\tAM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0)\t/* SPI0_CLK  - spi0_clk.spi0_clk */\n-\t\t\tAM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0)\t/* SPI0_CS0 (NBATTSS) - spi0_cs0.spi0_cs0 */\n-\t\t\tAM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE0)\t/* SPI0_CS1 (FPGA_FLASH_NCS) - spi0_cs1.spi0_cs1 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLUP, MUX_MODE0)\t/* SPI0_MOSI */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)\t/* SPI0_MISO */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)\t/* SPI0_CS0 (NBATTSS) */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE0)\t/* SPI0_CS1 (FPGA_FLASH_NCS) */\n \t\t>;\n \t};\n \n@@ -273,13 +273,13 @@\n \t\tpinctrl-single,pins = <\n \t\t\tAM33XX_IOPAD(0x9a4, PIN_OUTPUT | MUX_MODE7)\t/* SoundPA_en - mcasp0_fsr.gpio3_19 */\n \t\t\tAM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE7)\t/* nKbdOnC - gpmc_ad10.gpio0_26 */\n-\t\t\tAM33XX_IOPAD(0x830, PIN_INPUT_PULLUP | MUX_MODE7)\t/* nKbdInt - gpmc_ad12.gpio1_12 */\n-\t\t\tAM33XX_IOPAD(0x834, PIN_INPUT_PULLUP | MUX_MODE7)\t/* nKbdReset - gpmc_ad13.gpio1_13 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD12, PIN_INPUT_PULLUP, MUX_MODE7)\t/* nKbdInt - gpmc_ad12.gpio1_12 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD13, PIN_INPUT_PULLUP, MUX_MODE7)\t/* nKbdReset - gpmc_ad13.gpio1_13 */\n \t\t\tAM33XX_IOPAD(0x838, PIN_INPUT_PULLUP | MUX_MODE7)\t/* nDispReset - gpmc_ad14.gpio1_14 */\n-\t\t\tAM33XX_IOPAD(0x844, PIN_INPUT_PULLUP | MUX_MODE7)\t/* USB1_enPower - gpmc_a1.gpio1_17 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLUP, MUX_MODE7)\t/* USB1_enPower - gpmc_a1.gpio1_17 */\n \t\t\t/* PDI Bus - Battery system */\n-\t\t\tAM33XX_IOPAD(0x840, PIN_INPUT_PULLUP | MUX_MODE7)\t/* nBattReset  gpmc_a0.gpio1_16 */\n-\t\t\tAM33XX_IOPAD(0x83c, PIN_INPUT_PULLUP | MUX_MODE7)\t/* BattPDIData gpmc_ad15.gpio1_15 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_INPUT_PULLUP, MUX_MODE7)\t/* nBattReset  gpmc_a0.gpio1_16 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_AD15, PIN_INPUT_PULLUP, MUX_MODE7)\t/* BattPDIData gpmc_ad15.gpio1_15 */\n \t\t>;\n \t};\n };\ndiff --git a/arch/arm/dts/am335x-wega.dtsi b/arch/arm/dts/am335x-wega.dtsi\nindex 93902aa5c2f..3efcf31b84c 100644\n--- a/arch/arm/dts/am335x-wega.dtsi\n+++ b/arch/arm/dts/am335x-wega.dtsi\n@@ -29,11 +29,11 @@\n &am33xx_pinmux {\n \tmcasp0_pins: pinmux_mcasp0 {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x9AC, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahclkx.mcasp0_ahclkx */\n-\t\t\tAM33XX_IOPAD(0x990, PIN_INPUT_PULLDOWN | MUX_MODE0)  /* mcasp0_aclkx.mcasp0_aclkx */\n-\t\t\tAM33XX_IOPAD(0x994, PIN_INPUT_PULLDOWN | MUX_MODE0)  /* mcasp0_fsx.mcasp0_fsx */\n-\t\t\tAM33XX_IOPAD(0x998, PIN_INPUT_PULLDOWN | MUX_MODE0)  /* mcasp0_axr0.mcasp0_axr0 */\n-\t\t\tAM33XX_IOPAD(0x9A8, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr1.mcasp0_axr1 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MCASP0_AHCLKX, PIN_OUTPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MCASP0_ACLKX, PIN_INPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MCASP0_FSX, PIN_INPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MCASP0_AXR0, PIN_INPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MCASP0_AXR1, PIN_OUTPUT_PULLDOWN, MUX_MODE0)\n \t\t>;\n \t};\n };\n@@ -81,8 +81,8 @@\n &am33xx_pinmux {\n \tdcan1_pins: pinmux_dcan1 {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x968, PIN_OUTPUT_PULLUP | MUX_MODE2) /* uart0_ctsn.d_can1_tx */\n-\t\t\tAM33XX_IOPAD(0x96c, PIN_INPUT_PULLUP | MUX_MODE2) /* uart0_rtsn.d_can1_rx */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_OUTPUT_PULLUP, MUX_MODE2) /* uart0_ctsn.d_can1_tx */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_INPUT_PULLUP, MUX_MODE2) /* uart0_rtsn.d_can1_rx */\n \t\t>;\n \t};\n };\n@@ -97,20 +97,20 @@\n &am33xx_pinmux {\n \tethernet1_pins: pinmux_ethernet1 {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1)\t\t/* gpmc_a0.mii2_txen */\n-\t\t\tAM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE1)\t/* gpmc_a1.mii2_rxdv */\n-\t\t\tAM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1)\t\t/* gpmc_a2.mii2_txd3 */\n-\t\t\tAM33XX_IOPAD(0x84c, PIN_OUTPUT | MUX_MODE1)\t\t/* gpmc_a3.mii2_txd2 */\n-\t\t\tAM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1)\t\t/* gpmc_a4.mii2_txd1 */\n-\t\t\tAM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1)\t\t/* gpmc_a5.mii2_txd0 */\n-\t\t\tAM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE1)\t/* gpmc_a6.mii2_txclk */\n-\t\t\tAM33XX_IOPAD(0x85c, PIN_INPUT_PULLDOWN | MUX_MODE1)\t/* gpmc_a7.mii2_rxclk */\n-\t\t\tAM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE1)\t/* gpmc_a8.mii2_rxd3 */\n-\t\t\tAM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE1)\t/* gpmc_a9.mii2_rxd2 */\n-\t\t\tAM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE1)\t/* gpmc_a10.mii2_rxd1 */\n-\t\t\tAM33XX_IOPAD(0x86c, PIN_INPUT_PULLDOWN | MUX_MODE1)\t/* gpmc_a11.mii2_rxd0 */\n-\t\t\tAM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE1)\t/* gpmc_wpn.mii2_rxerr */\n-\t\t\tAM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE1)\t/* gpmc_ben1.mii2_col */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A0, PIN_OUTPUT, MUX_MODE1)\t\t/* gpmc_a0.mii2_txen */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A1, PIN_INPUT_PULLDOWN, MUX_MODE1)\t/* gpmc_a1.mii2_rxdv */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A2, PIN_OUTPUT, MUX_MODE1)\t\t/* gpmc_a2.mii2_txd3 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A3, PIN_OUTPUT, MUX_MODE1)\t\t/* gpmc_a3.mii2_txd2 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A4, PIN_OUTPUT, MUX_MODE1)\t\t/* gpmc_a4.mii2_txd1 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A5, PIN_OUTPUT, MUX_MODE1)\t\t/* gpmc_a5.mii2_txd0 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A6, PIN_INPUT_PULLDOWN, MUX_MODE1)\t/* gpmc_a6.mii2_txclk */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A7, PIN_INPUT_PULLDOWN, MUX_MODE1)\t/* gpmc_a7.mii2_rxclk */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A8, PIN_INPUT_PULLDOWN, MUX_MODE1)\t/* gpmc_a8.mii2_rxd3 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A9, PIN_INPUT_PULLDOWN, MUX_MODE1)\t/* gpmc_a9.mii2_rxd2 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A10, PIN_INPUT_PULLDOWN, MUX_MODE1)\t/* gpmc_a10.mii2_rxd1 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_A11, PIN_INPUT_PULLDOWN, MUX_MODE1)\t/* gpmc_a11.mii2_rxd0 */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLDOWN, MUX_MODE1)\t/* gpmc_wpn.mii2_rxerr */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_GPMC_BEN1, PIN_INPUT_PULLDOWN, MUX_MODE1)\t/* gpmc_ben1.mii2_col */\n \t\t>;\n \t};\n };\n@@ -138,13 +138,13 @@\n &am33xx_pinmux {\n \tmmc1_pins: pinmux_mmc1 {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc0_dat3.mmc0_dat3 */\n-\t\t\tAM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc0_dat2.mmc0_dat2 */\n-\t\t\tAM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc0_dat1.mmc0_dat1 */\n-\t\t\tAM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc0_dat0.mmc0_dat0 */\n-\t\t\tAM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc0_clk.mmc0_clk */\n-\t\t\tAM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)\t/* mmc0_cmd.mmc0_cmd */\n-\t\t\tAM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE7)\t/* spi0_cs1.mmc0_sdcd */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT_PULLUP, MUX_MODE7)\t/* spi0_cs1.mmc0_sdcd */\n \t\t>;\n \t};\n };\n@@ -168,17 +168,17 @@\n &am33xx_pinmux {\n \tuart0_pins: pinmux_uart0 {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)    /* uart0_rxd.uart0_rxd */\n-\t\t\tAM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)\n \t\t>;\n \t};\n \n \tuart1_pins: pinmux_uart1_pins {\n \t\tpinctrl-single,pins = <\n-\t\t\tAM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0)\t/* uart1_rxd.uart1_rxd */\n-\t\t\tAM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0)\t/* uart1_txd.uart1_txd */\n-\t\t\tAM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0)\t\t/* uart1_ctsn.uart1_ctsn */\n-\t\t\tAM33XX_IOPAD(0x97c, PIN_OUTPUT_PULLDOWN | MUX_MODE0)\t/* uart1_rtsn.uart1_rtsn */\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_RXD, PIN_INPUT_PULLUP, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT, MUX_MODE0)\n+\t\t\tAM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_OUTPUT_PULLDOWN, MUX_MODE0)\n \t\t>;\n \t};\n };\n",
    "prefixes": [
        "10/17"
    ]
}