Patch Detail

HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 1767778,
    "url": "http://patchwork.ozlabs.org/api/patches/1767778/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20230411182510.22158-14-afd@ti.com/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20230411182510.22158-14-afd@ti.com>",
    "list_archive_url": null,
    "date": "2023-04-11T18:25:06",
    "name": "[13/17] arm: dts: dra7x: Non-functional changes sync with v6.3-rc6",
    "commit_ref": "f8ae3e605b1ab8e7ac5f34ac8a8e7a44979c6168",
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "b27c2a2ad6ff612bccd7cdb590c59a08954410b6",
    "submitter": {
        "id": 67226,
        "url": "http://patchwork.ozlabs.org/api/people/67226/?format=api",
        "name": "Andrew Davis",
        "email": "afd@ti.com"
    },
    "delegate": {
        "id": 3651,
        "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api",
        "username": "trini",
        "first_name": "Tom",
        "last_name": "Rini",
        "email": "trini@ti.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20230411182510.22158-14-afd@ti.com/mbox/",
    "series": [
        {
            "id": 350384,
            "url": "http://patchwork.ozlabs.org/api/series/350384/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=350384",
            "date": "2023-04-11T18:24:56",
            "name": "Sync TI Device Trees with Linux v6.3-rc6",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/350384/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/1767778/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/1767778/checks/",
    "tags": {},
    "related": [],
    "headers": {
        "Return-Path": "<u-boot-bounces@lists.denx.de>",
        "X-Original-To": "incoming@patchwork.ozlabs.org",
        "Delivered-To": "patchwork-incoming@legolas.ozlabs.org",
        "Authentication-Results": [
            "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)",
            "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=ti.com header.i=@ti.com header.a=rsa-sha256\n header.s=ti-com-17Q1 header.b=Z7HDykoe;\n\tdkim-atps=neutral",
            "phobos.denx.de;\n dmarc=pass (p=quarantine dis=none) header.from=ti.com",
            "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de",
            "phobos.denx.de;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=ti.com header.i=@ti.com header.b=\"Z7HDykoe\";\n\tdkim-atps=neutral",
            "phobos.denx.de;\n dmarc=pass (p=quarantine dis=none) header.from=ti.com",
            "phobos.denx.de; spf=pass smtp.mailfrom=afd@ti.com"
        ],
        "Received": [
            "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature ECDSA (P-384))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4PwvXT5k4xz1yZP\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 12 Apr 2023 04:30:17 +1000 (AEST)",
            "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 873788601F;\n\tTue, 11 Apr 2023 20:27:35 +0200 (CEST)",
            "by phobos.denx.de (Postfix, from userid 109)\n id 9A38583A35; Tue, 11 Apr 2023 20:26:27 +0200 (CEST)",
            "from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 8C1A885F73\n for <u-boot@lists.denx.de>; Tue, 11 Apr 2023 20:25:23 +0200 (CEST)",
            "from lelv0266.itg.ti.com ([10.180.67.225])\n by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 33BIPISK033242;\n Tue, 11 Apr 2023 13:25:18 -0500",
            "from DLEE115.ent.ti.com (dlee115.ent.ti.com [157.170.170.26])\n by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 33BIPICm075484\n (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL);\n Tue, 11 Apr 2023 13:25:18 -0500",
            "from DLEE103.ent.ti.com (157.170.170.33) by DLEE115.ent.ti.com\n (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Tue, 11\n Apr 2023 13:25:17 -0500",
            "from fllv0040.itg.ti.com (10.64.41.20) by DLEE103.ent.ti.com\n (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via\n Frontend Transport; Tue, 11 Apr 2023 13:25:17 -0500",
            "from ula0226330.dal.design.ti.com (ileaxei01-snat.itg.ti.com\n [10.180.69.5])\n by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 33BIPAC7109488;\n Tue, 11 Apr 2023 13:25:17 -0500"
        ],
        "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de",
        "X-Spam-Level": "",
        "X-Spam-Status": "No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,\n DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,\n SPF_PASS autolearn=ham autolearn_force=no version=3.4.2",
        "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com;\n s=ti-com-17Q1; t=1681237518;\n bh=ZSRaVFu5wpoFIR1+AjP7yIcbf9Q0E3loHjXxEpWSsMg=;\n h=From:To:CC:Subject:Date:In-Reply-To:References;\n b=Z7HDykoeJwYdX7StAvG66rpxSBvTvsrpK4jrZdH5jTyGzAPSaVLMGCIj+gFk0zXyk\n 1osGcjcseUGhUjHTU3IXVknnresKIaq1hxGJVDYM8212pdszPbzDPhn98sw1QvIlqV\n q1+CvlOklAyue/31ThLgcCZQ+7sIIk1oD56eDoJQ=",
        "From": "Andrew Davis <afd@ti.com>",
        "To": "Simon Glass <sjg@chromium.org>, Tom Rini <trini@konsulko.com>, Nishanth\n Menon <nm@ti.com>, Vignesh Raghavendra <vigneshr@ti.com>,\n <u-boot@lists.denx.de>",
        "CC": "Andrew Davis <afd@ti.com>",
        "Subject": "[PATCH 13/17] arm: dts: dra7x: Non-functional changes sync with\n v6.3-rc6",
        "Date": "Tue, 11 Apr 2023 13:25:06 -0500",
        "Message-ID": "<20230411182510.22158-14-afd@ti.com>",
        "X-Mailer": "git-send-email 2.39.2",
        "In-Reply-To": "<20230411182510.22158-1-afd@ti.com>",
        "References": "<20230411182510.22158-1-afd@ti.com>",
        "MIME-Version": "1.0",
        "Content-Transfer-Encoding": "8bit",
        "Content-Type": "text/plain",
        "X-EXCLAIMER-MD-CONFIG": "e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180",
        "X-BeenThere": "u-boot@lists.denx.de",
        "X-Mailman-Version": "2.1.39",
        "Precedence": "list",
        "List-Id": "U-Boot discussion <u-boot.lists.denx.de>",
        "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>",
        "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>",
        "List-Post": "<mailto:u-boot@lists.denx.de>",
        "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>",
        "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>",
        "Errors-To": "u-boot-bounces@lists.denx.de",
        "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>",
        "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de",
        "X-Virus-Status": "Clean"
    },
    "content": "This is a collection of all the whitespace, renames, comment, and other\nchanges that should not change the DT functionality from Linux v6.3-rc6.\n\nSigned-off-by: Andrew Davis <afd@ti.com>\n---\n arch/arm/dts/am571x-idk.dts                |   6 +-\n arch/arm/dts/am572x-idk-common.dtsi        |   8 +-\n arch/arm/dts/am57xx-beagle-x15-common.dtsi |   8 +-\n arch/arm/dts/am57xx-idk-common.dtsi        |   4 +-\n arch/arm/dts/dra7-evm-common.dtsi          |  12 +-\n arch/arm/dts/dra7-evm.dts                  |   4 +-\n arch/arm/dts/dra7.dtsi                     |  16 +-\n arch/arm/dts/dra71-evm.dts                 |   2 +-\n arch/arm/dts/dra72-evm-common.dtsi         |  14 +-\n arch/arm/dts/dra72-evm-tps65917.dtsi       |   2 +-\n arch/arm/dts/dra72x.dtsi                   |   6 +-\n arch/arm/dts/dra74x.dtsi                   |   8 +-\n arch/arm/dts/dra76-evm.dts                 |   4 +-\n arch/arm/dts/dra7xx-clocks.dtsi            | 352 ++++++++++-----------\n 14 files changed, 226 insertions(+), 220 deletions(-)",
    "diff": "diff --git a/arch/arm/dts/am571x-idk.dts b/arch/arm/dts/am571x-idk.dts\nindex cca7a25fc13..b3592b22a0c 100644\n--- a/arch/arm/dts/am571x-idk.dts\n+++ b/arch/arm/dts/am571x-idk.dts\n@@ -74,17 +74,17 @@\n \n &mailbox5 {\n \tstatus = \"okay\";\n-\tmbox_ipu1_ipc3x: mbox_ipu1_ipc3x {\n+\tmbox_ipu1_ipc3x: mbox-ipu1-ipc3x {\n \t\tstatus = \"okay\";\n \t};\n-\tmbox_dsp1_ipc3x: mbox_dsp1_ipc3x {\n+\tmbox_dsp1_ipc3x: mbox-dsp1-ipc3x {\n \t\tstatus = \"okay\";\n \t};\n };\n \n &mailbox6 {\n \tstatus = \"okay\";\n-\tmbox_ipu2_ipc3x: mbox_ipu2_ipc3x {\n+\tmbox_ipu2_ipc3x: mbox-ipu2-ipc3x {\n \t\tstatus = \"okay\";\n \t};\n };\ndiff --git a/arch/arm/dts/am572x-idk-common.dtsi b/arch/arm/dts/am572x-idk-common.dtsi\nindex a84987dfb29..c7dc8445d68 100644\n--- a/arch/arm/dts/am572x-idk-common.dtsi\n+++ b/arch/arm/dts/am572x-idk-common.dtsi\n@@ -81,20 +81,20 @@\n \n &mailbox5 {\n \tstatus = \"okay\";\n-\tmbox_ipu1_ipc3x: mbox_ipu1_ipc3x {\n+\tmbox_ipu1_ipc3x: mbox-ipu1-ipc3x {\n \t\tstatus = \"okay\";\n \t};\n-\tmbox_dsp1_ipc3x: mbox_dsp1_ipc3x {\n+\tmbox_dsp1_ipc3x: mbox-dsp1-ipc3x {\n \t\tstatus = \"okay\";\n \t};\n };\n \n &mailbox6 {\n \tstatus = \"okay\";\n-\tmbox_ipu2_ipc3x: mbox_ipu2_ipc3x {\n+\tmbox_ipu2_ipc3x: mbox-ipu2-ipc3x {\n \t\tstatus = \"okay\";\n \t};\n-\tmbox_dsp2_ipc3x: mbox_dsp2_ipc3x {\n+\tmbox_dsp2_ipc3x: mbox-dsp2-ipc3x {\n \t\tstatus = \"okay\";\n \t};\n };\ndiff --git a/arch/arm/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/dts/am57xx-beagle-x15-common.dtsi\nindex 5002685396a..22d8d3d0d53 100644\n--- a/arch/arm/dts/am57xx-beagle-x15-common.dtsi\n+++ b/arch/arm/dts/am57xx-beagle-x15-common.dtsi\n@@ -568,20 +568,20 @@\n \n &mailbox5 {\n \tstatus = \"okay\";\n-\tmbox_ipu1_ipc3x: mbox_ipu1_ipc3x {\n+\tmbox_ipu1_ipc3x: mbox-ipu1-ipc3x {\n \t\tstatus = \"okay\";\n \t};\n-\tmbox_dsp1_ipc3x: mbox_dsp1_ipc3x {\n+\tmbox_dsp1_ipc3x: mbox-dsp1-ipc3x {\n \t\tstatus = \"okay\";\n \t};\n };\n \n &mailbox6 {\n \tstatus = \"okay\";\n-\tmbox_ipu2_ipc3x: mbox_ipu2_ipc3x {\n+\tmbox_ipu2_ipc3x: mbox-ipu2-ipc3x {\n \t\tstatus = \"okay\";\n \t};\n-\tmbox_dsp2_ipc3x: mbox_dsp2_ipc3x {\n+\tmbox_dsp2_ipc3x: mbox-dsp2-ipc3x {\n \t\tstatus = \"okay\";\n \t};\n };\ndiff --git a/arch/arm/dts/am57xx-idk-common.dtsi b/arch/arm/dts/am57xx-idk-common.dtsi\nindex 617f7b5553b..b83c9e9e6e1 100644\n--- a/arch/arm/dts/am57xx-idk-common.dtsi\n+++ b/arch/arm/dts/am57xx-idk-common.dtsi\n@@ -437,7 +437,7 @@\n \tstatus = \"okay\";\n \n \tspi-max-frequency = <76800000>;\n-\tm25p80@0 {\n+\tflash@0 {\n \t\tcompatible = \"s25fl256s1\", \"jedec,spi-nor\";\n \t\tspi-max-frequency = <76800000>;\n \t\treg = <0>;\n@@ -453,7 +453,7 @@\n \t\t */\n \t\tpartition@0 {\n \t\t\tlabel = \"QSPI.SPL\";\n-\t\t\treg = <0x00000000 0x000040000>;\n+\t\t\treg = <0x00000000 0x00040000>;\n \t\t};\n \t\tpartition@1 {\n \t\t\tlabel = \"QSPI.u-boot\";\ndiff --git a/arch/arm/dts/dra7-evm-common.dtsi b/arch/arm/dts/dra7-evm-common.dtsi\nindex 7119d441f46..8f3a0058a38 100644\n--- a/arch/arm/dts/dra7-evm-common.dtsi\n+++ b/arch/arm/dts/dra7-evm-common.dtsi\n@@ -129,7 +129,7 @@\n \tstatus = \"okay\";\n \n \tspi-max-frequency = <76800000>;\n-\tm25p80@0 {\n+\tflash@0 {\n \t\tcompatible = \"s25fl256s1\";\n \t\tspi-max-frequency = <76800000>;\n \t\treg = <0>;\n@@ -145,7 +145,7 @@\n \t\t */\n \t\tpartition@0 {\n \t\t\tlabel = \"QSPI.SPL\";\n-\t\t\treg = <0x00000000 0x000010000>;\n+\t\t\treg = <0x00000000 0x00010000>;\n \t\t};\n \t\tpartition@1 {\n \t\t\tlabel = \"QSPI.SPL.backup1\";\n@@ -236,20 +236,20 @@\n \n &mailbox5 {\n \tstatus = \"okay\";\n-\tmbox_ipu1_ipc3x: mbox_ipu1_ipc3x {\n+\tmbox_ipu1_ipc3x: mbox-ipu1-ipc3x {\n \t\tstatus = \"okay\";\n \t};\n-\tmbox_dsp1_ipc3x: mbox_dsp1_ipc3x {\n+\tmbox_dsp1_ipc3x: mbox-dsp1-ipc3x {\n \t\tstatus = \"okay\";\n \t};\n };\n \n &mailbox6 {\n \tstatus = \"okay\";\n-\tmbox_ipu2_ipc3x: mbox_ipu2_ipc3x {\n+\tmbox_ipu2_ipc3x: mbox-ipu2-ipc3x {\n \t\tstatus = \"okay\";\n \t};\n-\tmbox_dsp2_ipc3x: mbox_dsp2_ipc3x {\n+\tmbox_dsp2_ipc3x: mbox-dsp2-ipc3x {\n \t\tstatus = \"okay\";\n \t};\n };\ndiff --git a/arch/arm/dts/dra7-evm.dts b/arch/arm/dts/dra7-evm.dts\nindex e9a76af7c86..5333f171443 100644\n--- a/arch/arm/dts/dra7-evm.dts\n+++ b/arch/arm/dts/dra7-evm.dts\n@@ -312,7 +312,7 @@\n \t\treg = <0x26>;\n \t\tgpio-controller;\n \t\t#gpio-cells = <2>;\n-\t\tp1 {\n+\t\thdmi-audio-hog {\n \t\t\t/* vin6_sel_s0: high: VIN6, low: audio */\n \t\t\tgpio-hog;\n \t\t\tgpios = <1 GPIO_ACTIVE_HIGH>;\n@@ -416,7 +416,7 @@\n \t\t#size-cells = <1>;\n \t\tpartition@0 {\n \t\t\tlabel = \"NAND.SPL\";\n-\t\t\treg = <0x00000000 0x000020000>;\n+\t\t\treg = <0x00000000 0x00020000>;\n \t\t};\n \t\tpartition@1 {\n \t\t\tlabel = \"NAND.SPL.backup1\";\ndiff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts/dra7.dtsi\nindex 02338ae4fff..b1aef6351a0 100644\n--- a/arch/arm/dts/dra7.dtsi\n+++ b/arch/arm/dts/dra7.dtsi\n@@ -132,7 +132,7 @@\n \t * the moment, just use a fake OCP bus entry to represent the whole bus\n \t * hierarchy.\n \t */\n-\tocp {\n+\tocp: ocp {\n \t\tcompatible = \"ti,dra7-l3-noc\", \"simple-bus\";\n \t\t#address-cells = <1>;\n \t\t#size-cells = <1>;\n@@ -355,7 +355,13 @@\n \t\t\t};\n \t\t};\n \n-\t\taxi@1 {\n+\t\t/*\n+\t\t * Register access seems to have complex dependencies and also\n+\t\t * seems to need an enabled phy. See the TRM chapter for \"Table\n+\t\t * 26-678. Main Sequence PCIe Controller Global Initialization\"\n+\t\t * and also dra7xx_pcie_probe().\n+\t\t */\n+\t\taxi1: target-module@51800000 {\n \t\t\tcompatible = \"simple-bus\";\n \t\t\t#size-cells = <1>;\n \t\t\t#address-cells = <1>;\n@@ -370,8 +376,8 @@\n \t\t\t\t#address-cells = <3>;\n \t\t\t\t#size-cells = <2>;\n \t\t\t\tdevice_type = \"pci\";\n-\t\t\t\tranges = <0x81000000 0 0          0x03000 0 0x00010000\n-\t\t\t\t\t  0x82000000 0 0x30013000 0x13000 0 0xffed000>;\n+\t\t\t\tranges = <0x81000000 0 0x00000000 0x30003000 0 0x00010000>,\n+\t\t\t\t\t <0x82000000 0 0x30013000 0x30013000 0 0x0ffed000>;\n \t\t\t\tbus-range = <0x00 0xff>;\n \t\t\t\t#interrupt-cells = <1>;\n \t\t\t\tnum-lanes = <1>;\n@@ -2110,4 +2116,4 @@\n \ttemperature = <120000>; /* milli Celsius */\n };\n \n-/include/ \"dra7xx-clocks.dtsi\"\n+#include \"dra7xx-clocks.dtsi\"\ndiff --git a/arch/arm/dts/dra71-evm.dts b/arch/arm/dts/dra71-evm.dts\nindex d063ab201c1..b3225988e93 100644\n--- a/arch/arm/dts/dra71-evm.dts\n+++ b/arch/arm/dts/dra71-evm.dts\n@@ -157,7 +157,7 @@\n };\n \n &pcf_hdmi {\n-\tp0 {\n+\thdmi-i2c-disable-hog {\n \t\t/*\n \t\t * PM_OEn to High: Disable routing I2C3 to PM_I2C\n \t\t * With this PM_SEL(p3) should not matter\ndiff --git a/arch/arm/dts/dra72-evm-common.dtsi b/arch/arm/dts/dra72-evm-common.dtsi\nindex 84c7f2c726b..aa7a1c6744c 100644\n--- a/arch/arm/dts/dra72-evm-common.dtsi\n+++ b/arch/arm/dts/dra72-evm-common.dtsi\n@@ -269,7 +269,7 @@\n \t\t */\n \t\tlines-initial-states = <0x0f2b>;\n \n-\t\tp1 {\n+\t\thdmi-audio-hog {\n \t\t\t/* vin6_sel_s0: high: VIN6, low: audio */\n \t\t\tgpio-hog;\n \t\t\tgpios = <1 GPIO_ACTIVE_HIGH>;\n@@ -340,7 +340,7 @@\n \t\t#size-cells = <1>;\n \t\tpartition@0 {\n \t\t\tlabel = \"NAND.SPL\";\n-\t\t\treg = <0x00000000 0x000020000>;\n+\t\t\treg = <0x00000000 0x00020000>;\n \t\t};\n \t\tpartition@1 {\n \t\t\tlabel = \"NAND.SPL.backup1\";\n@@ -438,7 +438,7 @@\n \tstatus = \"okay\";\n \n \tspi-max-frequency = <76800000>;\n-\tm25p80@0 {\n+\tflash@0 {\n \t\tcompatible = \"s25fl256s1\";\n \t\tspi-max-frequency = <76800000>;\n \t\treg = <0>;\n@@ -454,7 +454,7 @@\n \t\t */\n \t\tpartition@0 {\n \t\t\tlabel = \"QSPI.SPL\";\n-\t\t\treg = <0x00000000 0x000010000>;\n+\t\t\treg = <0x00000000 0x00010000>;\n \t\t};\n \t\tpartition@1 {\n \t\t\tlabel = \"QSPI.SPL.backup1\";\n@@ -546,17 +546,17 @@\n \n &mailbox5 {\n \tstatus = \"okay\";\n-\tmbox_ipu1_ipc3x: mbox_ipu1_ipc3x {\n+\tmbox_ipu1_ipc3x: mbox-ipu1-ipc3x {\n \t\tstatus = \"okay\";\n \t};\n-\tmbox_dsp1_ipc3x: mbox_dsp1_ipc3x {\n+\tmbox_dsp1_ipc3x: mbox-dsp1-ipc3x {\n \t\tstatus = \"okay\";\n \t};\n };\n \n &mailbox6 {\n \tstatus = \"okay\";\n-\tmbox_ipu2_ipc3x: mbox_ipu2_ipc3x {\n+\tmbox_ipu2_ipc3x: mbox-ipu2-ipc3x {\n \t\tstatus = \"okay\";\n \t};\n };\ndiff --git a/arch/arm/dts/dra72-evm-tps65917.dtsi b/arch/arm/dts/dra72-evm-tps65917.dtsi\nindex 2221a42697c..c7b4768dfd9 100644\n--- a/arch/arm/dts/dra72-evm-tps65917.dtsi\n+++ b/arch/arm/dts/dra72-evm-tps65917.dtsi\n@@ -5,7 +5,7 @@\n \n /*\n  * Integrated Power Management Chip\n- * http://www.ti.com/lit/ds/symlink/tps65917-q1.pdf\n+ * https://www.ti.com/lit/ds/symlink/tps65917-q1.pdf\n  */\n \n &tps65917 {\ndiff --git a/arch/arm/dts/dra72x.dtsi b/arch/arm/dts/dra72x.dtsi\nindex d5c5460227f..481189d361b 100644\n--- a/arch/arm/dts/dra72x.dtsi\n+++ b/arch/arm/dts/dra72x.dtsi\n@@ -29,12 +29,12 @@\n };\n \n &mailbox5 {\n-\tmbox_ipu1_ipc3x: mbox_ipu1_ipc3x {\n+\tmbox_ipu1_ipc3x: mbox-ipu1-ipc3x {\n \t\tti,mbox-tx = <6 2 2>;\n \t\tti,mbox-rx = <4 2 2>;\n \t\tstatus = \"disabled\";\n \t};\n-\tmbox_dsp1_ipc3x: mbox_dsp1_ipc3x {\n+\tmbox_dsp1_ipc3x: mbox-dsp1-ipc3x {\n \t\tti,mbox-tx = <5 2 2>;\n \t\tti,mbox-rx = <1 2 2>;\n \t\tstatus = \"disabled\";\n@@ -42,7 +42,7 @@\n };\n \n &mailbox6 {\n-\tmbox_ipu2_ipc3x: mbox_ipu2_ipc3x {\n+\tmbox_ipu2_ipc3x: mbox-ipu2-ipc3x {\n \t\tti,mbox-tx = <6 2 2>;\n \t\tti,mbox-rx = <4 2 2>;\n \t\tstatus = \"disabled\";\ndiff --git a/arch/arm/dts/dra74x.dtsi b/arch/arm/dts/dra74x.dtsi\nindex ed517e1532b..9ade216cd45 100644\n--- a/arch/arm/dts/dra74x.dtsi\n+++ b/arch/arm/dts/dra74x.dtsi\n@@ -98,12 +98,12 @@\n };\n \n &mailbox5 {\n-\tmbox_ipu1_ipc3x: mbox_ipu1_ipc3x {\n+\tmbox_ipu1_ipc3x: mbox-ipu1-ipc3x {\n \t\tti,mbox-tx = <6 2 2>;\n \t\tti,mbox-rx = <4 2 2>;\n \t\tstatus = \"disabled\";\n \t};\n-\tmbox_dsp1_ipc3x: mbox_dsp1_ipc3x {\n+\tmbox_dsp1_ipc3x: mbox-dsp1-ipc3x {\n \t\tti,mbox-tx = <5 2 2>;\n \t\tti,mbox-rx = <1 2 2>;\n \t\tstatus = \"disabled\";\n@@ -111,12 +111,12 @@\n };\n \n &mailbox6 {\n-\tmbox_ipu2_ipc3x: mbox_ipu2_ipc3x {\n+\tmbox_ipu2_ipc3x: mbox-ipu2-ipc3x {\n \t\tti,mbox-tx = <6 2 2>;\n \t\tti,mbox-rx = <4 2 2>;\n \t\tstatus = \"disabled\";\n \t};\n-\tmbox_dsp2_ipc3x: mbox_dsp2_ipc3x {\n+\tmbox_dsp2_ipc3x: mbox-dsp2-ipc3x {\n \t\tti,mbox-tx = <5 2 2>;\n \t\tti,mbox-rx = <1 2 2>;\n \t\tstatus = \"disabled\";\ndiff --git a/arch/arm/dts/dra76-evm.dts b/arch/arm/dts/dra76-evm.dts\nindex 288f492cef6..c131e7f7f06 100644\n--- a/arch/arm/dts/dra76-evm.dts\n+++ b/arch/arm/dts/dra76-evm.dts\n@@ -271,7 +271,7 @@\n \t\treg = <0x26>;\n \t\tgpio-controller;\n \t\t#gpio-cells = <2>;\n-\t\tp1 {\n+\t\thdmi-audio-hog {\n \t\t\t/* vin6_sel_s0: high: VIN6, low: audio */\n \t\t\tgpio-hog;\n \t\t\tgpios = <1 GPIO_ACTIVE_HIGH>;\n@@ -379,7 +379,7 @@\n \n &qspi {\n \tspi-max-frequency = <96000000>;\n-\tm25p80@0 {\n+\tflash@0 {\n \t\tspi-max-frequency = <96000000>;\n \t};\n };\ndiff --git a/arch/arm/dts/dra7xx-clocks.dtsi b/arch/arm/dts/dra7xx-clocks.dtsi\nindex 1e53a2c90e6..b0cfe553afe 100644\n--- a/arch/arm/dts/dra7xx-clocks.dtsi\n+++ b/arch/arm/dts/dra7xx-clocks.dtsi\n@@ -5,103 +5,103 @@\n  * Copyright (C) 2013 Texas Instruments, Inc.\n  */\n &cm_core_aon_clocks {\n-\tatl_clkin0_ck: atl_clkin0_ck {\n+\tatl_clkin0_ck: clock-atl-clkin0 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,dra7-atl-clock\";\n \t\tclocks = <&atl_gfclk_mux>;\n \t};\n \n-\tatl_clkin1_ck: atl_clkin1_ck {\n+\tatl_clkin1_ck: clock-atl-clkin1 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,dra7-atl-clock\";\n \t\tclocks = <&atl_gfclk_mux>;\n \t};\n \n-\tatl_clkin2_ck: atl_clkin2_ck {\n+\tatl_clkin2_ck: clock-atl-clkin2 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,dra7-atl-clock\";\n \t\tclocks = <&atl_gfclk_mux>;\n \t};\n \n-\tatl_clkin3_ck: atl_clkin3_ck {\n+\tatl_clkin3_ck: clock-atl-clkin3 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,dra7-atl-clock\";\n \t\tclocks = <&atl_gfclk_mux>;\n \t};\n \n-\thdmi_clkin_ck: hdmi_clkin_ck {\n+\thdmi_clkin_ck: clock-hdmi-clkin {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-clock\";\n \t\tclock-frequency = <0>;\n \t};\n \n-\tmlb_clkin_ck: mlb_clkin_ck {\n+\tmlb_clkin_ck: clock-mlb-clkin {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-clock\";\n \t\tclock-frequency = <0>;\n \t};\n \n-\tmlbp_clkin_ck: mlbp_clkin_ck {\n+\tmlbp_clkin_ck: clock-mlbp-clkin {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-clock\";\n \t\tclock-frequency = <0>;\n \t};\n \n-\tpciesref_acs_clk_ck: pciesref_acs_clk_ck {\n+\tpciesref_acs_clk_ck: clock-pciesref-acs {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-clock\";\n \t\tclock-frequency = <100000000>;\n \t};\n \n-\tref_clkin0_ck: ref_clkin0_ck {\n+\tref_clkin0_ck: clock-ref-clkin0 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-clock\";\n \t\tclock-frequency = <0>;\n \t};\n \n-\tref_clkin1_ck: ref_clkin1_ck {\n+\tref_clkin1_ck: clock-ref-clkin1 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-clock\";\n \t\tclock-frequency = <0>;\n \t};\n \n-\tref_clkin2_ck: ref_clkin2_ck {\n+\tref_clkin2_ck: clock-ref-clkin2 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-clock\";\n \t\tclock-frequency = <0>;\n \t};\n \n-\tref_clkin3_ck: ref_clkin3_ck {\n+\tref_clkin3_ck: clock-ref-clkin3 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-clock\";\n \t\tclock-frequency = <0>;\n \t};\n \n-\trmii_clk_ck: rmii_clk_ck {\n+\trmii_clk_ck: clock-rmii {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-clock\";\n \t\tclock-frequency = <0>;\n \t};\n \n-\tsdvenc_clkin_ck: sdvenc_clkin_ck {\n+\tsdvenc_clkin_ck: clock-sdvenc-clkin {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-clock\";\n \t\tclock-frequency = <0>;\n \t};\n \n-\tsecure_32k_clk_src_ck: secure_32k_clk_src_ck {\n+\tsecure_32k_clk_src_ck: clock-secure-32k-clk-src {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-clock\";\n \t\tclock-frequency = <32768>;\n \t};\n \n-\tsys_clk32_crystal_ck: sys_clk32_crystal_ck {\n+\tsys_clk32_crystal_ck: clock-sys-clk32-crystal {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-clock\";\n \t\tclock-frequency = <32768>;\n \t};\n \n-\tsys_clk32_pseudo_ck: sys_clk32_pseudo_ck {\n+\tsys_clk32_pseudo_ck: clock-sys-clk32-pseudo {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&sys_clkin1>;\n@@ -109,104 +109,104 @@\n \t\tclock-div = <610>;\n \t};\n \n-\tvirt_12000000_ck: virt_12000000_ck {\n+\tvirt_12000000_ck: clock-virt-12000000 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-clock\";\n \t\tclock-frequency = <12000000>;\n \t};\n \n-\tvirt_13000000_ck: virt_13000000_ck {\n+\tvirt_13000000_ck: clock-virt-13000000 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-clock\";\n \t\tclock-frequency = <13000000>;\n \t};\n \n-\tvirt_16800000_ck: virt_16800000_ck {\n+\tvirt_16800000_ck: clock-virt-16800000 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-clock\";\n \t\tclock-frequency = <16800000>;\n \t};\n \n-\tvirt_19200000_ck: virt_19200000_ck {\n+\tvirt_19200000_ck: clock-virt-19200000 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-clock\";\n \t\tclock-frequency = <19200000>;\n \t};\n \n-\tvirt_20000000_ck: virt_20000000_ck {\n+\tvirt_20000000_ck: clock-virt-20000000 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-clock\";\n \t\tclock-frequency = <20000000>;\n \t};\n \n-\tvirt_26000000_ck: virt_26000000_ck {\n+\tvirt_26000000_ck: clock-virt-26000000 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-clock\";\n \t\tclock-frequency = <26000000>;\n \t};\n \n-\tvirt_27000000_ck: virt_27000000_ck {\n+\tvirt_27000000_ck: clock-virt-27000000 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-clock\";\n \t\tclock-frequency = <27000000>;\n \t};\n \n-\tvirt_38400000_ck: virt_38400000_ck {\n+\tvirt_38400000_ck: clock-virt-38400000 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-clock\";\n \t\tclock-frequency = <38400000>;\n \t};\n \n-\tsys_clkin2: sys_clkin2 {\n+\tsys_clkin2: clock-sys-clkin2 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-clock\";\n \t\tclock-frequency = <22579200>;\n \t};\n \n-\tusb_otg_clkin_ck: usb_otg_clkin_ck {\n+\tusb_otg_clkin_ck: clock-usb-otg-clkin {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-clock\";\n \t\tclock-frequency = <0>;\n \t};\n \n-\tvideo1_clkin_ck: video1_clkin_ck {\n+\tvideo1_clkin_ck: clock-video1-clkin {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-clock\";\n \t\tclock-frequency = <0>;\n \t};\n \n-\tvideo1_m2_clkin_ck: video1_m2_clkin_ck {\n+\tvideo1_m2_clkin_ck: clock-video1-m2-clkin {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-clock\";\n \t\tclock-frequency = <0>;\n \t};\n \n-\tvideo2_clkin_ck: video2_clkin_ck {\n+\tvideo2_clkin_ck: clock-video2-clkin {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-clock\";\n \t\tclock-frequency = <0>;\n \t};\n \n-\tvideo2_m2_clkin_ck: video2_m2_clkin_ck {\n+\tvideo2_m2_clkin_ck: clock-video2-m2-clkin {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-clock\";\n \t\tclock-frequency = <0>;\n \t};\n \n-\tdpll_abe_ck: dpll_abe_ck@1e0 {\n+\tdpll_abe_ck: clock@1e0 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,omap4-dpll-m4xen-clock\";\n \t\tclocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;\n \t\treg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;\n \t};\n \n-\tdpll_abe_x2_ck: dpll_abe_x2_ck {\n+\tdpll_abe_x2_ck: clock-dpll-abe-x2 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,omap4-dpll-x2-clock\";\n \t\tclocks = <&dpll_abe_ck>;\n \t};\n \n-\tdpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {\n+\tdpll_abe_m2x2_ck: clock-dpll-abe-m2x2-8@1f0 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_abe_x2_ck>;\n@@ -217,7 +217,7 @@\n \t\tti,invert-autoidle-bit;\n \t};\n \n-\tabe_clk: abe_clk@108 {\n+\tabe_clk: clock-abe@108 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_abe_m2x2_ck>;\n@@ -226,7 +226,7 @@\n \t\tti,index-power-of-two;\n \t};\n \n-\tdpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {\n+\tdpll_abe_m2_ck: clock-dpll-abe-m2-8@1f0 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_abe_ck>;\n@@ -237,7 +237,7 @@\n \t\tti,invert-autoidle-bit;\n \t};\n \n-\tdpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {\n+\tdpll_abe_m3x2_ck: clock-dpll-abe-m3x2-8@1f4 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_abe_x2_ck>;\n@@ -248,7 +248,7 @@\n \t\tti,invert-autoidle-bit;\n \t};\n \n-\tdpll_core_byp_mux: dpll_core_byp_mux@12c {\n+\tdpll_core_byp_mux: clock-dpll-core-byp-mux-23@12c {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,mux-clock\";\n \t\tclocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;\n@@ -256,20 +256,20 @@\n \t\treg = <0x012c>;\n \t};\n \n-\tdpll_core_ck: dpll_core_ck@120 {\n+\tdpll_core_ck: clock@120 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,omap4-dpll-core-clock\";\n \t\tclocks = <&sys_clkin1>, <&dpll_core_byp_mux>;\n \t\treg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;\n \t};\n \n-\tdpll_core_x2_ck: dpll_core_x2_ck {\n+\tdpll_core_x2_ck: clock-dpll-core-x2 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,omap4-dpll-x2-clock\";\n \t\tclocks = <&dpll_core_ck>;\n \t};\n \n-\tdpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {\n+\tdpll_core_h12x2_ck: clock-dpll-core-h12x2-8@13c {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_core_x2_ck>;\n@@ -280,7 +280,7 @@\n \t\tti,invert-autoidle-bit;\n \t};\n \n-\tmpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {\n+\tmpu_dpll_hs_clk_div: clock-mpu-dpll-hs-clk-div {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&dpll_core_h12x2_ck>;\n@@ -288,14 +288,14 @@\n \t\tclock-div = <1>;\n \t};\n \n-\tdpll_mpu_ck: dpll_mpu_ck@160 {\n+\tdpll_mpu_ck: clock@160 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,omap5-mpu-dpll-clock\";\n \t\tclocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;\n \t\treg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;\n \t};\n \n-\tdpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {\n+\tdpll_mpu_m2_ck: clock-dpll-mpu-m2-8@170 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_mpu_ck>;\n@@ -306,7 +306,7 @@\n \t\tti,invert-autoidle-bit;\n \t};\n \n-\tmpu_dclk_div: mpu_dclk_div {\n+\tmpu_dclk_div: clock-mpu-dclk-div {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&dpll_mpu_m2_ck>;\n@@ -314,7 +314,7 @@\n \t\tclock-div = <1>;\n \t};\n \n-\tdsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {\n+\tdsp_dpll_hs_clk_div: clock-dsp-dpll-hs-clk-div {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&dpll_core_h12x2_ck>;\n@@ -322,7 +322,7 @@\n \t\tclock-div = <1>;\n \t};\n \n-\tdpll_dsp_byp_mux: dpll_dsp_byp_mux@240 {\n+\tdpll_dsp_byp_mux: clock-dpll-dsp-byp-mux-23@240 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,mux-clock\";\n \t\tclocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;\n@@ -330,7 +330,7 @@\n \t\treg = <0x0240>;\n \t};\n \n-\tdpll_dsp_ck: dpll_dsp_ck@234 {\n+\tdpll_dsp_ck: clock@234 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,omap4-dpll-clock\";\n \t\tclocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;\n@@ -339,7 +339,7 @@\n \t\tassigned-clock-rates = <600000000>;\n \t};\n \n-\tdpll_dsp_m2_ck: dpll_dsp_m2_ck@244 {\n+\tdpll_dsp_m2_ck: clock-dpll-dsp-m2-8@244 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_dsp_ck>;\n@@ -352,7 +352,7 @@\n \t\tassigned-clock-rates = <600000000>;\n \t};\n \n-\tiva_dpll_hs_clk_div: iva_dpll_hs_clk_div {\n+\tiva_dpll_hs_clk_div: clock-iva-dpll-hs-clk-div {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&dpll_core_h12x2_ck>;\n@@ -360,7 +360,7 @@\n \t\tclock-div = <1>;\n \t};\n \n-\tdpll_iva_byp_mux: dpll_iva_byp_mux@1ac {\n+\tdpll_iva_byp_mux: clock-dpll-iva-byp-mux-23@1ac {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,mux-clock\";\n \t\tclocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;\n@@ -368,7 +368,7 @@\n \t\treg = <0x01ac>;\n \t};\n \n-\tdpll_iva_ck: dpll_iva_ck@1a0 {\n+\tdpll_iva_ck: clock@1a0 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,omap4-dpll-clock\";\n \t\tclocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;\n@@ -377,7 +377,7 @@\n \t\tassigned-clock-rates = <1165000000>;\n \t};\n \n-\tdpll_iva_m2_ck: dpll_iva_m2_ck@1b0 {\n+\tdpll_iva_m2_ck: clock-dpll-iva-m2-8@1b0 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_iva_ck>;\n@@ -390,7 +390,7 @@\n \t\tassigned-clock-rates = <388333334>;\n \t};\n \n-\tiva_dclk: iva_dclk {\n+\tiva_dclk: clock-iva-dclk {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&dpll_iva_m2_ck>;\n@@ -398,7 +398,7 @@\n \t\tclock-div = <1>;\n \t};\n \n-\tdpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 {\n+\tdpll_gpu_byp_mux: clock-dpll-gpu-byp-mux-23@2e4 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,mux-clock\";\n \t\tclocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;\n@@ -406,7 +406,7 @@\n \t\treg = <0x02e4>;\n \t};\n \n-\tdpll_gpu_ck: dpll_gpu_ck@2d8 {\n+\tdpll_gpu_ck: clock@2d8 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,omap4-dpll-clock\";\n \t\tclocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;\n@@ -415,7 +415,7 @@\n \t\tassigned-clock-rates = <1277000000>;\n \t};\n \n-\tdpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 {\n+\tdpll_gpu_m2_ck: clock-dpll-gpu-m2-8@2e8 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_gpu_ck>;\n@@ -428,7 +428,7 @@\n \t\tassigned-clock-rates = <425666667>;\n \t};\n \n-\tdpll_core_m2_ck: dpll_core_m2_ck@130 {\n+\tdpll_core_m2_ck: clock-dpll-core-m2-8@130 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_core_ck>;\n@@ -439,7 +439,7 @@\n \t\tti,invert-autoidle-bit;\n \t};\n \n-\tcore_dpll_out_dclk_div: core_dpll_out_dclk_div {\n+\tcore_dpll_out_dclk_div: clock-core-dpll-out-dclk-div {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&dpll_core_m2_ck>;\n@@ -447,7 +447,7 @@\n \t\tclock-div = <1>;\n \t};\n \n-\tdpll_ddr_byp_mux: dpll_ddr_byp_mux@21c {\n+\tdpll_ddr_byp_mux: clock-dpll-ddr-byp-mux-23@21c {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,mux-clock\";\n \t\tclocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;\n@@ -455,14 +455,14 @@\n \t\treg = <0x021c>;\n \t};\n \n-\tdpll_ddr_ck: dpll_ddr_ck@210 {\n+\tdpll_ddr_ck: clock@210 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,omap4-dpll-clock\";\n \t\tclocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;\n \t\treg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;\n \t};\n \n-\tdpll_ddr_m2_ck: dpll_ddr_m2_ck@220 {\n+\tdpll_ddr_m2_ck: clock-dpll-ddr-m2-8@220 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_ddr_ck>;\n@@ -473,7 +473,7 @@\n \t\tti,invert-autoidle-bit;\n \t};\n \n-\tdpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 {\n+\tdpll_gmac_byp_mux: clock-dpll-gmac-byp-mux-23@2b4 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,mux-clock\";\n \t\tclocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;\n@@ -481,14 +481,14 @@\n \t\treg = <0x02b4>;\n \t};\n \n-\tdpll_gmac_ck: dpll_gmac_ck@2a8 {\n+\tdpll_gmac_ck: clock@2a8 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,omap4-dpll-clock\";\n \t\tclocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;\n \t\treg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;\n \t};\n \n-\tdpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 {\n+\tdpll_gmac_m2_ck: clock-dpll-gmac-m2-8@2b8 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_gmac_ck>;\n@@ -499,7 +499,7 @@\n \t\tti,invert-autoidle-bit;\n \t};\n \n-\tvideo2_dclk_div: video2_dclk_div {\n+\tvideo2_dclk_div: clock-video2-dclk-div {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&video2_m2_clkin_ck>;\n@@ -507,7 +507,7 @@\n \t\tclock-div = <1>;\n \t};\n \n-\tvideo1_dclk_div: video1_dclk_div {\n+\tvideo1_dclk_div: clock-video1-dclk-div {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&video1_m2_clkin_ck>;\n@@ -515,7 +515,7 @@\n \t\tclock-div = <1>;\n \t};\n \n-\thdmi_dclk_div: hdmi_dclk_div {\n+\thdmi_dclk_div: clock-hdmi-dclk-div {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&hdmi_clkin_ck>;\n@@ -523,7 +523,7 @@\n \t\tclock-div = <1>;\n \t};\n \n-\tper_dpll_hs_clk_div: per_dpll_hs_clk_div {\n+\tper_dpll_hs_clk_div: clock-per-dpll-hs-clk-div {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&dpll_abe_m3x2_ck>;\n@@ -531,7 +531,7 @@\n \t\tclock-div = <2>;\n \t};\n \n-\tusb_dpll_hs_clk_div: usb_dpll_hs_clk_div {\n+\tusb_dpll_hs_clk_div: clock-usb-dpll-hs-clk-div {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&dpll_abe_m3x2_ck>;\n@@ -539,7 +539,7 @@\n \t\tclock-div = <3>;\n \t};\n \n-\teve_dpll_hs_clk_div: eve_dpll_hs_clk_div {\n+\teve_dpll_hs_clk_div: clock-eve-dpll-hs-clk-div {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&dpll_core_h12x2_ck>;\n@@ -547,7 +547,7 @@\n \t\tclock-div = <1>;\n \t};\n \n-\tdpll_eve_byp_mux: dpll_eve_byp_mux@290 {\n+\tdpll_eve_byp_mux: clock-dpll-eve-byp-mux-23@290 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,mux-clock\";\n \t\tclocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;\n@@ -555,14 +555,14 @@\n \t\treg = <0x0290>;\n \t};\n \n-\tdpll_eve_ck: dpll_eve_ck@284 {\n+\tdpll_eve_ck: clock@284 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,omap4-dpll-clock\";\n \t\tclocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;\n \t\treg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;\n \t};\n \n-\tdpll_eve_m2_ck: dpll_eve_m2_ck@294 {\n+\tdpll_eve_m2_ck: clock-dpll-eve-m2-8@294 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_eve_ck>;\n@@ -573,7 +573,7 @@\n \t\tti,invert-autoidle-bit;\n \t};\n \n-\teve_dclk_div: eve_dclk_div {\n+\teve_dclk_div: clock-eve-dclk-div {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&dpll_eve_m2_ck>;\n@@ -581,7 +581,7 @@\n \t\tclock-div = <1>;\n \t};\n \n-\tdpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {\n+\tdpll_core_h13x2_ck: clock-dpll-core-h13x2-8@140 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_core_x2_ck>;\n@@ -592,7 +592,7 @@\n \t\tti,invert-autoidle-bit;\n \t};\n \n-\tdpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {\n+\tdpll_core_h14x2_ck: clock-dpll-core-h14x2-8@144 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_core_x2_ck>;\n@@ -603,7 +603,7 @@\n \t\tti,invert-autoidle-bit;\n \t};\n \n-\tdpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {\n+\tdpll_core_h22x2_ck: clock-dpll-core-h22x2-8@154 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_core_x2_ck>;\n@@ -614,7 +614,7 @@\n \t\tti,invert-autoidle-bit;\n \t};\n \n-\tdpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {\n+\tdpll_core_h23x2_ck: clock-dpll-core-h23x2-8@158 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_core_x2_ck>;\n@@ -625,7 +625,7 @@\n \t\tti,invert-autoidle-bit;\n \t};\n \n-\tdpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {\n+\tdpll_core_h24x2_ck: clock-dpll-core-h24x2-8@15c {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_core_x2_ck>;\n@@ -636,13 +636,13 @@\n \t\tti,invert-autoidle-bit;\n \t};\n \n-\tdpll_ddr_x2_ck: dpll_ddr_x2_ck {\n+\tdpll_ddr_x2_ck: clock-dpll-ddr-x2 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,omap4-dpll-x2-clock\";\n \t\tclocks = <&dpll_ddr_ck>;\n \t};\n \n-\tdpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 {\n+\tdpll_ddr_h11x2_ck: clock-dpll-ddr-h11x2-8@228 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_ddr_x2_ck>;\n@@ -653,13 +653,13 @@\n \t\tti,invert-autoidle-bit;\n \t};\n \n-\tdpll_dsp_x2_ck: dpll_dsp_x2_ck {\n+\tdpll_dsp_x2_ck: clock-dpll-dsp-x2 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,omap4-dpll-x2-clock\";\n \t\tclocks = <&dpll_dsp_ck>;\n \t};\n \n-\tdpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 {\n+\tdpll_dsp_m3x2_ck: clock-dpll-dsp-m3x2-8@248 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_dsp_x2_ck>;\n@@ -672,13 +672,13 @@\n \t\tassigned-clock-rates = <400000000>;\n \t};\n \n-\tdpll_gmac_x2_ck: dpll_gmac_x2_ck {\n+\tdpll_gmac_x2_ck: clock-dpll-gmac-x2 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,omap4-dpll-x2-clock\";\n \t\tclocks = <&dpll_gmac_ck>;\n \t};\n \n-\tdpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 {\n+\tdpll_gmac_h11x2_ck: clock-dpll-gmac-h11x2-8@2c0 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_gmac_x2_ck>;\n@@ -689,7 +689,7 @@\n \t\tti,invert-autoidle-bit;\n \t};\n \n-\tdpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 {\n+\tdpll_gmac_h12x2_ck: clock-dpll-gmac-h12x2-8@2c4 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_gmac_x2_ck>;\n@@ -700,7 +700,7 @@\n \t\tti,invert-autoidle-bit;\n \t};\n \n-\tdpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 {\n+\tdpll_gmac_h13x2_ck: clock-dpll-gmac-h13x2-8@2c8 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_gmac_x2_ck>;\n@@ -711,7 +711,7 @@\n \t\tti,invert-autoidle-bit;\n \t};\n \n-\tdpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc {\n+\tdpll_gmac_m3x2_ck: clock-dpll-gmac-m3x2-8@2bc {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_gmac_x2_ck>;\n@@ -722,7 +722,7 @@\n \t\tti,invert-autoidle-bit;\n \t};\n \n-\tgmii_m_clk_div: gmii_m_clk_div {\n+\tgmii_m_clk_div: clock-gmii-m-clk-div {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&dpll_gmac_h11x2_ck>;\n@@ -730,7 +730,7 @@\n \t\tclock-div = <2>;\n \t};\n \n-\thdmi_clk2_div: hdmi_clk2_div {\n+\thdmi_clk2_div: clock-hdmi-clk2-div {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&hdmi_clkin_ck>;\n@@ -738,7 +738,7 @@\n \t\tclock-div = <1>;\n \t};\n \n-\thdmi_div_clk: hdmi_div_clk {\n+\thdmi_div_clk: clock-hdmi-div {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&hdmi_clkin_ck>;\n@@ -746,7 +746,7 @@\n \t\tclock-div = <1>;\n \t};\n \n-\tl3_iclk_div: l3_iclk_div@100 {\n+\tl3_iclk_div: clock-l3-iclk-div-4@100 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tti,max-div = <2>;\n@@ -756,7 +756,7 @@\n \t\tti,index-power-of-two;\n \t};\n \n-\tl4_root_clk_div: l4_root_clk_div {\n+\tl4_root_clk_div: clock-l4-root-clk-div {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&l3_iclk_div>;\n@@ -764,7 +764,7 @@\n \t\tclock-div = <2>;\n \t};\n \n-\tvideo1_clk2_div: video1_clk2_div {\n+\tvideo1_clk2_div: clock-video1-clk2-div {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&video1_clkin_ck>;\n@@ -772,7 +772,7 @@\n \t\tclock-div = <1>;\n \t};\n \n-\tvideo1_div_clk: video1_div_clk {\n+\tvideo1_div_clk: clock-video1-div {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&video1_clkin_ck>;\n@@ -780,7 +780,7 @@\n \t\tclock-div = <1>;\n \t};\n \n-\tvideo2_clk2_div: video2_clk2_div {\n+\tvideo2_clk2_div: clock-video2-clk2-div {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&video2_clkin_ck>;\n@@ -788,7 +788,7 @@\n \t\tclock-div = <1>;\n \t};\n \n-\tvideo2_div_clk: video2_div_clk {\n+\tvideo2_div_clk: clock-video2-div {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&video2_clkin_ck>;\n@@ -870,14 +870,14 @@\n \t\treg = <0x0580>;\n \t};\n \n-\tdummy_ck: dummy_ck {\n+\tdummy_ck: clock-dummy {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-clock\";\n \t\tclock-frequency = <0>;\n \t};\n };\n &prm_clocks {\n-\tsys_clkin1: sys_clkin1@110 {\n+\tsys_clkin1: clock-sys-clkin1@110 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,mux-clock\";\n \t\tclocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;\n@@ -885,28 +885,28 @@\n \t\tti,index-starts-at-one;\n \t};\n \n-\tabe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 {\n+\tabe_dpll_sys_clk_mux: clock-abe-dpll-sys-clk-mux@118 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,mux-clock\";\n \t\tclocks = <&sys_clkin1>, <&sys_clkin2>;\n \t\treg = <0x0118>;\n \t};\n \n-\tabe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 {\n+\tabe_dpll_bypass_clk_mux: clock-abe-dpll-bypass-clk-mux@114 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,mux-clock\";\n \t\tclocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;\n \t\treg = <0x0114>;\n \t};\n \n-\tabe_dpll_clk_mux: abe_dpll_clk_mux@10c {\n+\tabe_dpll_clk_mux: clock-abe-dpll-clk-mux@10c {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,mux-clock\";\n \t\tclocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;\n \t\treg = <0x010c>;\n \t};\n \n-\tabe_24m_fclk: abe_24m_fclk@11c {\n+\tabe_24m_fclk: clock-abe-24m@11c {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_abe_m2x2_ck>;\n@@ -914,7 +914,7 @@\n \t\tti,dividers = <8>, <16>;\n \t};\n \n-\taess_fclk: aess_fclk@178 {\n+\taess_fclk: clock-aess@178 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&abe_clk>;\n@@ -922,7 +922,7 @@\n \t\tti,max-div = <2>;\n \t};\n \n-\tabe_giclk_div: abe_giclk_div@174 {\n+\tabe_giclk_div: clock-abe-giclk-div@174 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&aess_fclk>;\n@@ -930,7 +930,7 @@\n \t\tti,max-div = <2>;\n \t};\n \n-\tabe_lp_clk_div: abe_lp_clk_div@1d8 {\n+\tabe_lp_clk_div: clock-abe-lp-clk-div@1d8 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_abe_m2x2_ck>;\n@@ -938,7 +938,7 @@\n \t\tti,dividers = <16>, <32>;\n \t};\n \n-\tabe_sys_clk_div: abe_sys_clk_div@120 {\n+\tabe_sys_clk_div: clock-abe-sys-clk-div@120 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&sys_clkin1>;\n@@ -946,14 +946,14 @@\n \t\tti,max-div = <2>;\n \t};\n \n-\tadc_gfclk_mux: adc_gfclk_mux@1dc {\n+\tadc_gfclk_mux: clock-adc-gfclk-mux@1dc {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,mux-clock\";\n \t\tclocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;\n \t\treg = <0x01dc>;\n \t};\n \n-\tsys_clk1_dclk_div: sys_clk1_dclk_div@1c8 {\n+\tsys_clk1_dclk_div: clock-sys-clk1-dclk-div@1c8 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&sys_clkin1>;\n@@ -962,7 +962,7 @@\n \t\tti,index-power-of-two;\n \t};\n \n-\tsys_clk2_dclk_div: sys_clk2_dclk_div@1cc {\n+\tsys_clk2_dclk_div: clock-sys-clk2-dclk-div@1cc {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&sys_clkin2>;\n@@ -971,7 +971,7 @@\n \t\tti,index-power-of-two;\n \t};\n \n-\tper_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc {\n+\tper_abe_x1_dclk_div: clock-per-abe-x1-dclk-div@1bc {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_abe_m2_ck>;\n@@ -980,7 +980,7 @@\n \t\tti,index-power-of-two;\n \t};\n \n-\tdsp_gclk_div: dsp_gclk_div@18c {\n+\tdsp_gclk_div: clock-dsp-gclk-div@18c {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_dsp_m2_ck>;\n@@ -989,7 +989,7 @@\n \t\tti,index-power-of-two;\n \t};\n \n-\tgpu_dclk: gpu_dclk@1a0 {\n+\tgpu_dclk: clock-gpu-dclk@1a0 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_gpu_m2_ck>;\n@@ -998,7 +998,7 @@\n \t\tti,index-power-of-two;\n \t};\n \n-\temif_phy_dclk_div: emif_phy_dclk_div@190 {\n+\temif_phy_dclk_div: clock-emif-phy-dclk-div@190 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_ddr_m2_ck>;\n@@ -1007,7 +1007,7 @@\n \t\tti,index-power-of-two;\n \t};\n \n-\tgmac_250m_dclk_div: gmac_250m_dclk_div@19c {\n+\tgmac_250m_dclk_div: clock-gmac-250m-dclk-div@19c {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_gmac_m2_ck>;\n@@ -1016,7 +1016,7 @@\n \t\tti,index-power-of-two;\n \t};\n \n-\tgmac_main_clk: gmac_main_clk {\n+\tgmac_main_clk: clock-gmac-main {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&gmac_250m_dclk_div>;\n@@ -1024,7 +1024,7 @@\n \t\tclock-div = <2>;\n \t};\n \n-\tl3init_480m_dclk_div: l3init_480m_dclk_div@1ac {\n+\tl3init_480m_dclk_div: clock-l3init-480m-dclk-div@1ac {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_usb_m2_ck>;\n@@ -1033,7 +1033,7 @@\n \t\tti,index-power-of-two;\n \t};\n \n-\tusb_otg_dclk_div: usb_otg_dclk_div@184 {\n+\tusb_otg_dclk_div: clock-usb-otg-dclk-div@184 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&usb_otg_clkin_ck>;\n@@ -1042,7 +1042,7 @@\n \t\tti,index-power-of-two;\n \t};\n \n-\tsata_dclk_div: sata_dclk_div@1c0 {\n+\tsata_dclk_div: clock-sata-dclk-div@1c0 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&sys_clkin1>;\n@@ -1051,7 +1051,7 @@\n \t\tti,index-power-of-two;\n \t};\n \n-\tpcie2_dclk_div: pcie2_dclk_div@1b8 {\n+\tpcie2_dclk_div: clock-pcie2-dclk-div@1b8 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_pcie_ref_m2_ck>;\n@@ -1060,7 +1060,7 @@\n \t\tti,index-power-of-two;\n \t};\n \n-\tpcie_dclk_div: pcie_dclk_div@1b4 {\n+\tpcie_dclk_div: clock-pcie-dclk-div@1b4 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&apll_pcie_m2_ck>;\n@@ -1069,7 +1069,7 @@\n \t\tti,index-power-of-two;\n \t};\n \n-\temu_dclk_div: emu_dclk_div@194 {\n+\temu_dclk_div: clock-emu-dclk-div@194 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&sys_clkin1>;\n@@ -1078,7 +1078,7 @@\n \t\tti,index-power-of-two;\n \t};\n \n-\tsecure_32k_dclk_div: secure_32k_dclk_div@1c4 {\n+\tsecure_32k_dclk_div: clock-secure-32k-dclk-div@1c4 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&secure_32k_clk_src_ck>;\n@@ -1087,28 +1087,28 @@\n \t\tti,index-power-of-two;\n \t};\n \n-\tclkoutmux0_clk_mux: clkoutmux0_clk_mux@158 {\n+\tclkoutmux0_clk_mux: clock-clkoutmux0-clk-mux@158 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,mux-clock\";\n \t\tclocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;\n \t\treg = <0x0158>;\n \t};\n \n-\tclkoutmux1_clk_mux: clkoutmux1_clk_mux@15c {\n+\tclkoutmux1_clk_mux: clock-clkoutmux1-clk-mux@15c {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,mux-clock\";\n \t\tclocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;\n \t\treg = <0x015c>;\n \t};\n \n-\tclkoutmux2_clk_mux: clkoutmux2_clk_mux@160 {\n+\tclkoutmux2_clk_mux: clock-clkoutmux2-clk-mux@160 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,mux-clock\";\n \t\tclocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;\n \t\treg = <0x0160>;\n \t};\n \n-\tcustefuse_sys_gfclk_div: custefuse_sys_gfclk_div {\n+\tcustefuse_sys_gfclk_div: clock-custefuse-sys-gfclk-div {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&sys_clkin1>;\n@@ -1116,21 +1116,21 @@\n \t\tclock-div = <2>;\n \t};\n \n-\teve_clk: eve_clk@180 {\n+\teve_clk: clock-eve@180 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,mux-clock\";\n \t\tclocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;\n \t\treg = <0x0180>;\n \t};\n \n-\thdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 {\n+\thdmi_dpll_clk_mux: clock-hdmi-dpll-clk-mux@164 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,mux-clock\";\n \t\tclocks = <&sys_clkin1>, <&sys_clkin2>;\n \t\treg = <0x0164>;\n \t};\n \n-\tmlb_clk: mlb_clk@134 {\n+\tmlb_clk: clock-mlb@134 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&mlb_clkin_ck>;\n@@ -1139,7 +1139,7 @@\n \t\tti,index-power-of-two;\n \t};\n \n-\tmlbp_clk: mlbp_clk@130 {\n+\tmlbp_clk: clock-mlbp@130 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&mlbp_clkin_ck>;\n@@ -1148,7 +1148,7 @@\n \t\tti,index-power-of-two;\n \t};\n \n-\tper_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 {\n+\tper_abe_x1_gfclk2_div: clock-per-abe-x1-gfclk2-div@138 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_abe_m2_ck>;\n@@ -1157,7 +1157,7 @@\n \t\tti,index-power-of-two;\n \t};\n \n-\ttimer_sys_clk_div: timer_sys_clk_div@144 {\n+\ttimer_sys_clk_div: clock-timer-sys-clk-div@144 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&sys_clkin1>;\n@@ -1165,21 +1165,21 @@\n \t\tti,max-div = <2>;\n \t};\n \n-\tvideo1_dpll_clk_mux: video1_dpll_clk_mux@168 {\n+\tvideo1_dpll_clk_mux: clock-video1-dpll-clk-mux@168 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,mux-clock\";\n \t\tclocks = <&sys_clkin1>, <&sys_clkin2>;\n \t\treg = <0x0168>;\n \t};\n \n-\tvideo2_dpll_clk_mux: video2_dpll_clk_mux@16c {\n+\tvideo2_dpll_clk_mux: clock-video2-dpll-clk-mux@16c {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,mux-clock\";\n \t\tclocks = <&sys_clkin1>, <&sys_clkin2>;\n \t\treg = <0x016c>;\n \t};\n \n-\twkupaon_iclk_mux: wkupaon_iclk_mux@108 {\n+\twkupaon_iclk_mux: clock-wkupaon-iclk-mux@108 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,mux-clock\";\n \t\tclocks = <&sys_clkin1>, <&abe_lp_clk_div>;\n@@ -1219,14 +1219,14 @@\n \t};\n };\n &cm_core_clocks {\n-\tdpll_pcie_ref_ck: dpll_pcie_ref_ck@200 {\n+\tdpll_pcie_ref_ck: clock@200 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,omap4-dpll-clock\";\n \t\tclocks = <&sys_clkin1>, <&sys_clkin1>;\n \t\treg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;\n \t};\n \n-\tdpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 {\n+\tdpll_pcie_ref_m2ldo_ck: clock-dpll-pcie-ref-m2ldo-8@210 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_pcie_ref_ck>;\n@@ -1237,7 +1237,7 @@\n \t\tti,invert-autoidle-bit;\n \t};\n \n-\tapll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {\n+\tapll_pcie_in_clk_mux: clock-apll-pcie-in-clk-mux-7@4ae06118 {\n \t\tcompatible = \"ti,mux-clock\";\n \t\tclocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;\n \t\t#clock-cells = <0>;\n@@ -1245,7 +1245,7 @@\n \t\tti,bit-shift = <7>;\n \t};\n \n-\tapll_pcie_ck: apll_pcie_ck@21c {\n+\tapll_pcie_ck: clock@21c {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,dra7-apll-clock\";\n \t\tclocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;\n@@ -1268,7 +1268,7 @@\n \t\tti,bit-shift = <8>;\n \t};\n \n-\toptfclk_pciephy_div: optfclk_pciephy_div@4a00821c {\n+\toptfclk_pciephy_div: clock-optfclk-pciephy-div-8@4a00821c {\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&apll_pcie_ck>;\n \t\t#clock-cells = <0>;\n@@ -1310,7 +1310,7 @@\n \t\tti,bit-shift = <10>;\n \t};\n \n-\tapll_pcie_clkvcoldo: apll_pcie_clkvcoldo {\n+\tapll_pcie_clkvcoldo: clock-apll-pcie-clkvcoldo {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&apll_pcie_ck>;\n@@ -1318,7 +1318,7 @@\n \t\tclock-div = <1>;\n \t};\n \n-\tapll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {\n+\tapll_pcie_clkvcoldo_div: clock-apll-pcie-clkvcoldo-div {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&apll_pcie_ck>;\n@@ -1326,7 +1326,7 @@\n \t\tclock-div = <1>;\n \t};\n \n-\tapll_pcie_m2_ck: apll_pcie_m2_ck {\n+\tapll_pcie_m2_ck: clock-apll-pcie-m2 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&apll_pcie_ck>;\n@@ -1334,7 +1334,7 @@\n \t\tclock-div = <1>;\n \t};\n \n-\tdpll_per_byp_mux: dpll_per_byp_mux@14c {\n+\tdpll_per_byp_mux: clock-dpll-per-byp-mux-23@14c {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,mux-clock\";\n \t\tclocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;\n@@ -1342,14 +1342,14 @@\n \t\treg = <0x014c>;\n \t};\n \n-\tdpll_per_ck: dpll_per_ck@140 {\n+\tdpll_per_ck: clock@140 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,omap4-dpll-clock\";\n \t\tclocks = <&sys_clkin1>, <&dpll_per_byp_mux>;\n \t\treg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;\n \t};\n \n-\tdpll_per_m2_ck: dpll_per_m2_ck@150 {\n+\tdpll_per_m2_ck: clock-dpll-per-m2-8@150 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_per_ck>;\n@@ -1360,7 +1360,7 @@\n \t\tti,invert-autoidle-bit;\n \t};\n \n-\tfunc_96m_aon_dclk_div: func_96m_aon_dclk_div {\n+\tfunc_96m_aon_dclk_div: clock-func-96m-aon-dclk-div {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&dpll_per_m2_ck>;\n@@ -1368,7 +1368,7 @@\n \t\tclock-div = <1>;\n \t};\n \n-\tdpll_usb_byp_mux: dpll_usb_byp_mux@18c {\n+\tdpll_usb_byp_mux: clock-dpll-usb-byp-mux-23@18c {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,mux-clock\";\n \t\tclocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;\n@@ -1376,14 +1376,14 @@\n \t\treg = <0x018c>;\n \t};\n \n-\tdpll_usb_ck: dpll_usb_ck@180 {\n+\tdpll_usb_ck: clock@180 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,omap4-dpll-j-type-clock\";\n \t\tclocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;\n \t\treg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;\n \t};\n \n-\tdpll_usb_m2_ck: dpll_usb_m2_ck@190 {\n+\tdpll_usb_m2_ck: clock-dpll-usb-m2-8@190 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_usb_ck>;\n@@ -1394,7 +1394,7 @@\n \t\tti,invert-autoidle-bit;\n \t};\n \n-\tdpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 {\n+\tdpll_pcie_ref_m2_ck: clock-dpll-pcie-ref-m2-8@210 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_pcie_ref_ck>;\n@@ -1405,13 +1405,13 @@\n \t\tti,invert-autoidle-bit;\n \t};\n \n-\tdpll_per_x2_ck: dpll_per_x2_ck {\n+\tdpll_per_x2_ck: clock-dpll-per-x2 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,omap4-dpll-x2-clock\";\n \t\tclocks = <&dpll_per_ck>;\n \t};\n \n-\tdpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {\n+\tdpll_per_h11x2_ck: clock-dpll-per-h11x2-8@158 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_per_x2_ck>;\n@@ -1422,7 +1422,7 @@\n \t\tti,invert-autoidle-bit;\n \t};\n \n-\tdpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {\n+\tdpll_per_h12x2_ck: clock-dpll-per-h12x2-8@15c {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_per_x2_ck>;\n@@ -1433,7 +1433,7 @@\n \t\tti,invert-autoidle-bit;\n \t};\n \n-\tdpll_per_h13x2_ck: dpll_per_h13x2_ck@160 {\n+\tdpll_per_h13x2_ck: clock-dpll-per-h13x2-8@160 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_per_x2_ck>;\n@@ -1444,7 +1444,7 @@\n \t\tti,invert-autoidle-bit;\n \t};\n \n-\tdpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {\n+\tdpll_per_h14x2_ck: clock-dpll-per-h14x2-8@164 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_per_x2_ck>;\n@@ -1455,7 +1455,7 @@\n \t\tti,invert-autoidle-bit;\n \t};\n \n-\tdpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {\n+\tdpll_per_m2x2_ck: clock-dpll-per-m2x2-8@150 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_per_x2_ck>;\n@@ -1466,7 +1466,7 @@\n \t\tti,invert-autoidle-bit;\n \t};\n \n-\tdpll_usb_clkdcoldo: dpll_usb_clkdcoldo {\n+\tdpll_usb_clkdcoldo: clock-dpll-usb-clkdcoldo {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&dpll_usb_ck>;\n@@ -1474,7 +1474,7 @@\n \t\tclock-div = <1>;\n \t};\n \n-\tfunc_128m_clk: func_128m_clk {\n+\tfunc_128m_clk: clock-func-128m {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&dpll_per_h11x2_ck>;\n@@ -1482,7 +1482,7 @@\n \t\tclock-div = <2>;\n \t};\n \n-\tfunc_12m_fclk: func_12m_fclk {\n+\tfunc_12m_fclk: clock-func-12m-fclk {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&dpll_per_m2x2_ck>;\n@@ -1490,7 +1490,7 @@\n \t\tclock-div = <16>;\n \t};\n \n-\tfunc_24m_clk: func_24m_clk {\n+\tfunc_24m_clk: clock-func-24m {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&dpll_per_m2_ck>;\n@@ -1498,7 +1498,7 @@\n \t\tclock-div = <4>;\n \t};\n \n-\tfunc_48m_fclk: func_48m_fclk {\n+\tfunc_48m_fclk: clock-func-48m-fclk {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&dpll_per_m2x2_ck>;\n@@ -1506,7 +1506,7 @@\n \t\tclock-div = <4>;\n \t};\n \n-\tfunc_96m_fclk: func_96m_fclk {\n+\tfunc_96m_fclk: clock-func-96m-fclk {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"fixed-factor-clock\";\n \t\tclocks = <&dpll_per_m2x2_ck>;\n@@ -1514,7 +1514,7 @@\n \t\tclock-div = <2>;\n \t};\n \n-\tl3init_60m_fclk: l3init_60m_fclk@104 {\n+\tl3init_60m_fclk: clock-l3init-60m@104 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&dpll_usb_m2_ck>;\n@@ -1522,7 +1522,7 @@\n \t\tti,dividers = <1>, <8>;\n \t};\n \n-\tclkout2_clk: clkout2_clk@6b0 {\n+\tclkout2_clk: clock-clkout2-8@6b0 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,gate-clock\";\n \t\tclocks = <&clkoutmux2_clk_mux>;\n@@ -1530,7 +1530,7 @@\n \t\treg = <0x06b0>;\n \t};\n \n-\tl3init_960m_gfclk: l3init_960m_gfclk@6c0 {\n+\tl3init_960m_gfclk: clock-l3init-960m-gfclk-8@6c0 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,gate-clock\";\n \t\tclocks = <&dpll_usb_clkdcoldo>;\n@@ -1699,7 +1699,7 @@\n \t\treg = <0x1340>;\n \t};\n \n-\tusb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 {\n+\tusb_phy1_always_on_clk32k: clock-usb-phy1-always-on-clk32k-8@640 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,gate-clock\";\n \t\tclocks = <&sys_32k_ck>;\n@@ -1707,7 +1707,7 @@\n \t\treg = <0x0640>;\n \t};\n \n-\tusb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 {\n+\tusb_phy2_always_on_clk32k: clock-usb-phy2-always-on-clk32k-8@688 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,gate-clock\";\n \t\tclocks = <&sys_32k_ck>;\n@@ -1715,7 +1715,7 @@\n \t\treg = <0x0688>;\n \t};\n \n-\tusb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 {\n+\tusb_phy3_always_on_clk32k: clock-usb-phy3-always-on-clk32k-8@698 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,gate-clock\";\n \t\tclocks = <&sys_32k_ck>;\n@@ -1755,7 +1755,7 @@\n \t\treg = <0x13d0>;\n \t};\n \n-\tgpu_core_gclk_mux: gpu_core_gclk_mux@1220 {\n+\tgpu_core_gclk_mux: clock-gpu-core-gclk-mux-24@1220 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,mux-clock\";\n \t\tclocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;\n@@ -1765,7 +1765,7 @@\n \t\tassigned-clock-parents = <&dpll_gpu_m2_ck>;\n \t};\n \n-\tgpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 {\n+\tgpu_hyd_gclk_mux: clock-gpu-hyd-gclk-mux-26@1220 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,mux-clock\";\n \t\tclocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;\n@@ -1775,7 +1775,7 @@\n \t\tassigned-clock-parents = <&dpll_gpu_m2_ck>;\n \t};\n \n-\tl3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 {\n+\tl3instr_ts_gclk_div: clock-l3instr-ts-gclk-div-24@e50 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,divider-clock\";\n \t\tclocks = <&wkupaon_iclk_mux>;\n@@ -2138,7 +2138,7 @@\n \t\treg = <0x18e8>;\n \t};\n \n-\tvip1_gclk_mux: vip1_gclk_mux@1020 {\n+\tvip1_gclk_mux: clock-vip1-gclk-mux-24@1020 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,mux-clock\";\n \t\tclocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;\n@@ -2146,7 +2146,7 @@\n \t\treg = <0x1020>;\n \t};\n \n-\tvip2_gclk_mux: vip2_gclk_mux@1028 {\n+\tvip2_gclk_mux: clock-vip2-gclk-mux-24@1028 {\n \t\t#clock-cells = <0>;\n \t\tcompatible = \"ti,mux-clock\";\n \t\tclocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;\n",
    "prefixes": [
        "13/17"
    ]
}