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{
    "id": 1761711,
    "url": "http://patchwork.ozlabs.org/api/patches/1761711/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20230327132718.573-3-quic_devipriy@quicinc.com/",
    "project": {
        "id": 42,
        "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api",
        "name": "Linux GPIO development",
        "link_name": "linux-gpio",
        "list_id": "linux-gpio.vger.kernel.org",
        "list_email": "linux-gpio@vger.kernel.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": "",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20230327132718.573-3-quic_devipriy@quicinc.com>",
    "list_archive_url": null,
    "date": "2023-03-27T13:27:16",
    "name": "[V10,2/4] clk: qcom: Add Global Clock Controller driver for IPQ9574",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "c2a320c2dae38fb9c2ec9de7781985ccfc43f261",
    "submitter": {
        "id": 85567,
        "url": "http://patchwork.ozlabs.org/api/people/85567/?format=api",
        "name": "Devi Priya",
        "email": "quic_devipriy@quicinc.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20230327132718.573-3-quic_devipriy@quicinc.com/mbox/",
    "series": [
        {
            "id": 348168,
            "url": "http://patchwork.ozlabs.org/api/series/348168/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=348168",
            "date": "2023-03-27T13:27:14",
            "name": "Add minimal boot support for IPQ9574",
            "version": 10,
            "mbox": "http://patchwork.ozlabs.org/series/348168/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/1761711/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/1761711/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Devi Priya <quic_devipriy@quicinc.com>",
        "To": "<agross@kernel.org>, <andersson@kernel.org>,\n        <konrad.dybcio@linaro.org>, <robh+dt@kernel.org>,\n        <krzysztof.kozlowski+dt@linaro.org>, <mturquette@baylibre.com>,\n        <sboyd@kernel.org>, <linus.walleij@linaro.org>,\n        <catalin.marinas@arm.com>, <will@kernel.org>,\n        <p.zabel@pengutronix.de>, <shawnguo@kernel.org>, <arnd@arndb.de>,\n        <marcel.ziswiler@toradex.com>, <dmitry.baryshkov@linaro.org>,\n        <nfraprado@collabora.com>, <broonie@kernel.org>,\n        <linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>,\n        <linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>,\n        <linux-gpio@vger.kernel.org>,\n        <linux-arm-kernel@lists.infradead.org>",
        "CC": "<quic_srichara@quicinc.com>, <quic_gokulsri@quicinc.com>,\n        <quic_sjaganat@quicinc.com>, <quic_kathirav@quicinc.com>,\n        <quic_arajkuma@quicinc.com>, <quic_anusha@quicinc.com>,\n        <quic_poovendh@quicinc.com>",
        "Subject": "[PATCH V10 2/4] clk: qcom: Add Global Clock Controller driver for\n IPQ9574",
        "Date": "Mon, 27 Mar 2023 18:57:16 +0530",
        "Message-ID": "<20230327132718.573-3-quic_devipriy@quicinc.com>",
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        "References": "<20230327132718.573-1-quic_devipriy@quicinc.com>",
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        "List-ID": "<linux-gpio.vger.kernel.org>",
        "X-Mailing-List": "linux-gpio@vger.kernel.org"
    },
    "content": "Add Global Clock Controller (GCC) driver for ipq9574 based devices\n\nCo-developed-by: Anusha Rao <quic_anusha@quicinc.com>\nSigned-off-by: Anusha Rao <quic_anusha@quicinc.com>\nSigned-off-by: Devi Priya <quic_devipriy@quicinc.com>\n---\n Changes in V10:\n\t- No change\n\n drivers/clk/qcom/Kconfig       |    8 +\n drivers/clk/qcom/Makefile      |    1 +\n drivers/clk/qcom/gcc-ipq9574.c | 4248 ++++++++++++++++++++++++++++++++\n 3 files changed, 4257 insertions(+)\n create mode 100644 drivers/clk/qcom/gcc-ipq9574.c",
    "diff": "diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig\nindex 449bc8314d21..d71c9d6036bb 100644\n--- a/drivers/clk/qcom/Kconfig\n+++ b/drivers/clk/qcom/Kconfig\n@@ -181,6 +181,14 @@ config IPQ_GCC_8074\n \t  i2c, USB, SD/eMMC, etc. Select this for the root clock\n \t  of ipq8074.\n \n+config IPQ_GCC_9574\n+\ttristate \"IPQ9574 Global Clock Controller\"\n+\thelp\n+\t  Support for global clock controller on ipq9574 devices.\n+\t  Say Y if you want to use peripheral devices such as UART, SPI,\n+\t  i2c, USB, SD/eMMC, etc. Select this for the root clock\n+\t  of ipq9574.\n+\n config MSM_GCC_8660\n \ttristate \"MSM8660 Global Clock Controller\"\n \thelp\ndiff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile\nindex c1adb427d1ef..b54085e579a0 100644\n--- a/drivers/clk/qcom/Makefile\n+++ b/drivers/clk/qcom/Makefile\n@@ -28,6 +28,7 @@ obj-$(CONFIG_IPQ_GCC_5332) += gcc-ipq5332.o\n obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o\n obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o\n obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o\n+obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o\n obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o\n obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o\n obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o\ndiff --git a/drivers/clk/qcom/gcc-ipq9574.c b/drivers/clk/qcom/gcc-ipq9574.c\nnew file mode 100644\nindex 000000000000..b2a2d618a5ec\n--- /dev/null\n+++ b/drivers/clk/qcom/gcc-ipq9574.c\n@@ -0,0 +1,4248 @@\n+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+/*\n+ * Copyright (c) 2023 The Linux Foundation. All rights reserved.\n+ */\n+\n+#include <linux/kernel.h>\n+#include <linux/err.h>\n+#include <linux/platform_device.h>\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/of_device.h>\n+#include <linux/regmap.h>\n+\n+#include <linux/reset-controller.h>\n+#include <dt-bindings/clock/qcom,ipq9574-gcc.h>\n+#include <dt-bindings/reset/qcom,ipq9574-gcc.h>\n+\n+#include \"clk-rcg.h\"\n+#include \"clk-branch.h\"\n+#include \"clk-alpha-pll.h\"\n+#include \"clk-regmap-divider.h\"\n+#include \"clk-regmap-mux.h\"\n+#include \"clk-regmap-phy-mux.h\"\n+#include \"reset.h\"\n+\n+/* Need to match the order of clocks in DT binding */\n+enum {\n+\tDT_XO,\n+\tDT_SLEEP_CLK,\n+\tDT_BIAS_PLL_UBI_NC_CLK,\n+\tDT_PCIE30_PHY0_PIPE_CLK,\n+\tDT_PCIE30_PHY1_PIPE_CLK,\n+\tDT_PCIE30_PHY2_PIPE_CLK,\n+\tDT_PCIE30_PHY3_PIPE_CLK,\n+\tDT_USB3PHY_0_CC_PIPE_CLK,\n+};\n+\n+enum {\n+\tP_XO,\n+\tP_PCIE30_PHY0_PIPE,\n+\tP_PCIE30_PHY1_PIPE,\n+\tP_PCIE30_PHY2_PIPE,\n+\tP_PCIE30_PHY3_PIPE,\n+\tP_USB3PHY_0_PIPE,\n+\tP_GPLL0,\n+\tP_GPLL0_DIV2,\n+\tP_GPLL0_OUT_AUX,\n+\tP_GPLL2,\n+\tP_GPLL4,\n+\tP_PI_SLEEP,\n+\tP_BIAS_PLL_UBI_NC_CLK,\n+};\n+\n+static const struct parent_map gcc_xo_map[] = {\n+\t{ P_XO, 0 },\n+};\n+\n+static const struct clk_parent_data gcc_xo_data[] = {\n+\t{ .index = DT_XO },\n+};\n+\n+static const struct clk_parent_data gcc_sleep_clk_data[] = {\n+\t{ .index = DT_SLEEP_CLK },\n+};\n+\n+static struct clk_alpha_pll gpll0_main = {\n+\t.offset = 0x20000,\n+\t.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],\n+\t.clkr = {\n+\t\t.enable_reg = 0x0b000,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gpll0_main\",\n+\t\t\t.parent_data = gcc_xo_data,\n+\t\t\t.num_parents = ARRAY_SIZE(gcc_xo_data),\n+\t\t\t.ops = &clk_alpha_pll_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_fixed_factor gpll0_out_main_div2 = {\n+\t.mult = 1,\n+\t.div = 2,\n+\t.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"gpll0_out_main_div2\",\n+\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t&gpll0_main.clkr.hw\n+\t\t},\n+\t\t.num_parents = 1,\n+\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t.ops = &clk_fixed_factor_ops,\n+\t},\n+};\n+\n+static struct clk_alpha_pll_postdiv gpll0 = {\n+\t.offset = 0x20000,\n+\t.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],\n+\t.width = 4,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"gpll0\",\n+\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t&gpll0_main.clkr.hw\n+\t\t},\n+\t\t.num_parents = 1,\n+\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t.ops = &clk_alpha_pll_postdiv_ro_ops,\n+\t},\n+};\n+\n+static struct clk_alpha_pll gpll4_main = {\n+\t.offset = 0x22000,\n+\t.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],\n+\t.clkr = {\n+\t\t.enable_reg = 0x0b000,\n+\t\t.enable_mask = BIT(2),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gpll4_main\",\n+\t\t\t.parent_data = gcc_xo_data,\n+\t\t\t.num_parents = ARRAY_SIZE(gcc_xo_data),\n+\t\t\t.ops = &clk_alpha_pll_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_alpha_pll_postdiv gpll4 = {\n+\t.offset = 0x22000,\n+\t.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],\n+\t.width = 4,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"gpll4\",\n+\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t&gpll4_main.clkr.hw\n+\t\t},\n+\t\t.num_parents = 1,\n+\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t.ops = &clk_alpha_pll_postdiv_ro_ops,\n+\t},\n+};\n+\n+static struct clk_alpha_pll gpll2_main = {\n+\t.offset = 0x21000,\n+\t.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],\n+\t.clkr = {\n+\t\t.enable_reg = 0x0b000,\n+\t\t.enable_mask = BIT(1),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gpll2_main\",\n+\t\t\t.parent_data = gcc_xo_data,\n+\t\t\t.num_parents = ARRAY_SIZE(gcc_xo_data),\n+\t\t\t.ops = &clk_alpha_pll_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_alpha_pll_postdiv gpll2 = {\n+\t.offset = 0x21000,\n+\t.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_DEFAULT],\n+\t.width = 4,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"gpll2\",\n+\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t&gpll2_main.clkr.hw\n+\t\t},\n+\t\t.num_parents = 1,\n+\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t.ops = &clk_alpha_pll_postdiv_ro_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_sleep_clk_src = {\n+\t.halt_reg = 0x3400c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x3400c,\n+\t\t.enable_mask = BIT(1),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_sleep_clk_src\",\n+\t\t\t.parent_data = gcc_sleep_clk_data,\n+\t\t\t.num_parents = ARRAY_SIZE(gcc_sleep_clk_data),\n+\t\t\t.flags = CLK_IS_CRITICAL,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static const struct clk_parent_data gcc_xo_gpll0_gpll0_out_main_div2[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .hw = &gpll0_out_main_div2.hw },\n+};\n+\n+static const struct parent_map gcc_xo_gpll0_gpll0_out_main_div2_map[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0, 1 },\n+\t{ P_GPLL0_DIV2, 4 },\n+};\n+\n+static const struct clk_parent_data gcc_xo_gpll0[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll0.clkr.hw },\n+};\n+\n+static const struct parent_map gcc_xo_gpll0_map[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0, 1 },\n+};\n+\n+static const struct clk_parent_data gcc_xo_gpll0_gpll4[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .hw = &gpll4.clkr.hw },\n+};\n+\n+static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0, 1 },\n+\t{ P_GPLL4, 2 },\n+};\n+\n+static const struct clk_parent_data gcc_xo_gpll0_gpll0_div2_gpll0[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .hw = &gpll0_out_main_div2.hw },\n+\t{ .hw = &gpll0.clkr.hw },\n+};\n+\n+static const struct parent_map gcc_xo_gpll0_gpll0_div2_gpll0_map[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0, 1 },\n+\t{ P_GPLL0_DIV2, 4 },\n+\t{ P_GPLL0, 5 },\n+};\n+\n+static const struct clk_parent_data gcc_xo_gpll0_gpll0_sleep_clk[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .hw = &gpll0_out_main_div2.hw },\n+\t{ .index = DT_SLEEP_CLK },\n+};\n+\n+static const struct parent_map gcc_xo_gpll0_gpll0_sleep_clk_map[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0, 1 },\n+\t{ P_GPLL0_DIV2, 4 },\n+\t{ P_PI_SLEEP, 6 },\n+};\n+\n+static const struct clk_parent_data gcc_xo_gpll0_core_pi_sleep_clk[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .index = DT_SLEEP_CLK },\n+};\n+\n+static const struct parent_map gcc_xo_gpll0_core_pi_sleep_clk_map[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0, 2 },\n+\t{ P_PI_SLEEP, 6 },\n+};\n+\n+static const struct clk_parent_data gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .hw = &gpll4.clkr.hw },\n+\t{ .index = DT_BIAS_PLL_UBI_NC_CLK },\n+};\n+\n+static const struct parent_map gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0, 1 },\n+\t{ P_GPLL4, 2 },\n+\t{ P_BIAS_PLL_UBI_NC_CLK, 3 },\n+};\n+\n+static const struct clk_parent_data\n+\t\t\tgcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .index = DT_SLEEP_CLK },\n+};\n+\n+static const struct parent_map\n+\t\t\tgcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk_map[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0, 1 },\n+\t{ P_GPLL0_OUT_AUX, 2 },\n+\t{ P_PI_SLEEP, 6 },\n+};\n+\n+static const struct clk_parent_data gcc_xo_gpll0_out_main_div2_gpll0[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .hw = &gpll0_out_main_div2.hw },\n+};\n+\n+static const struct parent_map gcc_xo_gpll0_out_main_div2_gpll0_map[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0, 1 },\n+\t{ P_GPLL0_DIV2, 4 },\n+};\n+\n+static const struct clk_parent_data\n+\t\t\tgcc_xo_gpll4_gpll0_gpll0_out_main_div2[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll4.clkr.hw },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .hw = &gpll0_out_main_div2.hw },\n+};\n+\n+static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL4, 1 },\n+\t{ P_GPLL0, 3 },\n+\t{ P_GPLL0_DIV2, 4 },\n+};\n+\n+static const struct clk_parent_data gcc_usb3phy_0_cc_pipe_clk_xo[] = {\n+\t{ .index = DT_USB3PHY_0_CC_PIPE_CLK },\n+\t{ .index = DT_XO },\n+};\n+\n+static const struct parent_map gcc_usb3phy_0_cc_pipe_clk_xo_map[] = {\n+\t{ P_USB3PHY_0_PIPE, 0 },\n+\t{ P_XO, 2 },\n+};\n+\n+static const struct clk_parent_data\n+\t\t\tgcc_xo_gpll0_gpll2_gpll0_out_main_div2[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .hw = &gpll2.clkr.hw },\n+\t{ .hw = &gpll0_out_main_div2.hw },\n+};\n+\n+static const struct parent_map gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0, 1 },\n+\t{ P_GPLL2, 2 },\n+\t{ P_GPLL0_DIV2, 4 },\n+};\n+\n+static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_div2[] = {\n+\t{ .index = DT_XO},\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .hw = &gpll4.clkr.hw },\n+\t{ .hw = &gpll0_out_main_div2.hw },\n+};\n+\n+static const struct parent_map gcc_xo_gpll0_gpll4_gpll0_div2_map[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0, 1 },\n+\t{ P_GPLL4, 2 },\n+\t{ P_GPLL0_DIV2, 4 },\n+};\n+\n+static const struct clk_parent_data gcc_xo_gpll4_gpll0_gpll0_div2[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll4.clkr.hw },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .hw = &gpll0_out_main_div2.hw },\n+};\n+\n+static const struct parent_map gcc_xo_gpll4_gpll0_gpll0_div2_map[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL4, 1 },\n+\t{ P_GPLL0, 2 },\n+\t{ P_GPLL0_DIV2, 4 },\n+};\n+\n+static const struct clk_parent_data gcc_xo_gpll0_gpll2[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .hw = &gpll2.clkr.hw },\n+};\n+\n+static const struct parent_map gcc_xo_gpll0_gpll2_map[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0, 1 },\n+\t{ P_GPLL2, 2 },\n+};\n+\n+static const struct clk_parent_data gcc_xo_gpll0_gpll2_gpll4_pi_sleep[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .hw = &gpll2.clkr.hw },\n+\t{ .hw = &gpll4.clkr.hw },\n+\t{ .index = DT_SLEEP_CLK },\n+};\n+\n+static const struct parent_map gcc_xo_gpll0_gpll2_gpll4_pi_sleep_map[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0, 1 },\n+\t{ P_GPLL2, 2 },\n+\t{ P_GPLL4, 3 },\n+\t{ P_PI_SLEEP, 6 },\n+};\n+\n+static const struct clk_parent_data gcc_xo_gpll0_gpll0_aux_gpll2[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .hw = &gpll2.clkr.hw },\n+};\n+\n+static const struct parent_map gcc_xo_gpll0_gpll0_aux_gpll2_map[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0, 1 },\n+\t{ P_GPLL0_OUT_AUX, 2 },\n+\t{ P_GPLL2, 3 },\n+};\n+\n+static const struct freq_tbl ftbl_apss_ahb_clk_src[] = {\n+\tF(24000000, P_XO, 1, 0, 0),\n+\tF(50000000, P_GPLL0, 16, 0, 0),\n+\tF(100000000, P_GPLL0, 8, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 apss_ahb_clk_src = {\n+\t.cmd_rcgr = 0x2400c,\n+\t.freq_tbl = ftbl_apss_ahb_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"apss_ahb_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_apss_axi_clk_src[] = {\n+\tF(533000000, P_GPLL0, 1.5, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 apss_axi_clk_src = {\n+\t.cmd_rcgr = 0x24004,\n+\t.freq_tbl = ftbl_apss_axi_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_div2_gpll0_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"apss_axi_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_div2_gpll0,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_div2_gpll0),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_blsp1_qup_i2c_apps_clk_src[] = {\n+\tF(9600000, P_XO, 2.5, 0, 0),\n+\tF(24000000, P_XO, 1, 0, 0),\n+\tF(50000000, P_GPLL0, 16, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 blsp1_qup1_i2c_apps_clk_src = {\n+\t.cmd_rcgr = 0x02018,\n+\t.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"blsp1_qup1_i2c_apps_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_blsp1_qup_spi_apps_clk_src[] = {\n+\tF(960000, P_XO, 10, 2, 5),\n+\tF(4800000, P_XO, 5, 0, 0),\n+\tF(9600000, P_XO, 2, 4, 5),\n+\tF(16000000, P_GPLL0, 10, 1, 5),\n+\tF(24000000, P_XO, 1, 0, 0),\n+\tF(25000000, P_GPLL0, 16, 1, 2),\n+\tF(50000000, P_GPLL0, 16, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 blsp1_qup1_spi_apps_clk_src = {\n+\t.cmd_rcgr = 0x02004,\n+\t.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,\n+\t.mnd_width = 8,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"blsp1_qup1_spi_apps_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 blsp1_qup2_i2c_apps_clk_src = {\n+\t.cmd_rcgr = 0x03018,\n+\t.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"blsp1_qup2_i2c_apps_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 blsp1_qup2_spi_apps_clk_src = {\n+\t.cmd_rcgr = 0x03004,\n+\t.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,\n+\t.mnd_width = 8,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"blsp1_qup2_spi_apps_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 blsp1_qup3_i2c_apps_clk_src = {\n+\t.cmd_rcgr = 0x04018,\n+\t.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"blsp1_qup3_i2c_apps_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 blsp1_qup3_spi_apps_clk_src = {\n+\t.cmd_rcgr = 0x04004,\n+\t.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,\n+\t.mnd_width = 8,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"blsp1_qup3_spi_apps_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 blsp1_qup4_i2c_apps_clk_src = {\n+\t.cmd_rcgr = 0x05018,\n+\t.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"blsp1_qup4_i2c_apps_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 blsp1_qup4_spi_apps_clk_src = {\n+\t.cmd_rcgr = 0x05004,\n+\t.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,\n+\t.mnd_width = 8,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"blsp1_qup4_spi_apps_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 blsp1_qup5_i2c_apps_clk_src = {\n+\t.cmd_rcgr = 0x06018,\n+\t.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"blsp1_qup5_i2c_apps_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 blsp1_qup5_spi_apps_clk_src = {\n+\t.cmd_rcgr = 0x06004,\n+\t.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,\n+\t.mnd_width = 8,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"blsp1_qup5_spi_apps_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 blsp1_qup6_i2c_apps_clk_src = {\n+\t.cmd_rcgr = 0x07018,\n+\t.freq_tbl = ftbl_blsp1_qup_i2c_apps_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"blsp1_qup6_i2c_apps_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 blsp1_qup6_spi_apps_clk_src = {\n+\t.cmd_rcgr = 0x07004,\n+\t.freq_tbl = ftbl_blsp1_qup_spi_apps_clk_src,\n+\t.mnd_width = 8,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"blsp1_qup6_spi_apps_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_blsp1_uart_apps_clk_src[] = {\n+\tF(3686400, P_GPLL0_DIV2, 1, 144, 15625),\n+\tF(7372800, P_GPLL0_DIV2, 1, 288, 15625),\n+\tF(14745600, P_GPLL0_DIV2, 1, 576, 15625),\n+\tF(24000000, P_XO, 1, 0, 0),\n+\tF(25000000, P_GPLL0, 16, 1, 2),\n+\tF(32000000, P_GPLL0, 1, 1, 25),\n+\tF(40000000, P_GPLL0, 1, 1, 20),\n+\tF(46400000, P_GPLL0, 1, 29, 500),\n+\tF(48000000, P_GPLL0, 1, 3, 50),\n+\tF(51200000, P_GPLL0, 1, 8, 125),\n+\tF(56000000, P_GPLL0, 1, 7, 100),\n+\tF(58982400, P_GPLL0, 1, 1152, 15625),\n+\tF(60000000, P_GPLL0, 1, 3, 40),\n+\tF(64000000, P_GPLL0, 12.5, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 blsp1_uart1_apps_clk_src = {\n+\t.cmd_rcgr = 0x0202c,\n+\t.freq_tbl = ftbl_blsp1_uart_apps_clk_src,\n+\t.mnd_width = 16,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"blsp1_uart1_apps_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 blsp1_uart2_apps_clk_src = {\n+\t.cmd_rcgr = 0x0302c,\n+\t.freq_tbl = ftbl_blsp1_uart_apps_clk_src,\n+\t.mnd_width = 16,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"blsp1_uart2_apps_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 blsp1_uart3_apps_clk_src = {\n+\t.cmd_rcgr = 0x0402c,\n+\t.freq_tbl = ftbl_blsp1_uart_apps_clk_src,\n+\t.mnd_width = 16,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"blsp1_uart3_apps_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 blsp1_uart4_apps_clk_src = {\n+\t.cmd_rcgr = 0x0502c,\n+\t.freq_tbl = ftbl_blsp1_uart_apps_clk_src,\n+\t.mnd_width = 16,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"blsp1_uart4_apps_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 blsp1_uart5_apps_clk_src = {\n+\t.cmd_rcgr = 0x0602c,\n+\t.freq_tbl = ftbl_blsp1_uart_apps_clk_src,\n+\t.mnd_width = 16,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"blsp1_uart5_apps_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 blsp1_uart6_apps_clk_src = {\n+\t.cmd_rcgr = 0x0702c,\n+\t.freq_tbl = ftbl_blsp1_uart_apps_clk_src,\n+\t.mnd_width = 16,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"blsp1_uart6_apps_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_apss_ahb_clk = {\n+\t.halt_reg = 0x24018,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x0b004,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_apss_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&apss_ahb_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_apss_axi_clk = {\n+\t.halt_reg = 0x2401c,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x0b004,\n+\t\t.enable_mask = BIT(1),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_apss_axi_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&apss_axi_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {\n+\t.halt_reg = 0x2024,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2024,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_qup1_i2c_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&blsp1_qup1_i2c_apps_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {\n+\t.halt_reg = 0x02020,\n+\t.clkr = {\n+\t\t.enable_reg = 0x02020,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_qup1_spi_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&blsp1_qup1_spi_apps_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {\n+\t.halt_reg = 0x03024,\n+\t.clkr = {\n+\t\t.enable_reg = 0x03024,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_qup2_i2c_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&blsp1_qup2_i2c_apps_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {\n+\t.halt_reg = 0x03020,\n+\t.clkr = {\n+\t\t.enable_reg = 0x03020,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_qup2_spi_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&blsp1_qup2_spi_apps_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {\n+\t.halt_reg = 0x04024,\n+\t.clkr = {\n+\t\t.enable_reg = 0x04024,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_qup3_i2c_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&blsp1_qup3_i2c_apps_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {\n+\t.halt_reg = 0x04020,\n+\t.clkr = {\n+\t\t.enable_reg = 0x04020,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_qup3_spi_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&blsp1_qup3_spi_apps_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_qup4_i2c_apps_clk = {\n+\t.halt_reg = 0x05024,\n+\t.clkr = {\n+\t\t.enable_reg = 0x05024,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_qup4_i2c_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&blsp1_qup4_i2c_apps_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_qup4_spi_apps_clk = {\n+\t.halt_reg = 0x05020,\n+\t.clkr = {\n+\t\t.enable_reg = 0x05020,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_qup4_spi_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&blsp1_qup4_spi_apps_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_qup5_i2c_apps_clk = {\n+\t.halt_reg = 0x06024,\n+\t.clkr = {\n+\t\t.enable_reg = 0x06024,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_qup5_i2c_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&blsp1_qup5_i2c_apps_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_qup5_spi_apps_clk = {\n+\t.halt_reg = 0x06020,\n+\t.clkr = {\n+\t\t.enable_reg = 0x06020,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_qup5_spi_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&blsp1_qup5_spi_apps_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_qup6_i2c_apps_clk = {\n+\t.halt_reg = 0x07024,\n+\t.clkr = {\n+\t\t.enable_reg = 0x07024,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_qup6_i2c_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&blsp1_qup6_i2c_apps_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_qup6_spi_apps_clk = {\n+\t.halt_reg = 0x07020,\n+\t.clkr = {\n+\t\t.enable_reg = 0x07020,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_qup6_spi_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&blsp1_qup6_spi_apps_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_uart1_apps_clk = {\n+\t.halt_reg = 0x02040,\n+\t.clkr = {\n+\t\t.enable_reg = 0x02040,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_uart1_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&blsp1_uart1_apps_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_uart2_apps_clk = {\n+\t.halt_reg = 0x03040,\n+\t.clkr = {\n+\t\t.enable_reg = 0x03040,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_uart2_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&blsp1_uart2_apps_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_uart3_apps_clk = {\n+\t.halt_reg = 0x04054,\n+\t.clkr = {\n+\t\t.enable_reg = 0x04054,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_uart3_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&blsp1_uart3_apps_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_uart4_apps_clk = {\n+\t.halt_reg = 0x05040,\n+\t.clkr = {\n+\t\t.enable_reg = 0x05040,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_uart4_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&blsp1_uart4_apps_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_uart5_apps_clk = {\n+\t.halt_reg = 0x06040,\n+\t.clkr = {\n+\t\t.enable_reg = 0x06040,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_uart5_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&blsp1_uart5_apps_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_uart6_apps_clk = {\n+\t.halt_reg = 0x07040,\n+\t.clkr = {\n+\t\t.enable_reg = 0x07040,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_uart6_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&blsp1_uart6_apps_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_pcie0_axi_m_clk_src[] = {\n+\tF(240000000, P_GPLL4, 5, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 pcie0_axi_m_clk_src = {\n+\t.cmd_rcgr = 0x28018,\n+\t.freq_tbl = ftbl_pcie0_axi_m_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll4_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"pcie0_axi_m_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll4,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie0_axi_m_clk = {\n+\t.halt_reg = 0x28038,\n+\t.clkr = {\n+\t\t.enable_reg = 0x28038,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie0_axi_m_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie0_axi_m_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_anoc_pcie0_1lane_m_clk = {\n+\t.halt_reg = 0x2e07c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2e07c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_anoc_pcie0_1lane_m_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie0_axi_m_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_rcg2 pcie1_axi_m_clk_src = {\n+\t.cmd_rcgr = 0x29018,\n+\t.freq_tbl = ftbl_pcie0_axi_m_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll4_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"pcie1_axi_m_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll4,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie1_axi_m_clk = {\n+\t.halt_reg = 0x29038,\n+\t.clkr = {\n+\t\t.enable_reg = 0x29038,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie1_axi_m_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie1_axi_m_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_anoc_pcie1_1lane_m_clk = {\n+\t.halt_reg = 0x2e08c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2e08c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_anoc_pcie1_1lane_m_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie1_axi_m_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_pcie2_axi_m_clk_src[] = {\n+\tF(342857143, P_GPLL4, 3.5, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 pcie2_axi_m_clk_src = {\n+\t.cmd_rcgr = 0x2a018,\n+\t.freq_tbl = ftbl_pcie2_axi_m_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"pcie2_axi_m_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie2_axi_m_clk = {\n+\t.halt_reg = 0x2a038,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2a038,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie2_axi_m_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie2_axi_m_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_anoc_pcie2_2lane_m_clk = {\n+\t.halt_reg = 0x2e080,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2e080,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_anoc_pcie2_2lane_m_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie2_axi_m_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_rcg2 pcie3_axi_m_clk_src = {\n+\t.cmd_rcgr = 0x2b018,\n+\t.freq_tbl = ftbl_pcie2_axi_m_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"pcie3_axi_m_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie3_axi_m_clk = {\n+\t.halt_reg = 0x2b038,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2b038,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie3_axi_m_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie3_axi_m_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_anoc_pcie3_2lane_m_clk = {\n+\t.halt_reg = 0x2e090,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2e090,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_anoc_pcie3_2lane_m_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie3_axi_m_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_rcg2 pcie0_axi_s_clk_src = {\n+\t.cmd_rcgr = 0x28020,\n+\t.freq_tbl = ftbl_pcie0_axi_m_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll4_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"pcie0_axi_s_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll4,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie0_axi_s_clk = {\n+\t.halt_reg = 0x2803c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2803c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie0_axi_s_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie0_axi_s_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie0_axi_s_bridge_clk = {\n+\t.halt_reg = 0x28040,\n+\t.clkr = {\n+\t\t.enable_reg = 0x28040,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie0_axi_s_bridge_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie0_axi_s_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_snoc_pcie0_1lane_s_clk = {\n+\t.halt_reg = 0x2e048,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2e048,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_snoc_pcie0_1lane_s_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie0_axi_s_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_rcg2 pcie1_axi_s_clk_src = {\n+\t.cmd_rcgr = 0x29020,\n+\t.freq_tbl = ftbl_pcie0_axi_m_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll4_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"pcie1_axi_s_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll4,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie1_axi_s_clk = {\n+\t.halt_reg = 0x2903c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2903c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie1_axi_s_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie1_axi_s_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie1_axi_s_bridge_clk = {\n+\t.halt_reg = 0x29040,\n+\t.clkr = {\n+\t\t.enable_reg = 0x29040,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie1_axi_s_bridge_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie1_axi_s_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_snoc_pcie1_1lane_s_clk = {\n+\t.halt_reg = 0x2e04c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2e04c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_snoc_pcie1_1lane_s_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie1_axi_s_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_rcg2 pcie2_axi_s_clk_src = {\n+\t.cmd_rcgr = 0x2a020,\n+\t.freq_tbl = ftbl_pcie0_axi_m_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll4_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"pcie2_axi_s_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll4,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie2_axi_s_clk = {\n+\t.halt_reg = 0x2a03c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2a03c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie2_axi_s_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie2_axi_s_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie2_axi_s_bridge_clk = {\n+\t.halt_reg = 0x2a040,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2a040,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie2_axi_s_bridge_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie2_axi_s_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_snoc_pcie2_2lane_s_clk = {\n+\t.halt_reg = 0x2e050,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2e050,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_snoc_pcie2_2lane_s_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie2_axi_s_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_rcg2 pcie3_axi_s_clk_src = {\n+\t.cmd_rcgr = 0x2b020,\n+\t.freq_tbl = ftbl_pcie0_axi_m_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll4_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"pcie3_axi_s_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll4,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie3_axi_s_clk = {\n+\t.halt_reg = 0x2b03c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2b03c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie3_axi_s_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie3_axi_s_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie3_axi_s_bridge_clk = {\n+\t.halt_reg = 0x2b040,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2b040,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie3_axi_s_bridge_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie3_axi_s_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_snoc_pcie3_2lane_s_clk = {\n+\t.halt_reg = 0x2e054,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2e054,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_snoc_pcie3_2lane_s_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie3_axi_s_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_regmap_phy_mux pcie0_pipe_clk_src = {\n+\t.reg = 0x28064,\n+\t.clkr = {\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"pcie0_pipe_clk_src\",\n+\t\t\t.parent_data = &(const struct clk_parent_data) {\n+\t\t\t\t.index = DT_PCIE30_PHY0_PIPE_CLK,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.ops = &clk_regmap_phy_mux_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_regmap_phy_mux pcie1_pipe_clk_src = {\n+\t.reg = 0x29064,\n+\t.clkr = {\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"pcie1_pipe_clk_src\",\n+\t\t\t.parent_data = &(const struct clk_parent_data) {\n+\t\t\t\t.index = DT_PCIE30_PHY1_PIPE_CLK,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.ops = &clk_regmap_phy_mux_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_regmap_phy_mux pcie2_pipe_clk_src = {\n+\t.reg = 0x2a064,\n+\t.clkr = {\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"pcie2_pipe_clk_src\",\n+\t\t\t.parent_data = &(const struct clk_parent_data) {\n+\t\t\t\t.index = DT_PCIE30_PHY2_PIPE_CLK,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.ops = &clk_regmap_phy_mux_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_regmap_phy_mux pcie3_pipe_clk_src = {\n+\t.reg = 0x2b064,\n+\t.clkr = {\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"pcie3_pipe_clk_src\",\n+\t\t\t.parent_data = &(const struct clk_parent_data) {\n+\t\t\t\t.index = DT_PCIE30_PHY3_PIPE_CLK,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.ops = &clk_regmap_phy_mux_ops,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_pcie_rchng_clk_src[] = {\n+\tF(24000000, P_XO, 1, 0, 0),\n+\tF(100000000, P_GPLL0, 8, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 pcie0_rchng_clk_src = {\n+\t.cmd_rcgr = 0x28028,\n+\t.freq_tbl = ftbl_pcie_rchng_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"pcie0_rchng_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie0_rchng_clk = {\n+\t.halt_reg = 0x28028,\n+\t.clkr = {\n+\t\t.enable_reg = 0x28028,\n+\t\t.enable_mask = BIT(1),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie0_rchng_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie0_rchng_clk_src.clkr.hw\n+\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_rcg2 pcie1_rchng_clk_src = {\n+\t.cmd_rcgr = 0x29028,\n+\t.freq_tbl = ftbl_pcie_rchng_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"pcie1_rchng_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie1_rchng_clk = {\n+\t.halt_reg = 0x29028,\n+\t.clkr = {\n+\t\t.enable_reg = 0x29028,\n+\t\t.enable_mask = BIT(1),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie1_rchng_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie1_rchng_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_rcg2 pcie2_rchng_clk_src = {\n+\t.cmd_rcgr = 0x2a028,\n+\t.freq_tbl = ftbl_pcie_rchng_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"pcie2_rchng_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie2_rchng_clk = {\n+\t.halt_reg = 0x2a028,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2a028,\n+\t\t.enable_mask = BIT(1),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie2_rchng_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie2_rchng_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_rcg2 pcie3_rchng_clk_src = {\n+\t.cmd_rcgr = 0x2b028,\n+\t.freq_tbl = ftbl_pcie_rchng_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"pcie3_rchng_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie3_rchng_clk = {\n+\t.halt_reg = 0x2b028,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2b028,\n+\t\t.enable_mask = BIT(1),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie3_rchng_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie3_rchng_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_pcie_aux_clk_src[] = {\n+\tF(20000000, P_GPLL0, 10, 1, 4),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 pcie_aux_clk_src = {\n+\t.cmd_rcgr = 0x28004,\n+\t.freq_tbl = ftbl_pcie_aux_clk_src,\n+\t.mnd_width = 16,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"pcie_aux_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_aux_core_pi_sleep_clk),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie0_aux_clk = {\n+\t.halt_reg = 0x28034,\n+\t.clkr = {\n+\t\t.enable_reg = 0x28034,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie0_aux_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie_aux_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie1_aux_clk = {\n+\t.halt_reg = 0x29034,\n+\t.clkr = {\n+\t\t.enable_reg = 0x29034,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie1_aux_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie_aux_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie2_aux_clk = {\n+\t.halt_reg = 0x2a034,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2a034,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie2_aux_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie_aux_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie3_aux_clk = {\n+\t.halt_reg = 0x2b034,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2b034,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie3_aux_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcie_aux_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_usb_aux_clk_src[] = {\n+\tF(24000000, P_XO, 1, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 usb0_aux_clk_src = {\n+\t.cmd_rcgr = 0x2c018,\n+\t.freq_tbl = ftbl_usb_aux_clk_src,\n+\t.mnd_width = 16,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_core_pi_sleep_clk_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"usb0_aux_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_core_pi_sleep_clk,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_core_pi_sleep_clk),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_usb0_aux_clk = {\n+\t.halt_reg = 0x2c048,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2c048,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_usb0_aux_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&usb0_aux_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_usb0_master_clk_src[] = {\n+\tF(100000000, P_GPLL0, 8, 0, 0),\n+\tF(200000000, P_GPLL0, 4, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 usb0_master_clk_src = {\n+\t.cmd_rcgr = 0x2c004,\n+\t.freq_tbl = ftbl_usb0_master_clk_src,\n+\t.mnd_width = 8,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_out_main_div2_gpll0_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"usb0_master_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_out_main_div2_gpll0,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_out_main_div2_gpll0),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_usb0_master_clk = {\n+\t.halt_reg = 0x2c044,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2c044,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_usb0_master_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&usb0_master_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_snoc_usb_clk = {\n+\t.halt_reg = 0x2e058,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2e058,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_snoc_usb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&usb0_master_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_anoc_usb_axi_clk = {\n+\t.halt_reg = 0x2e084,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2e084,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_anoc_usb_axi_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&usb0_master_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_usb0_mock_utmi_clk_src[] = {\n+\tF(24000000, P_XO, 1, 0, 0),\n+\tF(60000000, P_GPLL4, 10, 1, 2),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 usb0_mock_utmi_clk_src = {\n+\t.cmd_rcgr = 0x2c02c,\n+\t.freq_tbl = ftbl_usb0_mock_utmi_clk_src,\n+\t.mnd_width = 8,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll4_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"usb0_mock_utmi_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll4_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_regmap_div usb0_mock_utmi_div_clk_src = {\n+\t.reg = 0x2c040,\n+\t.shift = 0,\n+\t.width = 2,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"usb0_mock_utmi_div_clk_src\",\n+\t\t.parent_data = &(const struct clk_parent_data) {\n+\t\t\t.hw = &usb0_mock_utmi_clk_src.clkr.hw,\n+\t\t},\n+\t\t.num_parents = 1,\n+\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t.ops = &clk_regmap_div_ro_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_usb0_mock_utmi_clk = {\n+\t.halt_reg = 0x2c04c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2c04c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_usb0_mock_utmi_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&usb0_mock_utmi_div_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_regmap_mux usb0_pipe_clk_src = {\n+\t.reg = 0x2C074,\n+\t.shift = 8,\n+\t.width = 2,\n+\t.parent_map = gcc_usb3phy_0_cc_pipe_clk_xo_map,\n+\t.clkr = {\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"usb0_pipe_clk_src\",\n+\t\t\t.parent_data = gcc_usb3phy_0_cc_pipe_clk_xo,\n+\t\t\t.num_parents = ARRAY_SIZE(gcc_usb3phy_0_cc_pipe_clk_xo),\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_regmap_mux_closest_ops,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_sdcc_apps_clk_src[] = {\n+\tF(144000, P_XO, 16, 12, 125),\n+\tF(400000, P_XO, 12, 1, 5),\n+\tF(24000000, P_GPLL2, 12, 1, 4),\n+\tF(48000000, P_GPLL2, 12, 1, 2),\n+\tF(96000000, P_GPLL2, 12, 0, 0),\n+\tF(177777778, P_GPLL0, 4.5, 0, 0),\n+\tF(192000000, P_GPLL2, 6, 0, 0),\n+\tF(384000000, P_GPLL2, 3, 0, 0),\n+\tF(400000000, P_GPLL0, 2, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 sdcc1_apps_clk_src = {\n+\t.cmd_rcgr = 0x33004,\n+\t.freq_tbl = ftbl_sdcc_apps_clk_src,\n+\t.mnd_width = 8,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll2_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"sdcc1_apps_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll2_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_floor_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_sdcc1_apps_clk = {\n+\t.halt_reg = 0x3302c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x3302c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_sdcc1_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&sdcc1_apps_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_sdcc_ice_core_clk_src[] = {\n+\tF(150000000, P_GPLL4, 8, 0, 0),\n+\tF(300000000, P_GPLL4, 4, 0, 0),\n+};\n+\n+static struct clk_rcg2 sdcc1_ice_core_clk_src = {\n+\t.cmd_rcgr = 0x33018,\n+\t.freq_tbl = ftbl_sdcc_ice_core_clk_src,\n+\t.mnd_width = 8,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll4_gpll0_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"sdcc1_ice_core_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll4_gpll0_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_gpll0_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_sdcc1_ice_core_clk = {\n+\t.halt_reg = 0x33030,\n+\t.clkr = {\n+\t\t.enable_reg = 0x33030,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_sdcc1_ice_core_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&sdcc1_ice_core_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_pcnoc_bfdcd_clk_src[] = {\n+\tF(24000000, P_XO, 1, 0, 0),\n+\tF(50000000, P_GPLL0, 16, 0, 0),\n+\tF(80000000, P_GPLL0, 10, 0, 0),\n+\tF(100000000, P_GPLL0, 8, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 pcnoc_bfdcd_clk_src = {\n+\t.cmd_rcgr = 0x31004,\n+\t.freq_tbl = ftbl_pcnoc_bfdcd_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"pcnoc_bfdcd_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),\n+\t\t.flags = CLK_IS_CRITICAL,\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_nsscfg_clk = {\n+\t.halt_reg = 0x1702c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x1702c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_nsscfg_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_bfdcd_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_nssnoc_nsscc_clk = {\n+\t.halt_reg = 0x17030,\n+\t.clkr = {\n+\t\t.enable_reg = 0x17030,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_nssnoc_nsscc_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_bfdcd_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_nsscc_clk = {\n+\t.halt_reg = 0x17034,\n+\t.clkr = {\n+\t\t.enable_reg = 0x17034,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_nsscc_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_bfdcd_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_nssnoc_pcnoc_1_clk = {\n+\t.halt_reg = 0x17080,\n+\t.clkr = {\n+\t\t.enable_reg = 0x17080,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_nssnoc_pcnoc_1_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_bfdcd_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_qdss_dap_ahb_clk = {\n+\t.halt_reg = 0x2d064,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2d064,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_qdss_dap_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_bfdcd_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_qdss_cfg_ahb_clk = {\n+\t.halt_reg = 0x2d068,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2d068,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_qdss_cfg_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_bfdcd_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_qpic_ahb_clk = {\n+\t.halt_reg = 0x32010,\n+\t.clkr = {\n+\t\t.enable_reg = 0x32010,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_qpic_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_bfdcd_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_qpic_clk = {\n+\t.halt_reg = 0x32014,\n+\t.clkr = {\n+\t\t.enable_reg = 0x32014,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_qpic_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_bfdcd_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_ahb_clk = {\n+\t.halt_reg = 0x01004,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x0b004,\n+\t\t.enable_mask = BIT(4),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_bfdcd_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_mdio_ahb_clk = {\n+\t.halt_reg = 0x17040,\n+\t.clkr = {\n+\t\t.enable_reg = 0x17040,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_mdio_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_bfdcd_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_prng_ahb_clk = {\n+\t.halt_reg = 0x13024,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x0b004,\n+\t\t.enable_mask = BIT(10),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_prng_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_bfdcd_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_uniphy0_ahb_clk = {\n+\t.halt_reg = 0x1704c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x1704c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_uniphy0_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_bfdcd_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_uniphy1_ahb_clk = {\n+\t.halt_reg = 0x1705c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x1705c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_uniphy1_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_bfdcd_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_uniphy2_ahb_clk = {\n+\t.halt_reg = 0x1706c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x1706c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_uniphy2_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_bfdcd_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_cmn_12gpll_ahb_clk = {\n+\t.halt_reg = 0x3a004,\n+\t.clkr = {\n+\t\t.enable_reg = 0x3a004,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_cmn_12gpll_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_bfdcd_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_cmn_12gpll_apu_clk = {\n+\t.halt_reg = 0x3a00c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x3a00c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_cmn_12gpll_apu_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_bfdcd_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie0_ahb_clk = {\n+\t.halt_reg = 0x28030,\n+\t.clkr = {\n+\t\t.enable_reg = 0x28030,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie0_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_bfdcd_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie1_ahb_clk = {\n+\t.halt_reg = 0x29030,\n+\t.clkr = {\n+\t\t.enable_reg = 0x29030,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie1_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_bfdcd_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie2_ahb_clk = {\n+\t.halt_reg = 0x2a030,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2a030,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie2_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_bfdcd_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie3_ahb_clk = {\n+\t.halt_reg = 0x2b030,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2b030,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie3_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_bfdcd_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {\n+\t.halt_reg = 0x2c05c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2c05c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_usb0_phy_cfg_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_bfdcd_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_sdcc1_ahb_clk = {\n+\t.halt_reg = 0x33034,\n+\t.clkr = {\n+\t\t.enable_reg = 0x33034,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_sdcc1_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&pcnoc_bfdcd_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_system_noc_bfdcd_clk_src[] = {\n+\tF(24000000, P_XO, 1, 0, 0),\n+\tF(133333333, P_GPLL0, 6, 0, 0),\n+\tF(200000000, P_GPLL0, 4, 0, 0),\n+\tF(342850000, P_GPLL4, 3.5, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 system_noc_bfdcd_clk_src = {\n+\t.cmd_rcgr = 0x2e004,\n+\t.freq_tbl = ftbl_system_noc_bfdcd_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll4_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"system_noc_bfdcd_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll4,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4),\n+\t\t.flags = CLK_IS_CRITICAL,\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_q6ss_boot_clk = {\n+\t.halt_reg = 0x25080,\n+\t.halt_check = BRANCH_HALT_SKIP,\n+\t.clkr = {\n+\t\t.enable_reg = 0x25080,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_q6ss_boot_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&system_noc_bfdcd_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_nssnoc_snoc_clk = {\n+\t.halt_reg = 0x17028,\n+\t.clkr = {\n+\t\t.enable_reg = 0x17028,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_nssnoc_snoc_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&system_noc_bfdcd_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_nssnoc_snoc_1_clk = {\n+\t.halt_reg = 0x1707c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x1707c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_nssnoc_snoc_1_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&system_noc_bfdcd_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_qdss_etr_usb_clk = {\n+\t.halt_reg = 0x2d060,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2d060,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_qdss_etr_usb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&system_noc_bfdcd_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_wcss_ahb_clk_src[] = {\n+\tF(24000000, P_XO, 1, 0, 0),\n+\tF(133333333, P_GPLL0, 6, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 wcss_ahb_clk_src = {\n+\t.cmd_rcgr = 0x25030,\n+\t.freq_tbl = ftbl_wcss_ahb_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"wcss_ahb_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_q6_ahb_clk = {\n+\t.halt_reg = 0x25014,\n+\t.clkr = {\n+\t\t.enable_reg = 0x25014,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_q6_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&wcss_ahb_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_q6_ahb_s_clk = {\n+\t.halt_reg = 0x25018,\n+\t.clkr = {\n+\t\t.enable_reg = 0x25018,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_q6_ahb_s_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&wcss_ahb_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_wcss_ecahb_clk = {\n+\t.halt_reg = 0x25058,\n+\t.clkr = {\n+\t\t.enable_reg = 0x25058,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_wcss_ecahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&wcss_ahb_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_wcss_acmt_clk = {\n+\t.halt_reg = 0x2505c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2505c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_wcss_acmt_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&wcss_ahb_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_sys_noc_wcss_ahb_clk = {\n+\t.halt_reg = 0x2e030,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2e030,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_sys_noc_wcss_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&wcss_ahb_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_wcss_axi_m_clk_src[] = {\n+\tF(24000000, P_XO, 1, 0, 0),\n+\tF(133333333, P_GPLL0, 6, 0, 0),\n+\tF(266666667, P_GPLL0, 3, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 wcss_axi_m_clk_src = {\n+\t.cmd_rcgr = 0x25078,\n+\t.freq_tbl = ftbl_wcss_axi_m_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"wcss_axi_m_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_anoc_wcss_axi_m_clk = {\n+\t.halt_reg = 0x2e0a8,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2e0a8,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_anoc_wcss_axi_m_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&wcss_axi_m_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_qdss_at_clk_src[] = {\n+\tF(240000000, P_GPLL4, 5, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 qdss_at_clk_src = {\n+\t.cmd_rcgr = 0x2d004,\n+\t.freq_tbl = ftbl_qdss_at_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"qdss_at_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_q6ss_atbm_clk = {\n+\t.halt_reg = 0x2501c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2501c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_q6ss_atbm_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_at_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = {\n+\t.halt_reg = 0x2503c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2503c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_wcss_dbg_ifc_atb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_at_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_nssnoc_atb_clk = {\n+\t.halt_reg = 0x17014,\n+\t.clkr = {\n+\t\t.enable_reg = 0x17014,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_nssnoc_atb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_at_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_qdss_at_clk = {\n+\t.halt_reg = 0x2d038,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2d038,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_qdss_at_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_at_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_sys_noc_at_clk = {\n+\t.halt_reg = 0x2e038,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2e038,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_sys_noc_at_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_at_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcnoc_at_clk = {\n+\t.halt_reg = 0x31024,\n+\t.clkr = {\n+\t\t.enable_reg = 0x31024,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcnoc_at_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_at_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_fixed_factor gcc_eud_at_div_clk_src = {\n+\t.mult = 1,\n+\t.div = 6,\n+\t.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"gcc_eud_at_div_clk_src\",\n+\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t&qdss_at_clk_src.clkr.hw\n+\t\t},\n+\t\t.num_parents = 1,\n+\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t.ops = &clk_fixed_factor_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_usb0_eud_at_clk = {\n+\t.halt_reg = 0x30004,\n+\t.clkr = {\n+\t\t.enable_reg = 0x30004,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_usb0_eud_at_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gcc_eud_at_div_clk_src.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_qdss_eud_at_clk = {\n+\t.halt_reg = 0x2d06c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2d06c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_qdss_eud_at_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gcc_eud_at_div_clk_src.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_qdss_stm_clk_src[] = {\n+\tF(24000000, P_XO, 1, 0, 0),\n+\tF(200000000, P_GPLL0, 4, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 qdss_stm_clk_src = {\n+\t.cmd_rcgr = 0x2d00c,\n+\t.freq_tbl = ftbl_qdss_stm_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_out_main_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"qdss_stm_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_out_main_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_out_main_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_qdss_stm_clk = {\n+\t.halt_reg = 0x2d03c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2d03c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_qdss_stm_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_stm_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_sys_noc_qdss_stm_axi_clk = {\n+\t.halt_reg = 0x2e034,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2e034,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_sys_noc_qdss_stm_axi_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_stm_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_qdss_traceclkin_clk_src[] = {\n+\tF(300000000, P_GPLL4, 4, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 qdss_traceclkin_clk_src = {\n+\t.cmd_rcgr = 0x2d014,\n+\t.freq_tbl = ftbl_qdss_traceclkin_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"qdss_traceclkin_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_qdss_traceclkin_clk = {\n+\t.halt_reg = 0x2d040,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2d040,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_qdss_traceclkin_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_traceclkin_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_qdss_tsctr_clk_src[] = {\n+\tF(600000000, P_GPLL4, 2, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 qdss_tsctr_clk_src = {\n+\t.cmd_rcgr = 0x2d01c,\n+\t.freq_tbl = ftbl_qdss_tsctr_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll4_gpll0_gpll0_div2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"qdss_tsctr_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll4_gpll0_gpll0_div2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll4_gpll0_gpll0_div2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_fixed_factor qdss_tsctr_div2_clk_src = {\n+\t.mult = 1,\n+\t.div = 2,\n+\t.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"qdss_tsctr_div2_clk_src\",\n+\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t&qdss_tsctr_clk_src.clkr.hw\n+\t\t},\n+\t\t.num_parents = 1,\n+\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t.ops = &clk_fixed_factor_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_q6_tsctr_1to2_clk = {\n+\t.halt_reg = 0x25020,\n+\t.clkr = {\n+\t\t.enable_reg = 0x25020,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_q6_tsctr_1to2_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_tsctr_div2_clk_src.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = {\n+\t.halt_reg = 0x25040,\n+\t.clkr = {\n+\t\t.enable_reg = 0x25040,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_wcss_dbg_ifc_nts_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_tsctr_div2_clk_src.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_qdss_tsctr_div2_clk = {\n+\t.halt_reg = 0x2d044,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2d044,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_qdss_tsctr_div2_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_tsctr_div2_clk_src.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_uniphy_sys_clk_src[] = {\n+\tF(24000000, P_XO, 1, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 uniphy_sys_clk_src = {\n+\t.cmd_rcgr = 0x17090,\n+\t.freq_tbl = ftbl_uniphy_sys_clk_src,\n+\t.mnd_width = 8,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"uniphy_sys_clk_src\",\n+\t\t.parent_data = gcc_xo_data,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_data),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 nss_ts_clk_src = {\n+\t.cmd_rcgr = 0x17088,\n+\t.freq_tbl = ftbl_uniphy_sys_clk_src,\n+\t.mnd_width = 8,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"nss_ts_clk_src\",\n+\t\t.parent_data = gcc_xo_data,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_data),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_qdss_ts_clk = {\n+\t.halt_reg = 0x2d078,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2d078,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_qdss_ts_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&nss_ts_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_fixed_factor qdss_dap_sync_clk_src = {\n+\t.mult = 1,\n+\t.div = 4,\n+\t.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"qdss_dap_sync_clk_src\",\n+\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t&qdss_tsctr_clk_src.clkr.hw\n+\t\t},\n+\t\t.num_parents = 1,\n+\t\t.ops = &clk_fixed_factor_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_qdss_tsctr_div4_clk = {\n+\t.halt_reg = 0x2d04c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2d04c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_qdss_tsctr_div4_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_dap_sync_clk_src.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_fixed_factor qdss_tsctr_div8_clk_src = {\n+\t.mult = 1,\n+\t.div = 8,\n+\t.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"qdss_tsctr_div8_clk_src\",\n+\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t&qdss_tsctr_clk_src.clkr.hw\n+\t\t},\n+\t\t.num_parents = 1,\n+\t\t.ops = &clk_fixed_factor_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_nss_ts_clk = {\n+\t.halt_reg = 0x17018,\n+\t.clkr = {\n+\t\t.enable_reg = 0x17018,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_nss_ts_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&nss_ts_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_qdss_tsctr_div8_clk = {\n+\t.halt_reg = 0x2d050,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2d050,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_qdss_tsctr_div8_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_tsctr_div8_clk_src.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_fixed_factor qdss_tsctr_div16_clk_src = {\n+\t.mult = 1,\n+\t.div = 16,\n+\t.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"qdss_tsctr_div16_clk_src\",\n+\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t&qdss_tsctr_clk_src.clkr.hw\n+\t\t},\n+\t\t.num_parents = 1,\n+\t\t.ops = &clk_fixed_factor_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_qdss_tsctr_div16_clk = {\n+\t.halt_reg = 0x2d054,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2d054,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_qdss_tsctr_div16_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_tsctr_div16_clk_src.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_q6ss_pclkdbg_clk = {\n+\t.halt_reg = 0x25024,\n+\t.clkr = {\n+\t\t.enable_reg = 0x25024,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_q6ss_pclkdbg_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_dap_sync_clk_src.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_q6ss_trig_clk = {\n+\t.halt_reg = 0x25068,\n+\t.clkr = {\n+\t\t.enable_reg = 0x25068,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_q6ss_trig_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_dap_sync_clk_src.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = {\n+\t.halt_reg = 0x25038,\n+\t.clkr = {\n+\t\t.enable_reg = 0x25038,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_wcss_dbg_ifc_apb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_dap_sync_clk_src.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_wcss_dbg_ifc_dapbus_clk = {\n+\t.halt_reg = 0x25044,\n+\t.clkr = {\n+\t\t.enable_reg = 0x25044,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_wcss_dbg_ifc_dapbus_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_dap_sync_clk_src.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_qdss_dap_clk = {\n+\t.halt_reg = 0x2d058,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2d058,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_qdss_dap_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_dap_sync_clk_src.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_qdss_apb2jtag_clk = {\n+\t.halt_reg = 0x2d05c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2d05c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_qdss_apb2jtag_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_dap_sync_clk_src.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_fixed_factor qdss_tsctr_div3_clk_src = {\n+\t.mult = 1,\n+\t.div = 3,\n+\t.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"qdss_tsctr_div3_clk_src\",\n+\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t&qdss_tsctr_clk_src.clkr.hw\n+\t\t},\n+\t\t.num_parents = 1,\n+\t\t.ops = &clk_fixed_factor_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_qdss_tsctr_div3_clk = {\n+\t.halt_reg = 0x2d048,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2d048,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_qdss_tsctr_div3_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&qdss_tsctr_div3_clk_src.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_qpic_io_macro_clk_src[] = {\n+\tF(24000000, P_XO, 1, 0, 0),\n+\tF(100000000, P_GPLL0, 8, 0, 0),\n+\tF(200000000, P_GPLL0, 4, 0, 0),\n+\tF(320000000, P_GPLL0, 2.5, 0, 0),\n+\tF(400000000, P_GPLL0, 2, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 qpic_io_macro_clk_src = {\n+\t.cmd_rcgr = 0x32004,\n+\t.freq_tbl = ftbl_qpic_io_macro_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"qpic_io_macro_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_qpic_io_macro_clk = {\n+\t.halt_reg = 0x3200c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x3200c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data){\n+\t\t\t.name = \"gcc_qpic_io_macro_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]){\n+\t\t\t\t&qpic_io_macro_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_q6_axi_clk_src[] = {\n+\tF(533333333, P_GPLL0, 1.5, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 q6_axi_clk_src = {\n+\t.cmd_rcgr = 0x25004,\n+\t.freq_tbl = ftbl_q6_axi_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll2_gpll4_pi_sleep_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"q6_axi_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll2_gpll4_pi_sleep,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll2_gpll4_pi_sleep),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_q6_axim_clk = {\n+\t.halt_reg = 0x2500c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2500c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_q6_axim_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&q6_axi_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_wcss_q6_tbu_clk = {\n+\t.halt_reg = 0x12050,\n+\t.halt_check = BRANCH_HALT_DELAY,\n+\t.clkr = {\n+\t\t.enable_reg = 0xb00c,\n+\t\t.enable_mask = BIT(6),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_wcss_q6_tbu_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&q6_axi_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_mem_noc_q6_axi_clk = {\n+\t.halt_reg = 0x19010,\n+\t.clkr = {\n+\t\t.enable_reg = 0x19010,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_mem_noc_q6_axi_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&q6_axi_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_q6_axim2_clk_src[] = {\n+\tF(342857143, P_GPLL4, 3.5, 0, 0),\n+\t{ }\n+};\n+\n+static const struct parent_map gcc_xo_gpll0_gpll4_bias_pll_ubinc_clk_map[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0, 1 },\n+\t{ P_GPLL4, 2 },\n+\t{ P_BIAS_PLL_UBI_NC_CLK, 4 },\n+};\n+\n+static struct clk_rcg2 q6_axim2_clk_src = {\n+\t.cmd_rcgr = 0x25028,\n+\t.freq_tbl = ftbl_q6_axim2_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll4_bias_pll_ubinc_clk_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"q6_axim2_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll4_bias_pll_ubi_nc_clk),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_nssnoc_memnoc_bfdcd_clk_src[] = {\n+\tF(533333333, P_GPLL0, 1.5, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 nssnoc_memnoc_bfdcd_clk_src = {\n+\t.cmd_rcgr = 0x17004,\n+\t.freq_tbl = ftbl_nssnoc_memnoc_bfdcd_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_aux_gpll2_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"nssnoc_memnoc_bfdcd_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_aux_gpll2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_aux_gpll2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_nssnoc_memnoc_clk = {\n+\t.halt_reg = 0x17024,\n+\t.clkr = {\n+\t\t.enable_reg = 0x17024,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_nssnoc_memnoc_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&nssnoc_memnoc_bfdcd_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_nssnoc_mem_noc_1_clk = {\n+\t.halt_reg = 0x17084,\n+\t.clkr = {\n+\t\t.enable_reg = 0x17084,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_nssnoc_mem_noc_1_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&nssnoc_memnoc_bfdcd_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_nss_tbu_clk = {\n+\t.halt_reg = 0x12040,\n+\t.clkr = {\n+\t\t.enable_reg = 0xb00c,\n+\t\t.enable_mask = BIT(4),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_nss_tbu_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&nssnoc_memnoc_bfdcd_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_mem_noc_nssnoc_clk = {\n+\t.halt_reg = 0x19014,\n+\t.clkr = {\n+\t\t.enable_reg = 0x19014,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_mem_noc_nssnoc_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&nssnoc_memnoc_bfdcd_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_lpass_axim_clk_src[] = {\n+\tF(133333333, P_GPLL0, 6, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 lpass_axim_clk_src = {\n+\t.cmd_rcgr = 0x2700c,\n+\t.freq_tbl = ftbl_lpass_axim_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"lpass_axim_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 lpass_sway_clk_src = {\n+\t.cmd_rcgr = 0x27004,\n+\t.freq_tbl = ftbl_lpass_axim_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"lpass_sway_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_adss_pwm_clk_src[] = {\n+\tF(24000000, P_XO, 1, 0, 0),\n+\tF(100000000, P_GPLL0, 8, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 adss_pwm_clk_src = {\n+\t.cmd_rcgr = 0x1c004,\n+\t.freq_tbl = ftbl_adss_pwm_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"adss_pwm_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_adss_pwm_clk = {\n+\t.halt_reg = 0x1c00c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x1c00c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_adss_pwm_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&adss_pwm_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_gp1_clk_src[] = {\n+\tF(24000000, P_XO, 1, 0, 0),\n+\tF(200000000, P_GPLL0, 4, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 gp1_clk_src = {\n+\t.cmd_rcgr = 0x8004,\n+\t.freq_tbl = ftbl_gp1_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"gp1_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_sleep_clk,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 gp2_clk_src = {\n+\t.cmd_rcgr = 0x9004,\n+\t.freq_tbl = ftbl_gp1_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"gp2_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_sleep_clk,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 gp3_clk_src = {\n+\t.cmd_rcgr = 0xa004,\n+\t.freq_tbl = ftbl_gp1_clk_src,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_xo_gpll0_gpll0_sleep_clk_map,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"gp3_clk_src\",\n+\t\t.parent_data = gcc_xo_gpll0_gpll0_sleep_clk,\n+\t\t.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_sleep_clk),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_xo_clk_src = {\n+\t.halt_reg = 0x34004,\n+\t.clkr = {\n+\t\t.enable_reg = 0x34004,\n+\t\t.enable_mask = BIT(1),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_xo_clk_src\",\n+\t\t\t.parent_data = gcc_xo_data,\n+\t\t\t.num_parents = ARRAY_SIZE(gcc_xo_data),\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_nssnoc_xo_dcd_clk = {\n+\t.halt_reg = 0x17074,\n+\t.clkr = {\n+\t\t.enable_reg = 0x17074,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_nssnoc_xo_dcd_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gcc_xo_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_xo_clk = {\n+\t.halt_reg = 0x34018,\n+\t.clkr = {\n+\t\t.enable_reg = 0x34018,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_xo_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gcc_xo_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_uniphy0_sys_clk = {\n+\t.halt_reg = 0x17048,\n+\t.clkr = {\n+\t\t.enable_reg = 0x17048,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_uniphy0_sys_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&uniphy_sys_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_uniphy1_sys_clk = {\n+\t.halt_reg = 0x17058,\n+\t.clkr = {\n+\t\t.enable_reg = 0x17058,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_uniphy1_sys_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&uniphy_sys_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_uniphy2_sys_clk = {\n+\t.halt_reg = 0x17068,\n+\t.clkr = {\n+\t\t.enable_reg = 0x17068,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_uniphy2_sys_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&uniphy_sys_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_cmn_12gpll_sys_clk = {\n+\t.halt_reg = 0x3a008,\n+\t.clkr = {\n+\t\t.enable_reg = 0x3a008,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_cmn_12gpll_sys_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&uniphy_sys_clk_src.clkr.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_fixed_factor gcc_xo_div4_clk_src = {\n+\t.mult = 1,\n+\t.div = 4,\n+\t.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"gcc_xo_div4_clk_src\",\n+\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t&gcc_xo_clk_src.clkr.hw\n+\t\t},\n+\t\t.num_parents = 1,\n+\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t.ops = &clk_fixed_factor_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {\n+\t.halt_reg = 0x1701c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x1701c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_nssnoc_qosgen_ref_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gcc_xo_div4_clk_src.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_nssnoc_timeout_ref_clk = {\n+\t.halt_reg = 0x17020,\n+\t.clkr = {\n+\t\t.enable_reg = 0x17020,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_nssnoc_timeout_ref_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gcc_xo_div4_clk_src.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_xo_div4_clk = {\n+\t.halt_reg = 0x3401c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x3401c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_xo_div4_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gcc_xo_div4_clk_src.hw\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_hw *gcc_ipq9574_hws[] = {\n+\t&gpll0_out_main_div2.hw,\n+\t&gcc_xo_div4_clk_src.hw,\n+\t&qdss_dap_sync_clk_src.hw,\n+\t&qdss_tsctr_div2_clk_src.hw,\n+\t&qdss_tsctr_div8_clk_src.hw,\n+\t&qdss_tsctr_div16_clk_src.hw,\n+\t&qdss_tsctr_div3_clk_src.hw,\n+\t&gcc_eud_at_div_clk_src.hw,\n+};\n+\n+static struct clk_regmap *gcc_ipq9574_clks[] = {\n+\t[GPLL0_MAIN] = &gpll0_main.clkr,\n+\t[GPLL0] = &gpll0.clkr,\n+\t[GPLL4_MAIN] = &gpll4_main.clkr,\n+\t[GPLL4] = &gpll4.clkr,\n+\t[GPLL2_MAIN] = &gpll2_main.clkr,\n+\t[GPLL2] = &gpll2.clkr,\n+\t[GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,\n+\t[APSS_AHB_CLK_SRC] = &apss_ahb_clk_src.clkr,\n+\t[APSS_AXI_CLK_SRC] = &apss_axi_clk_src.clkr,\n+\t[BLSP1_QUP1_I2C_APPS_CLK_SRC] = &blsp1_qup1_i2c_apps_clk_src.clkr,\n+\t[BLSP1_QUP1_SPI_APPS_CLK_SRC] = &blsp1_qup1_spi_apps_clk_src.clkr,\n+\t[BLSP1_QUP2_I2C_APPS_CLK_SRC] = &blsp1_qup2_i2c_apps_clk_src.clkr,\n+\t[BLSP1_QUP2_SPI_APPS_CLK_SRC] = &blsp1_qup2_spi_apps_clk_src.clkr,\n+\t[BLSP1_QUP3_I2C_APPS_CLK_SRC] = &blsp1_qup3_i2c_apps_clk_src.clkr,\n+\t[BLSP1_QUP3_SPI_APPS_CLK_SRC] = &blsp1_qup3_spi_apps_clk_src.clkr,\n+\t[BLSP1_QUP4_I2C_APPS_CLK_SRC] = &blsp1_qup4_i2c_apps_clk_src.clkr,\n+\t[BLSP1_QUP4_SPI_APPS_CLK_SRC] = &blsp1_qup4_spi_apps_clk_src.clkr,\n+\t[BLSP1_QUP5_I2C_APPS_CLK_SRC] = &blsp1_qup5_i2c_apps_clk_src.clkr,\n+\t[BLSP1_QUP5_SPI_APPS_CLK_SRC] = &blsp1_qup5_spi_apps_clk_src.clkr,\n+\t[BLSP1_QUP6_I2C_APPS_CLK_SRC] = &blsp1_qup6_i2c_apps_clk_src.clkr,\n+\t[BLSP1_QUP6_SPI_APPS_CLK_SRC] = &blsp1_qup6_spi_apps_clk_src.clkr,\n+\t[BLSP1_UART1_APPS_CLK_SRC] = &blsp1_uart1_apps_clk_src.clkr,\n+\t[BLSP1_UART2_APPS_CLK_SRC] = &blsp1_uart2_apps_clk_src.clkr,\n+\t[BLSP1_UART3_APPS_CLK_SRC] = &blsp1_uart3_apps_clk_src.clkr,\n+\t[BLSP1_UART4_APPS_CLK_SRC] = &blsp1_uart4_apps_clk_src.clkr,\n+\t[BLSP1_UART5_APPS_CLK_SRC] = &blsp1_uart5_apps_clk_src.clkr,\n+\t[BLSP1_UART6_APPS_CLK_SRC] = &blsp1_uart6_apps_clk_src.clkr,\n+\t[GCC_APSS_AHB_CLK] = &gcc_apss_ahb_clk.clkr,\n+\t[GCC_APSS_AXI_CLK] = &gcc_apss_axi_clk.clkr,\n+\t[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,\n+\t[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,\n+\t[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,\n+\t[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,\n+\t[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,\n+\t[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,\n+\t[GCC_BLSP1_QUP4_I2C_APPS_CLK] = &gcc_blsp1_qup4_i2c_apps_clk.clkr,\n+\t[GCC_BLSP1_QUP4_SPI_APPS_CLK] = &gcc_blsp1_qup4_spi_apps_clk.clkr,\n+\t[GCC_BLSP1_QUP5_I2C_APPS_CLK] = &gcc_blsp1_qup5_i2c_apps_clk.clkr,\n+\t[GCC_BLSP1_QUP5_SPI_APPS_CLK] = &gcc_blsp1_qup5_spi_apps_clk.clkr,\n+\t[GCC_BLSP1_QUP6_I2C_APPS_CLK] = &gcc_blsp1_qup6_i2c_apps_clk.clkr,\n+\t[GCC_BLSP1_QUP6_SPI_APPS_CLK] = &gcc_blsp1_qup6_spi_apps_clk.clkr,\n+\t[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,\n+\t[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,\n+\t[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,\n+\t[GCC_BLSP1_UART4_APPS_CLK] = &gcc_blsp1_uart4_apps_clk.clkr,\n+\t[GCC_BLSP1_UART5_APPS_CLK] = &gcc_blsp1_uart5_apps_clk.clkr,\n+\t[GCC_BLSP1_UART6_APPS_CLK] = &gcc_blsp1_uart6_apps_clk.clkr,\n+\t[PCIE0_AXI_M_CLK_SRC] = &pcie0_axi_m_clk_src.clkr,\n+\t[GCC_PCIE0_AXI_M_CLK] = &gcc_pcie0_axi_m_clk.clkr,\n+\t[PCIE1_AXI_M_CLK_SRC] = &pcie1_axi_m_clk_src.clkr,\n+\t[GCC_PCIE1_AXI_M_CLK] = &gcc_pcie1_axi_m_clk.clkr,\n+\t[PCIE2_AXI_M_CLK_SRC] = &pcie2_axi_m_clk_src.clkr,\n+\t[GCC_PCIE2_AXI_M_CLK] = &gcc_pcie2_axi_m_clk.clkr,\n+\t[PCIE3_AXI_M_CLK_SRC] = &pcie3_axi_m_clk_src.clkr,\n+\t[GCC_PCIE3_AXI_M_CLK] = &gcc_pcie3_axi_m_clk.clkr,\n+\t[PCIE0_AXI_S_CLK_SRC] = &pcie0_axi_s_clk_src.clkr,\n+\t[GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr,\n+\t[GCC_PCIE0_AXI_S_CLK] = &gcc_pcie0_axi_s_clk.clkr,\n+\t[PCIE1_AXI_S_CLK_SRC] = &pcie1_axi_s_clk_src.clkr,\n+\t[GCC_PCIE1_AXI_S_BRIDGE_CLK] = &gcc_pcie1_axi_s_bridge_clk.clkr,\n+\t[GCC_PCIE1_AXI_S_CLK] = &gcc_pcie1_axi_s_clk.clkr,\n+\t[PCIE2_AXI_S_CLK_SRC] = &pcie2_axi_s_clk_src.clkr,\n+\t[GCC_PCIE2_AXI_S_BRIDGE_CLK] = &gcc_pcie2_axi_s_bridge_clk.clkr,\n+\t[GCC_PCIE2_AXI_S_CLK] = &gcc_pcie2_axi_s_clk.clkr,\n+\t[PCIE3_AXI_S_CLK_SRC] = &pcie3_axi_s_clk_src.clkr,\n+\t[GCC_PCIE3_AXI_S_BRIDGE_CLK] = &gcc_pcie3_axi_s_bridge_clk.clkr,\n+\t[GCC_PCIE3_AXI_S_CLK] = &gcc_pcie3_axi_s_clk.clkr,\n+\t[PCIE0_PIPE_CLK_SRC] = &pcie0_pipe_clk_src.clkr,\n+\t[PCIE1_PIPE_CLK_SRC] = &pcie1_pipe_clk_src.clkr,\n+\t[PCIE2_PIPE_CLK_SRC] = &pcie2_pipe_clk_src.clkr,\n+\t[PCIE3_PIPE_CLK_SRC] = &pcie3_pipe_clk_src.clkr,\n+\t[PCIE_AUX_CLK_SRC] = &pcie_aux_clk_src.clkr,\n+\t[GCC_PCIE0_AUX_CLK] = &gcc_pcie0_aux_clk.clkr,\n+\t[GCC_PCIE1_AUX_CLK] = &gcc_pcie1_aux_clk.clkr,\n+\t[GCC_PCIE2_AUX_CLK] = &gcc_pcie2_aux_clk.clkr,\n+\t[GCC_PCIE3_AUX_CLK] = &gcc_pcie3_aux_clk.clkr,\n+\t[PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr,\n+\t[GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr,\n+\t[PCIE1_RCHNG_CLK_SRC] = &pcie1_rchng_clk_src.clkr,\n+\t[GCC_PCIE1_RCHNG_CLK] = &gcc_pcie1_rchng_clk.clkr,\n+\t[PCIE2_RCHNG_CLK_SRC] = &pcie2_rchng_clk_src.clkr,\n+\t[GCC_PCIE2_RCHNG_CLK] = &gcc_pcie2_rchng_clk.clkr,\n+\t[PCIE3_RCHNG_CLK_SRC] = &pcie3_rchng_clk_src.clkr,\n+\t[GCC_PCIE3_RCHNG_CLK] = &gcc_pcie3_rchng_clk.clkr,\n+\t[GCC_PCIE0_AHB_CLK] = &gcc_pcie0_ahb_clk.clkr,\n+\t[GCC_PCIE1_AHB_CLK] = &gcc_pcie1_ahb_clk.clkr,\n+\t[GCC_PCIE2_AHB_CLK] = &gcc_pcie2_ahb_clk.clkr,\n+\t[GCC_PCIE3_AHB_CLK] = &gcc_pcie3_ahb_clk.clkr,\n+\t[USB0_AUX_CLK_SRC] = &usb0_aux_clk_src.clkr,\n+\t[GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,\n+\t[USB0_MASTER_CLK_SRC] = &usb0_master_clk_src.clkr,\n+\t[GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,\n+\t[GCC_SNOC_USB_CLK] = &gcc_snoc_usb_clk.clkr,\n+\t[GCC_ANOC_USB_AXI_CLK] = &gcc_anoc_usb_axi_clk.clkr,\n+\t[USB0_MOCK_UTMI_CLK_SRC] = &usb0_mock_utmi_clk_src.clkr,\n+\t[USB0_MOCK_UTMI_DIV_CLK_SRC] = &usb0_mock_utmi_div_clk_src.clkr,\n+\t[GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,\n+\t[USB0_PIPE_CLK_SRC] = &usb0_pipe_clk_src.clkr,\n+\t[GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,\n+\t[SDCC1_APPS_CLK_SRC] = &sdcc1_apps_clk_src.clkr,\n+\t[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,\n+\t[SDCC1_ICE_CORE_CLK_SRC] = &sdcc1_ice_core_clk_src.clkr,\n+\t[GCC_SDCC1_ICE_CORE_CLK] = &gcc_sdcc1_ice_core_clk.clkr,\n+\t[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,\n+\t[PCNOC_BFDCD_CLK_SRC] = &pcnoc_bfdcd_clk_src.clkr,\n+\t[GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr,\n+\t[GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr,\n+\t[GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr,\n+\t[GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr,\n+\t[GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr,\n+\t[GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr,\n+\t[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,\n+\t[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,\n+\t[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,\n+\t[GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,\n+\t[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,\n+\t[GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,\n+\t[GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,\n+\t[GCC_UNIPHY2_AHB_CLK] = &gcc_uniphy2_ahb_clk.clkr,\n+\t[GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,\n+\t[GCC_CMN_12GPLL_APU_CLK] = &gcc_cmn_12gpll_apu_clk.clkr,\n+\t[SYSTEM_NOC_BFDCD_CLK_SRC] = &system_noc_bfdcd_clk_src.clkr,\n+\t[GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,\n+\t[GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr,\n+\t[GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr,\n+\t[WCSS_AHB_CLK_SRC] = &wcss_ahb_clk_src.clkr,\n+\t[GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr,\n+\t[GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr,\n+\t[GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr,\n+\t[GCC_WCSS_ACMT_CLK] = &gcc_wcss_acmt_clk.clkr,\n+\t[GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr,\n+\t[WCSS_AXI_M_CLK_SRC] = &wcss_axi_m_clk_src.clkr,\n+\t[GCC_ANOC_WCSS_AXI_M_CLK] = &gcc_anoc_wcss_axi_m_clk.clkr,\n+\t[QDSS_AT_CLK_SRC] = &qdss_at_clk_src.clkr,\n+\t[GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr,\n+\t[GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr,\n+\t[GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr,\n+\t[GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,\n+\t[GCC_SYS_NOC_AT_CLK] = &gcc_sys_noc_at_clk.clkr,\n+\t[GCC_PCNOC_AT_CLK] = &gcc_pcnoc_at_clk.clkr,\n+\t[GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr,\n+\t[GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr,\n+\t[QDSS_STM_CLK_SRC] = &qdss_stm_clk_src.clkr,\n+\t[GCC_QDSS_STM_CLK] = &gcc_qdss_stm_clk.clkr,\n+\t[GCC_SYS_NOC_QDSS_STM_AXI_CLK] = &gcc_sys_noc_qdss_stm_axi_clk.clkr,\n+\t[QDSS_TRACECLKIN_CLK_SRC] = &qdss_traceclkin_clk_src.clkr,\n+\t[GCC_QDSS_TRACECLKIN_CLK] = &gcc_qdss_traceclkin_clk.clkr,\n+\t[QDSS_TSCTR_CLK_SRC] = &qdss_tsctr_clk_src.clkr,\n+\t[GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr,\n+\t[GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr,\n+\t[GCC_QDSS_TSCTR_DIV2_CLK] = &gcc_qdss_tsctr_div2_clk.clkr,\n+\t[GCC_QDSS_TS_CLK] = &gcc_qdss_ts_clk.clkr,\n+\t[GCC_QDSS_TSCTR_DIV4_CLK] = &gcc_qdss_tsctr_div4_clk.clkr,\n+\t[GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr,\n+\t[GCC_QDSS_TSCTR_DIV8_CLK] = &gcc_qdss_tsctr_div8_clk.clkr,\n+\t[GCC_QDSS_TSCTR_DIV16_CLK] = &gcc_qdss_tsctr_div16_clk.clkr,\n+\t[GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr,\n+\t[GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr,\n+\t[GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr,\n+\t[GCC_WCSS_DBG_IFC_DAPBUS_CLK] = &gcc_wcss_dbg_ifc_dapbus_clk.clkr,\n+\t[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,\n+\t[GCC_QDSS_APB2JTAG_CLK] = &gcc_qdss_apb2jtag_clk.clkr,\n+\t[GCC_QDSS_TSCTR_DIV3_CLK] = &gcc_qdss_tsctr_div3_clk.clkr,\n+\t[QPIC_IO_MACRO_CLK_SRC] = &qpic_io_macro_clk_src.clkr,\n+\t[GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,\n+\t[Q6_AXI_CLK_SRC] = &q6_axi_clk_src.clkr,\n+\t[GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr,\n+\t[GCC_WCSS_Q6_TBU_CLK] = &gcc_wcss_q6_tbu_clk.clkr,\n+\t[GCC_MEM_NOC_Q6_AXI_CLK] = &gcc_mem_noc_q6_axi_clk.clkr,\n+\t[Q6_AXIM2_CLK_SRC] = &q6_axim2_clk_src.clkr,\n+\t[NSSNOC_MEMNOC_BFDCD_CLK_SRC] = &nssnoc_memnoc_bfdcd_clk_src.clkr,\n+\t[GCC_NSSNOC_MEMNOC_CLK] = &gcc_nssnoc_memnoc_clk.clkr,\n+\t[GCC_NSSNOC_MEM_NOC_1_CLK] = &gcc_nssnoc_mem_noc_1_clk.clkr,\n+\t[GCC_NSS_TBU_CLK] = &gcc_nss_tbu_clk.clkr,\n+\t[GCC_MEM_NOC_NSSNOC_CLK] = &gcc_mem_noc_nssnoc_clk.clkr,\n+\t[LPASS_AXIM_CLK_SRC] = &lpass_axim_clk_src.clkr,\n+\t[LPASS_SWAY_CLK_SRC] = &lpass_sway_clk_src.clkr,\n+\t[ADSS_PWM_CLK_SRC] = &adss_pwm_clk_src.clkr,\n+\t[GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,\n+\t[GP1_CLK_SRC] = &gp1_clk_src.clkr,\n+\t[GP2_CLK_SRC] = &gp2_clk_src.clkr,\n+\t[GP3_CLK_SRC] = &gp3_clk_src.clkr,\n+\t[GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,\n+\t[GCC_NSSNOC_XO_DCD_CLK] = &gcc_nssnoc_xo_dcd_clk.clkr,\n+\t[GCC_XO_CLK] = &gcc_xo_clk.clkr,\n+\t[GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,\n+\t[GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,\n+\t[GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr,\n+\t[GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,\n+\t[GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,\n+\t[GCC_UNIPHY2_SYS_CLK] = &gcc_uniphy2_sys_clk.clkr,\n+\t[GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,\n+\t[GCC_Q6SS_BOOT_CLK] = &gcc_q6ss_boot_clk.clkr,\n+\t[UNIPHY_SYS_CLK_SRC] = &uniphy_sys_clk_src.clkr,\n+\t[NSS_TS_CLK_SRC] = &nss_ts_clk_src.clkr,\n+\t[GCC_ANOC_PCIE0_1LANE_M_CLK] = &gcc_anoc_pcie0_1lane_m_clk.clkr,\n+\t[GCC_ANOC_PCIE1_1LANE_M_CLK] = &gcc_anoc_pcie1_1lane_m_clk.clkr,\n+\t[GCC_ANOC_PCIE2_2LANE_M_CLK] = &gcc_anoc_pcie2_2lane_m_clk.clkr,\n+\t[GCC_ANOC_PCIE3_2LANE_M_CLK] = &gcc_anoc_pcie3_2lane_m_clk.clkr,\n+\t[GCC_SNOC_PCIE0_1LANE_S_CLK] = &gcc_snoc_pcie0_1lane_s_clk.clkr,\n+\t[GCC_SNOC_PCIE1_1LANE_S_CLK] = &gcc_snoc_pcie1_1lane_s_clk.clkr,\n+\t[GCC_SNOC_PCIE2_2LANE_S_CLK] = &gcc_snoc_pcie2_2lane_s_clk.clkr,\n+\t[GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr,\n+};\n+\n+static const struct qcom_reset_map gcc_ipq9574_resets[] = {\n+\t[GCC_ADSS_BCR] = { 0x1c000, 0 },\n+\t[GCC_ANOC0_TBU_BCR] = { 0x1203c, 0 },\n+\t[GCC_ANOC1_TBU_BCR] = { 0x1204c, 0 },\n+\t[GCC_ANOC_BCR] = { 0x2e074, 0 },\n+\t[GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000, 0 },\n+\t[GCC_APSS_TCU_BCR] = { 0x12014, 0 },\n+\t[GCC_BLSP1_BCR] = { 0x01000, 0 },\n+\t[GCC_BLSP1_QUP1_BCR] = { 0x02000, 0 },\n+\t[GCC_BLSP1_QUP2_BCR] = { 0x03000, 0 },\n+\t[GCC_BLSP1_QUP3_BCR] = { 0x04000, 0 },\n+\t[GCC_BLSP1_QUP4_BCR] = { 0x05000, 0 },\n+\t[GCC_BLSP1_QUP5_BCR] = { 0x06000, 0 },\n+\t[GCC_BLSP1_QUP6_BCR] = { 0x07000, 0 },\n+\t[GCC_BLSP1_UART1_BCR] = { 0x02028, 0 },\n+\t[GCC_BLSP1_UART2_BCR] = { 0x03028, 0 },\n+\t[GCC_BLSP1_UART3_BCR] = { 0x04028, 0 },\n+\t[GCC_BLSP1_UART4_BCR] = { 0x05028, 0 },\n+\t[GCC_BLSP1_UART5_BCR] = { 0x06028, 0 },\n+\t[GCC_BLSP1_UART6_BCR] = { 0x07028, 0 },\n+\t[GCC_BOOT_ROM_BCR] = { 0x13028, 0 },\n+\t[GCC_CMN_BLK_BCR] = { 0x3a000, 0 },\n+\t[GCC_CMN_BLK_AHB_ARES] = { 0x3a010, 0 },\n+\t[GCC_CMN_BLK_SYS_ARES] = { 0x3a010, 1 },\n+\t[GCC_CMN_BLK_APU_ARES] = { 0x3a010, 2 },\n+\t[GCC_DCC_BCR] = { 0x35000, 0 },\n+\t[GCC_DDRSS_BCR] = { 0x11000, 0 },\n+\t[GCC_IMEM_BCR] = { 0x0e000, 0 },\n+\t[GCC_LPASS_BCR] = { 0x27000, 0 },\n+\t[GCC_MDIO_BCR] = { 0x1703c, 0 },\n+\t[GCC_MPM_BCR] = { 0x37000, 0 },\n+\t[GCC_MSG_RAM_BCR] = { 0x26000, 0 },\n+\t[GCC_NSS_BCR] = { 0x17000, 0 },\n+\t[GCC_NSS_TBU_BCR] = { 0x12044, 0 },\n+\t[GCC_NSSNOC_MEMNOC_1_ARES] = { 0x17038, 13 },\n+\t[GCC_NSSNOC_PCNOC_1_ARES] = { 0x17038, 12 },\n+\t[GCC_NSSNOC_SNOC_1_ARES] = { 0x17038,  11 },\n+\t[GCC_NSSNOC_XO_DCD_ARES] = { 0x17038,  10 },\n+\t[GCC_NSSNOC_TS_ARES] = { 0x17038, 9 },\n+\t[GCC_NSSCC_ARES] = { 0x17038, 8 },\n+\t[GCC_NSSNOC_NSSCC_ARES] = { 0x17038, 7 },\n+\t[GCC_NSSNOC_ATB_ARES] = { 0x17038, 6 },\n+\t[GCC_NSSNOC_MEMNOC_ARES] = { 0x17038, 5 },\n+\t[GCC_NSSNOC_QOSGEN_REF_ARES] = { 0x17038, 4 },\n+\t[GCC_NSSNOC_SNOC_ARES] = { 0x17038, 3 },\n+\t[GCC_NSSNOC_TIMEOUT_REF_ARES] = { 0x17038, 2 },\n+\t[GCC_NSS_CFG_ARES] = { 0x17038, 1 },\n+\t[GCC_UBI0_DBG_ARES] = { 0x17038, 0 },\n+\t[GCC_PCIE0PHY_PHY_BCR] = { 0x2805c, 0 },\n+\t[GCC_PCIE0_AHB_ARES] = { 0x28058, 7 },\n+\t[GCC_PCIE0_AUX_ARES] = { 0x28058, 6 },\n+\t[GCC_PCIE0_AXI_M_ARES] = { 0x28058, 5 },\n+\t[GCC_PCIE0_AXI_M_STICKY_ARES] = { 0x28058, 4 },\n+\t[GCC_PCIE0_AXI_S_ARES] = { 0x28058, 3 },\n+\t[GCC_PCIE0_AXI_S_STICKY_ARES] = { 0x28058, 2 },\n+\t[GCC_PCIE0_CORE_STICKY_ARES] = { 0x28058, 1 },\n+\t[GCC_PCIE0_PIPE_ARES] = { 0x28058, 0 },\n+\t[GCC_PCIE1_AHB_ARES] = { 0x29058, 7 },\n+\t[GCC_PCIE1_AUX_ARES] = { 0x29058, 6 },\n+\t[GCC_PCIE1_AXI_M_ARES] = { 0x29058, 5 },\n+\t[GCC_PCIE1_AXI_M_STICKY_ARES] = { 0x29058, 4 },\n+\t[GCC_PCIE1_AXI_S_ARES] = { 0x29058, 3 },\n+\t[GCC_PCIE1_AXI_S_STICKY_ARES] = { 0x29058, 2 },\n+\t[GCC_PCIE1_CORE_STICKY_ARES] = { 0x29058, 1 },\n+\t[GCC_PCIE1_PIPE_ARES] = { 0x29058, 0 },\n+\t[GCC_PCIE2_AHB_ARES] = { 0x2a058, 7 },\n+\t[GCC_PCIE2_AUX_ARES] = { 0x2a058, 6 },\n+\t[GCC_PCIE2_AXI_M_ARES] = { 0x2a058, 5 },\n+\t[GCC_PCIE2_AXI_M_STICKY_ARES] = { 0x2a058, 4 },\n+\t[GCC_PCIE2_AXI_S_ARES] = { 0x2a058, 3 },\n+\t[GCC_PCIE2_AXI_S_STICKY_ARES] = { 0x2a058, 2 },\n+\t[GCC_PCIE2_CORE_STICKY_ARES] = { 0x2a058, 1 },\n+\t[GCC_PCIE2_PIPE_ARES] = { 0x2a058, 0 },\n+\t[GCC_PCIE3_AHB_ARES] = { 0x2b058, 7 },\n+\t[GCC_PCIE3_AUX_ARES] = { 0x2b058, 6 },\n+\t[GCC_PCIE3_AXI_M_ARES] = { 0x2b058, 5 },\n+\t[GCC_PCIE3_AXI_M_STICKY_ARES] = { 0x2b058, 4 },\n+\t[GCC_PCIE3_AXI_S_ARES] = { 0x2b058, 3 },\n+\t[GCC_PCIE3_AXI_S_STICKY_ARES] = { 0x2b058, 2 },\n+\t[GCC_PCIE3_CORE_STICKY_ARES] = { 0x2b058, 1 },\n+\t[GCC_PCIE3_PIPE_ARES] = { 0x2b058, 0 },\n+\t[GCC_PCIE0_BCR] = { 0x28000, 0 },\n+\t[GCC_PCIE0_LINK_DOWN_BCR] = { 0x28054, 0 },\n+\t[GCC_PCIE0_PHY_BCR] = { 0x28060, 0 },\n+\t[GCC_PCIE1_BCR] = { 0x29000, 0 },\n+\t[GCC_PCIE1_LINK_DOWN_BCR] = { 0x29054, 0 },\n+\t[GCC_PCIE1_PHY_BCR] = { 0x29060, 0 },\n+\t[GCC_PCIE1PHY_PHY_BCR] = { 0x2905c, 0 },\n+\t[GCC_PCIE2_BCR] = { 0x2a000, 0 },\n+\t[GCC_PCIE2_LINK_DOWN_BCR] = { 0x2a054, 0 },\n+\t[GCC_PCIE2_PHY_BCR] = { 0x2a060, 0 },\n+\t[GCC_PCIE2PHY_PHY_BCR] = { 0x2a05c, 0 },\n+\t[GCC_PCIE3_BCR] = { 0x2b000, 0 },\n+\t[GCC_PCIE3_LINK_DOWN_BCR] = { 0x2b054, 0 },\n+\t[GCC_PCIE3PHY_PHY_BCR] = { 0x2b05c, 0 },\n+\t[GCC_PCIE3_PHY_BCR] = { 0x2b060, 0 },\n+\t[GCC_PCNOC_BCR] = { 0x31000, 0 },\n+\t[GCC_PCNOC_BUS_TIMEOUT0_BCR] = { 0x31030, 0 },\n+\t[GCC_PCNOC_BUS_TIMEOUT1_BCR] = { 0x31038, 0 },\n+\t[GCC_PCNOC_BUS_TIMEOUT2_BCR] = { 0x31040, 0 },\n+\t[GCC_PCNOC_BUS_TIMEOUT3_BCR] = { 0x31048, 0 },\n+\t[GCC_PCNOC_BUS_TIMEOUT4_BCR] = { 0x31050, 0 },\n+\t[GCC_PCNOC_BUS_TIMEOUT5_BCR] = { 0x31058, 0 },\n+\t[GCC_PCNOC_BUS_TIMEOUT6_BCR] = { 0x31060, 0 },\n+\t[GCC_PCNOC_BUS_TIMEOUT7_BCR] = { 0x31068, 0 },\n+\t[GCC_PCNOC_BUS_TIMEOUT8_BCR] = { 0x31070, 0 },\n+\t[GCC_PCNOC_BUS_TIMEOUT9_BCR] = { 0x31078, 0 },\n+\t[GCC_PCNOC_TBU_BCR] = { 0x12034, 0 },\n+\t[GCC_PRNG_BCR] = { 0x13020, 0 },\n+\t[GCC_Q6SS_DBG_ARES] = { 0x2506c, 4 },\n+\t[GCC_Q6_AHB_ARES] = { 0x2506c, 3 },\n+\t[GCC_Q6_AHB_S_ARES] = { 0x2506c, 2 },\n+\t[GCC_Q6_AXIM2_ARES] = { 0x2506c, 1 },\n+\t[GCC_Q6_AXIM_ARES] = { 0x2506c, 0 },\n+\t[GCC_QDSS_BCR] = { 0x2d000, 0 },\n+\t[GCC_QPIC_BCR] = { 0x32000, 0 },\n+\t[GCC_QPIC_AHB_ARES] = { 0x3201c, 1 },\n+\t[GCC_QPIC_ARES] = { 0x3201c, 0 },\n+\t[GCC_QUSB2_0_PHY_BCR] = { 0x2c068, 0 },\n+\t[GCC_RBCPR_BCR] = { 0x39000, 0 },\n+\t[GCC_RBCPR_MX_BCR] = { 0x39014, 0 },\n+\t[GCC_SDCC_BCR] = { 0x33000, 0 },\n+\t[GCC_SEC_CTRL_BCR] = { 0x1a000, 0 },\n+\t[GCC_SMMU_CFG_BCR] = { 0x1202c, 0 },\n+\t[GCC_SNOC_BCR] = { 0x2e000, 0 },\n+\t[GCC_SPDM_BCR] = { 0x36000, 0 },\n+\t[GCC_TCSR_BCR] = { 0x3d000, 0 },\n+\t[GCC_TLMM_BCR] = { 0x3e000, 0 },\n+\t[GCC_TME_BCR] = { 0x10000, 0 },\n+\t[GCC_UNIPHY0_BCR] = { 0x17044, 0 },\n+\t[GCC_UNIPHY0_SYS_RESET] = { 0x17050, 0 },\n+\t[GCC_UNIPHY0_AHB_RESET] = { 0x17050, 1 },\n+\t[GCC_UNIPHY0_XPCS_RESET] = { 0x17050, 2 },\n+\t[GCC_UNIPHY1_SYS_RESET] = { 0x17060, 0 },\n+\t[GCC_UNIPHY1_AHB_RESET] = { 0x17060, 1 },\n+\t[GCC_UNIPHY1_XPCS_RESET] = { 0x17060, 2 },\n+\t[GCC_UNIPHY2_SYS_RESET] = { 0x17070, 0 },\n+\t[GCC_UNIPHY2_AHB_RESET] = { 0x17070, 1 },\n+\t[GCC_UNIPHY2_XPCS_RESET] = { 0x17070, 2 },\n+\t[GCC_UNIPHY1_BCR] = { 0x17054, 0 },\n+\t[GCC_UNIPHY2_BCR] = { 0x17064, 0 },\n+\t[GCC_USB0_PHY_BCR] = { 0x2c06c, 0 },\n+\t[GCC_USB3PHY_0_PHY_BCR] = { 0x2c070, 0 },\n+\t[GCC_USB_BCR] = { 0x2c000, 0 },\n+\t[GCC_USB_MISC_RESET] = { 0x2c064, 0 },\n+\t[GCC_WCSSAON_RESET] = { 0x25074, 0 },\n+\t[GCC_WCSS_ACMT_ARES] = { 0x25070, 5 },\n+\t[GCC_WCSS_AHB_S_ARES] = { 0x25070, 4 },\n+\t[GCC_WCSS_AXI_M_ARES] = { 0x25070, 3 },\n+\t[GCC_WCSS_BCR] = { 0x18004, 0 },\n+\t[GCC_WCSS_DBG_ARES] = { 0x25070, 2 },\n+\t[GCC_WCSS_DBG_BDG_ARES] = { 0x25070, 1 },\n+\t[GCC_WCSS_ECAHB_ARES] = { 0x25070, 0 },\n+\t[GCC_WCSS_Q6_BCR] = { 0x18000, 0 },\n+\t[GCC_WCSS_Q6_TBU_BCR] = { 0x12054, 0 },\n+};\n+\n+static const struct of_device_id gcc_ipq9574_match_table[] = {\n+\t{ .compatible = \"qcom,ipq9574-gcc\" },\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(of, gcc_ipq9574_match_table);\n+\n+static const struct regmap_config gcc_ipq9574_regmap_config = {\n+\t.reg_bits       = 32,\n+\t.reg_stride     = 4,\n+\t.val_bits       = 32,\n+\t.max_register   = 0x7fffc,\n+\t.fast_io\t= true,\n+};\n+\n+static const struct qcom_cc_desc gcc_ipq9574_desc = {\n+\t.config = &gcc_ipq9574_regmap_config,\n+\t.clks = gcc_ipq9574_clks,\n+\t.num_clks = ARRAY_SIZE(gcc_ipq9574_clks),\n+\t.resets = gcc_ipq9574_resets,\n+\t.num_resets = ARRAY_SIZE(gcc_ipq9574_resets),\n+\t.clk_hws = gcc_ipq9574_hws,\n+\t.num_clk_hws = ARRAY_SIZE(gcc_ipq9574_hws),\n+};\n+\n+static int gcc_ipq9574_probe(struct platform_device *pdev)\n+{\n+\treturn qcom_cc_probe(pdev, &gcc_ipq9574_desc);\n+}\n+\n+static struct platform_driver gcc_ipq9574_driver = {\n+\t.probe = gcc_ipq9574_probe,\n+\t.driver = {\n+\t\t.name   = \"qcom,gcc-ipq9574\",\n+\t\t.of_match_table = gcc_ipq9574_match_table,\n+\t},\n+};\n+\n+static int __init gcc_ipq9574_init(void)\n+{\n+\treturn platform_driver_register(&gcc_ipq9574_driver);\n+}\n+core_initcall(gcc_ipq9574_init);\n+\n+static void __exit gcc_ipq9574_exit(void)\n+{\n+\tplatform_driver_unregister(&gcc_ipq9574_driver);\n+}\n+module_exit(gcc_ipq9574_exit);\n+\n+MODULE_DESCRIPTION(\"Qualcomm Technologies, Inc. GCC IPQ9574 Driver\");\n+MODULE_LICENSE(\"GPL\");\n",
    "prefixes": [
        "V10",
        "2/4"
    ]
}