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GET /api/patches/1761709/?format=api
{ "id": 1761709, "url": "http://patchwork.ozlabs.org/api/patches/1761709/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20230327132718.573-2-quic_devipriy@quicinc.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20230327132718.573-2-quic_devipriy@quicinc.com>", "list_archive_url": null, "date": "2023-03-27T13:27:15", "name": "[V10,1/4] dt-bindings: clock: Add ipq9574 clock and reset definitions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c8eb37c53252a1549c2c12674a713397a333b755", "submitter": { "id": 85567, "url": "http://patchwork.ozlabs.org/api/people/85567/?format=api", "name": "Devi Priya", "email": "quic_devipriy@quicinc.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20230327132718.573-2-quic_devipriy@quicinc.com/mbox/", "series": [ { "id": 348168, "url": "http://patchwork.ozlabs.org/api/series/348168/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=348168", "date": "2023-03-27T13:27:14", "name": "Add minimal boot support for IPQ9574", "version": 10, "mbox": "http://patchwork.ozlabs.org/series/348168/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1761709/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1761709/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-gpio-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2620:137:e000::1:20; helo=out1.vger.email;\n envelope-from=linux-gpio-owner@vger.kernel.org; receiver=<UNKNOWN>)", "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=quicinc.com header.i=@quicinc.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=SK/wANNk;\n\tdkim-atps=neutral" ], "Received": [ "from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20])\n\tby legolas.ozlabs.org (Postfix) with ESMTP id 4PlYYd0g8tz1yYh\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 28 Mar 2023 00:28:53 +1100 (AEDT)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n id S232798AbjC0N2w (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n Mon, 27 Mar 2023 09:28:52 -0400", "from lindbergh.monkeyblade.net ([23.128.96.19]:46380 \"EHLO\n lindbergh.monkeyblade.net\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n with ESMTP id S232460AbjC0N23 (ORCPT\n <rfc822;linux-gpio@vger.kernel.org>); Mon, 27 Mar 2023 09:28:29 -0400", "from mx0b-0031df01.pphosted.com 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cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.986.41; Mon, 27 Mar 2023 06:27:46 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=qcppdkim1;\n bh=PG2UxY5LevOHnSWcNg/fjcIlRiWgQzwmf9ijrSKwkxg=;\n b=SK/wANNkxOziaqvUxksmuAH0Dp1Qb62FPfZ9glHiLpAQ/kAEJZMNzOOsZRMfaTQdnp1v\n xs6dHK6Tc3F4/lczZSedXbMXk08FigdgbSW7lywY60HCR74pJ1tHLBQr/F/pwFinQ61n\n X6sEJ6Z5XYOoOuu3ihJeqAoC3ss2ou1Asn7AxiTxXH/esCGV/aJ8sxEq1AWrdB31bpFD\n UBy5ZR0Sh4qOeNPOJt/3bSV69dML14hd92bY0bQBCFSos+eCKAwJ5O/gmoffSjF2u2Fz\n ucbDGh+p1lCFHKkY1q2eBbR66xGbLBfnhC1th/Fz9kYJMaSEpV4++gL/XP6fq7S0LNt2 cw==", "From": "Devi Priya <quic_devipriy@quicinc.com>", "To": "<agross@kernel.org>, <andersson@kernel.org>,\n <konrad.dybcio@linaro.org>, <robh+dt@kernel.org>,\n <krzysztof.kozlowski+dt@linaro.org>, <mturquette@baylibre.com>,\n <sboyd@kernel.org>, <linus.walleij@linaro.org>,\n <catalin.marinas@arm.com>, <will@kernel.org>,\n <p.zabel@pengutronix.de>, <shawnguo@kernel.org>, <arnd@arndb.de>,\n <marcel.ziswiler@toradex.com>, <dmitry.baryshkov@linaro.org>,\n <nfraprado@collabora.com>, <broonie@kernel.org>,\n <linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>,\n <linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>,\n <linux-gpio@vger.kernel.org>,\n <linux-arm-kernel@lists.infradead.org>", "CC": "<quic_srichara@quicinc.com>, <quic_gokulsri@quicinc.com>,\n <quic_sjaganat@quicinc.com>, <quic_kathirav@quicinc.com>,\n <quic_arajkuma@quicinc.com>, <quic_anusha@quicinc.com>,\n <quic_poovendh@quicinc.com>", "Subject": "[PATCH V10 1/4] dt-bindings: clock: Add ipq9574 clock and reset\n definitions", "Date": "Mon, 27 Mar 2023 18:57:15 +0530", "Message-ID": "<20230327132718.573-2-quic_devipriy@quicinc.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20230327132718.573-1-quic_devipriy@quicinc.com>", "References": "<20230327132718.573-1-quic_devipriy@quicinc.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.80.80.8]", "X-ClientProxiedBy": "nasanex01a.na.qualcomm.com (10.52.223.231) To\n nalasex01a.na.qualcomm.com (10.47.209.196)", "X-QCInternal": "smtphost", "X-Proofpoint-Virus-Version": [ "vendor=nai engine=6200 definitions=5800\n signatures=585085", "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22\n definitions=2023-03-24_11,2023-03-27_01,2023-02-09_01" ], "X-Proofpoint-ORIG-GUID": "LJExXKufTK8tcdpvhdShD8Rly8edTJhA", "X-Proofpoint-GUID": "LJExXKufTK8tcdpvhdShD8Rly8edTJhA", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n clxscore=1011\n lowpriorityscore=0 mlxscore=0 impostorscore=0 priorityscore=1501\n malwarescore=0 suspectscore=0 bulkscore=0 mlxlogscore=999 spamscore=0\n phishscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1\n engine=8.12.0-2303200000 definitions=main-2303270105", "X-Spam-Status": "No, score=-0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID,\n DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS\n autolearn=unavailable autolearn_force=no version=3.4.6", "X-Spam-Checker-Version": "SpamAssassin 3.4.6 (2021-04-09) on\n lindbergh.monkeyblade.net", "Precedence": "bulk", "List-ID": "<linux-gpio.vger.kernel.org>", "X-Mailing-List": "linux-gpio@vger.kernel.org" }, "content": "Add clock and reset ID definitions for ipq9574\n\nReviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>\nCo-developed-by: Anusha Rao <quic_anusha@quicinc.com>\nSigned-off-by: Anusha Rao <quic_anusha@quicinc.com>\nSigned-off-by: Devi Priya <quic_devipriy@quicinc.com>\n---\n Changes in V10:\n\t- Added Bjorn Andersson to the maintainers list in qcom,ipq9574-gcc.yaml\n\n .../bindings/clock/qcom,ipq9574-gcc.yaml | 62 +++++\n include/dt-bindings/clock/qcom,ipq9574-gcc.h | 213 ++++++++++++++++++\n include/dt-bindings/reset/qcom,ipq9574-gcc.h | 164 ++++++++++++++\n 3 files changed, 439 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml\n create mode 100644 include/dt-bindings/clock/qcom,ipq9574-gcc.h\n create mode 100644 include/dt-bindings/reset/qcom,ipq9574-gcc.h", "diff": "diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml\nnew file mode 100644\nindex 000000000000..944a0ea79cd6\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-gcc.yaml\n@@ -0,0 +1,62 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/clock/qcom,ipq9574-gcc.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Qualcomm Global Clock & Reset Controller on IPQ9574\n+\n+maintainers:\n+ - Bjorn Andersson <andersson@kernel.org>\n+ - Anusha Rao <quic_anusha@quicinc.com>\n+\n+description: |\n+ Qualcomm global clock control module provides the clocks, resets and power\n+ domains on IPQ9574\n+\n+ See also::\n+ include/dt-bindings/clock/qcom,ipq9574-gcc.h\n+ include/dt-bindings/reset/qcom,ipq9574-gcc.h\n+\n+properties:\n+ compatible:\n+ const: qcom,ipq9574-gcc\n+\n+ clocks:\n+ items:\n+ - description: Board XO source\n+ - description: Sleep clock source\n+ - description: Bias PLL ubi clock source\n+ - description: PCIE30 PHY0 pipe clock source\n+ - description: PCIE30 PHY1 pipe clock source\n+ - description: PCIE30 PHY2 pipe clock source\n+ - description: PCIE30 PHY3 pipe clock source\n+ - description: USB3 PHY pipe clock source\n+\n+required:\n+ - compatible\n+ - clocks\n+\n+allOf:\n+ - $ref: qcom,gcc.yaml#\n+\n+unevaluatedProperties: false\n+\n+examples:\n+ - |\n+ clock-controller@1800000 {\n+ compatible = \"qcom,ipq9574-gcc\";\n+ reg = <0x01800000 0x80000>;\n+ clocks = <&xo_board_clk>,\n+ <&sleep_clk>,\n+ <&bias_pll_ubi_nc_clk>,\n+ <&pcie30_phy0_pipe_clk>,\n+ <&pcie30_phy1_pipe_clk>,\n+ <&pcie30_phy2_pipe_clk>,\n+ <&pcie30_phy3_pipe_clk>,\n+ <&usb3phy_0_cc_pipe_clk>;\n+ #clock-cells = <1>;\n+ #reset-cells = <1>;\n+ #power-domain-cells = <1>;\n+ };\n+...\ndiff --git a/include/dt-bindings/clock/qcom,ipq9574-gcc.h b/include/dt-bindings/clock/qcom,ipq9574-gcc.h\nnew file mode 100644\nindex 000000000000..5a2961bfe893\n--- /dev/null\n+++ b/include/dt-bindings/clock/qcom,ipq9574-gcc.h\n@@ -0,0 +1,213 @@\n+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */\n+/*\n+ * Copyright (c) 2018-2023 The Linux Foundation. All rights reserved.\n+ */\n+\n+#ifndef _DT_BINDINGS_CLOCK_IPQ_GCC_9574_H\n+#define _DT_BINDINGS_CLOCK_IPQ_GCC_9574_H\n+\n+#define GPLL0_MAIN\t\t\t\t\t0\n+#define GPLL0\t\t\t\t\t\t1\n+#define GPLL2_MAIN\t\t\t\t\t2\n+#define GPLL2\t\t\t\t\t\t3\n+#define GPLL4_MAIN\t\t\t\t\t4\n+#define GPLL4\t\t\t\t\t\t5\n+#define GCC_SLEEP_CLK_SRC\t\t\t\t6\n+#define APSS_AHB_CLK_SRC\t\t\t\t7\n+#define APSS_AXI_CLK_SRC\t\t\t\t8\n+#define BLSP1_QUP1_I2C_APPS_CLK_SRC\t\t\t9\n+#define BLSP1_QUP1_SPI_APPS_CLK_SRC\t\t\t10\n+#define BLSP1_QUP2_I2C_APPS_CLK_SRC\t\t\t11\n+#define BLSP1_QUP2_SPI_APPS_CLK_SRC\t\t\t12\n+#define BLSP1_QUP3_I2C_APPS_CLK_SRC\t\t\t13\n+#define BLSP1_QUP3_SPI_APPS_CLK_SRC\t\t\t14\n+#define BLSP1_QUP4_I2C_APPS_CLK_SRC\t\t\t15\n+#define BLSP1_QUP4_SPI_APPS_CLK_SRC\t\t\t16\n+#define BLSP1_QUP5_I2C_APPS_CLK_SRC\t\t\t17\n+#define BLSP1_QUP5_SPI_APPS_CLK_SRC\t\t\t18\n+#define BLSP1_QUP6_I2C_APPS_CLK_SRC\t\t\t19\n+#define BLSP1_QUP6_SPI_APPS_CLK_SRC\t\t\t20\n+#define BLSP1_UART1_APPS_CLK_SRC\t\t\t21\n+#define BLSP1_UART2_APPS_CLK_SRC\t\t\t22\n+#define BLSP1_UART3_APPS_CLK_SRC\t\t\t23\n+#define BLSP1_UART4_APPS_CLK_SRC\t\t\t24\n+#define BLSP1_UART5_APPS_CLK_SRC\t\t\t25\n+#define BLSP1_UART6_APPS_CLK_SRC\t\t\t26\n+#define GCC_APSS_AHB_CLK\t\t\t\t27\n+#define GCC_APSS_AXI_CLK\t\t\t\t28\n+#define GCC_BLSP1_QUP1_I2C_APPS_CLK\t\t\t29\n+#define GCC_BLSP1_QUP1_SPI_APPS_CLK\t\t\t30\n+#define GCC_BLSP1_QUP2_I2C_APPS_CLK\t\t\t31\n+#define GCC_BLSP1_QUP2_SPI_APPS_CLK\t\t\t32\n+#define GCC_BLSP1_QUP3_I2C_APPS_CLK\t\t\t33\n+#define GCC_BLSP1_QUP3_SPI_APPS_CLK\t\t\t34\n+#define GCC_BLSP1_QUP4_I2C_APPS_CLK\t\t\t35\n+#define GCC_BLSP1_QUP4_SPI_APPS_CLK\t\t\t36\n+#define GCC_BLSP1_QUP5_I2C_APPS_CLK\t\t\t37\n+#define GCC_BLSP1_QUP5_SPI_APPS_CLK\t\t\t38\n+#define GCC_BLSP1_QUP6_I2C_APPS_CLK\t\t\t39\n+#define GCC_BLSP1_QUP6_SPI_APPS_CLK\t\t\t40\n+#define GCC_BLSP1_UART1_APPS_CLK\t\t\t41\n+#define GCC_BLSP1_UART2_APPS_CLK\t\t\t42\n+#define GCC_BLSP1_UART3_APPS_CLK\t\t\t43\n+#define GCC_BLSP1_UART4_APPS_CLK\t\t\t44\n+#define GCC_BLSP1_UART5_APPS_CLK\t\t\t45\n+#define GCC_BLSP1_UART6_APPS_CLK\t\t\t46\n+#define PCIE0_AXI_M_CLK_SRC\t\t\t\t47\n+#define GCC_PCIE0_AXI_M_CLK\t\t\t\t48\n+#define PCIE1_AXI_M_CLK_SRC\t\t\t\t49\n+#define GCC_PCIE1_AXI_M_CLK\t\t\t\t50\n+#define PCIE2_AXI_M_CLK_SRC\t\t\t\t51\n+#define GCC_PCIE2_AXI_M_CLK\t\t\t\t52\n+#define PCIE3_AXI_M_CLK_SRC\t\t\t\t53\n+#define GCC_PCIE3_AXI_M_CLK\t\t\t\t54\n+#define PCIE0_AXI_S_CLK_SRC\t\t\t\t55\n+#define GCC_PCIE0_AXI_S_BRIDGE_CLK\t\t\t56\n+#define GCC_PCIE0_AXI_S_CLK\t\t\t\t57\n+#define PCIE1_AXI_S_CLK_SRC\t\t\t\t58\n+#define GCC_PCIE1_AXI_S_BRIDGE_CLK\t\t\t59\n+#define GCC_PCIE1_AXI_S_CLK\t\t\t\t60\n+#define PCIE2_AXI_S_CLK_SRC\t\t\t\t61\n+#define GCC_PCIE2_AXI_S_BRIDGE_CLK\t\t\t62\n+#define GCC_PCIE2_AXI_S_CLK\t\t\t\t63\n+#define PCIE3_AXI_S_CLK_SRC\t\t\t\t64\n+#define GCC_PCIE3_AXI_S_BRIDGE_CLK\t\t\t65\n+#define GCC_PCIE3_AXI_S_CLK\t\t\t\t66\n+#define PCIE0_PIPE_CLK_SRC\t\t\t\t67\n+#define PCIE1_PIPE_CLK_SRC\t\t\t\t68\n+#define PCIE2_PIPE_CLK_SRC\t\t\t\t69\n+#define PCIE3_PIPE_CLK_SRC\t\t\t\t70\n+#define PCIE_AUX_CLK_SRC\t\t\t\t71\n+#define GCC_PCIE0_AUX_CLK\t\t\t\t72\n+#define GCC_PCIE1_AUX_CLK\t\t\t\t73\n+#define GCC_PCIE2_AUX_CLK\t\t\t\t74\n+#define GCC_PCIE3_AUX_CLK\t\t\t\t75\n+#define PCIE0_RCHNG_CLK_SRC\t\t\t\t76\n+#define GCC_PCIE0_RCHNG_CLK\t\t\t\t77\n+#define PCIE1_RCHNG_CLK_SRC\t\t\t\t78\n+#define GCC_PCIE1_RCHNG_CLK\t\t\t\t79\n+#define PCIE2_RCHNG_CLK_SRC\t\t\t\t80\n+#define GCC_PCIE2_RCHNG_CLK\t\t\t\t81\n+#define PCIE3_RCHNG_CLK_SRC\t\t\t\t82\n+#define GCC_PCIE3_RCHNG_CLK\t\t\t\t83\n+#define GCC_PCIE0_AHB_CLK\t\t\t\t84\n+#define GCC_PCIE1_AHB_CLK\t\t\t\t85\n+#define GCC_PCIE2_AHB_CLK\t\t\t\t86\n+#define GCC_PCIE3_AHB_CLK\t\t\t\t87\n+#define USB0_AUX_CLK_SRC\t\t\t\t88\n+#define GCC_USB0_AUX_CLK\t\t\t\t89\n+#define USB0_MASTER_CLK_SRC\t\t\t\t90\n+#define GCC_USB0_MASTER_CLK\t\t\t\t91\n+#define GCC_SNOC_USB_CLK\t\t\t\t92\n+#define GCC_ANOC_USB_AXI_CLK\t\t\t\t93\n+#define USB0_MOCK_UTMI_CLK_SRC\t\t\t\t94\n+#define USB0_MOCK_UTMI_DIV_CLK_SRC\t\t\t95\n+#define GCC_USB0_MOCK_UTMI_CLK\t\t\t\t96\n+#define USB0_PIPE_CLK_SRC\t\t\t\t97\n+#define GCC_USB0_PHY_CFG_AHB_CLK\t\t\t98\n+#define SDCC1_APPS_CLK_SRC\t\t\t\t99\n+#define GCC_SDCC1_APPS_CLK\t\t\t\t100\n+#define SDCC1_ICE_CORE_CLK_SRC\t\t\t\t101\n+#define GCC_SDCC1_ICE_CORE_CLK\t\t\t\t102\n+#define GCC_SDCC1_AHB_CLK\t\t\t\t103\n+#define PCNOC_BFDCD_CLK_SRC\t\t\t\t104\n+#define GCC_NSSCFG_CLK\t\t\t\t\t105\n+#define GCC_NSSNOC_NSSCC_CLK\t\t\t\t106\n+#define GCC_NSSCC_CLK\t\t\t\t\t107\n+#define GCC_NSSNOC_PCNOC_1_CLK\t\t\t\t108\n+#define GCC_QDSS_DAP_AHB_CLK\t\t\t\t109\n+#define GCC_QDSS_CFG_AHB_CLK\t\t\t\t110\n+#define GCC_QPIC_AHB_CLK\t\t\t\t111\n+#define GCC_QPIC_CLK\t\t\t\t\t112\n+#define GCC_BLSP1_AHB_CLK\t\t\t\t113\n+#define GCC_MDIO_AHB_CLK\t\t\t\t114\n+#define GCC_PRNG_AHB_CLK\t\t\t\t115\n+#define GCC_UNIPHY0_AHB_CLK\t\t\t\t116\n+#define GCC_UNIPHY1_AHB_CLK\t\t\t\t117\n+#define GCC_UNIPHY2_AHB_CLK\t\t\t\t118\n+#define GCC_CMN_12GPLL_AHB_CLK\t\t\t\t119\n+#define GCC_CMN_12GPLL_APU_CLK\t\t\t\t120\n+#define SYSTEM_NOC_BFDCD_CLK_SRC\t\t\t121\n+#define GCC_NSSNOC_SNOC_CLK\t\t\t\t122\n+#define GCC_NSSNOC_SNOC_1_CLK\t\t\t\t123\n+#define GCC_QDSS_ETR_USB_CLK\t\t\t\t124\n+#define WCSS_AHB_CLK_SRC\t\t\t\t125\n+#define GCC_Q6_AHB_CLK\t\t\t\t\t126\n+#define GCC_Q6_AHB_S_CLK\t\t\t\t127\n+#define GCC_WCSS_ECAHB_CLK\t\t\t\t128\n+#define GCC_WCSS_ACMT_CLK\t\t\t\t129\n+#define GCC_SYS_NOC_WCSS_AHB_CLK\t\t\t130\n+#define WCSS_AXI_M_CLK_SRC\t\t\t\t131\n+#define GCC_ANOC_WCSS_AXI_M_CLK\t\t\t\t132\n+#define QDSS_AT_CLK_SRC\t\t\t\t\t133\n+#define GCC_Q6SS_ATBM_CLK\t\t\t\t134\n+#define GCC_WCSS_DBG_IFC_ATB_CLK\t\t\t135\n+#define GCC_NSSNOC_ATB_CLK\t\t\t\t136\n+#define GCC_QDSS_AT_CLK\t\t\t\t\t137\n+#define GCC_SYS_NOC_AT_CLK\t\t\t\t138\n+#define GCC_PCNOC_AT_CLK\t\t\t\t139\n+#define GCC_USB0_EUD_AT_CLK\t\t\t\t140\n+#define GCC_QDSS_EUD_AT_CLK\t\t\t\t141\n+#define QDSS_STM_CLK_SRC\t\t\t\t142\n+#define GCC_QDSS_STM_CLK\t\t\t\t143\n+#define GCC_SYS_NOC_QDSS_STM_AXI_CLK\t\t\t144\n+#define QDSS_TRACECLKIN_CLK_SRC\t\t\t\t145\n+#define GCC_QDSS_TRACECLKIN_CLK\t\t\t\t146\n+#define QDSS_TSCTR_CLK_SRC\t\t\t\t147\n+#define GCC_Q6_TSCTR_1TO2_CLK\t\t\t\t148\n+#define GCC_WCSS_DBG_IFC_NTS_CLK\t\t\t149\n+#define GCC_QDSS_TSCTR_DIV2_CLK\t\t\t\t150\n+#define GCC_QDSS_TS_CLK\t\t\t\t\t151\n+#define GCC_QDSS_TSCTR_DIV4_CLK\t\t\t\t152\n+#define GCC_NSS_TS_CLK\t\t\t\t\t153\n+#define GCC_QDSS_TSCTR_DIV8_CLK\t\t\t\t154\n+#define GCC_QDSS_TSCTR_DIV16_CLK\t\t\t155\n+#define GCC_Q6SS_PCLKDBG_CLK\t\t\t\t156\n+#define GCC_Q6SS_TRIG_CLK\t\t\t\t157\n+#define GCC_WCSS_DBG_IFC_APB_CLK\t\t\t158\n+#define GCC_WCSS_DBG_IFC_DAPBUS_CLK\t\t\t159\n+#define GCC_QDSS_DAP_CLK\t\t\t\t160\n+#define GCC_QDSS_APB2JTAG_CLK\t\t\t\t161\n+#define GCC_QDSS_TSCTR_DIV3_CLK\t\t\t\t162\n+#define QPIC_IO_MACRO_CLK_SRC\t\t\t\t163\n+#define GCC_QPIC_IO_MACRO_CLK 164\n+#define Q6_AXI_CLK_SRC\t\t\t\t\t165\n+#define GCC_Q6_AXIM_CLK\t\t\t\t\t166\n+#define GCC_WCSS_Q6_TBU_CLK\t\t\t\t167\n+#define GCC_MEM_NOC_Q6_AXI_CLK\t\t\t\t168\n+#define Q6_AXIM2_CLK_SRC\t\t\t\t169\n+#define NSSNOC_MEMNOC_BFDCD_CLK_SRC\t\t\t170\n+#define GCC_NSSNOC_MEMNOC_CLK\t\t\t\t171\n+#define GCC_NSSNOC_MEM_NOC_1_CLK\t\t\t172\n+#define GCC_NSS_TBU_CLK\t\t\t\t\t173\n+#define GCC_MEM_NOC_NSSNOC_CLK\t\t\t\t174\n+#define LPASS_AXIM_CLK_SRC\t\t\t\t175\n+#define LPASS_SWAY_CLK_SRC\t\t\t\t176\n+#define ADSS_PWM_CLK_SRC\t\t\t\t177\n+#define GCC_ADSS_PWM_CLK\t\t\t\t178\n+#define GP1_CLK_SRC\t\t\t\t\t179\n+#define GP2_CLK_SRC\t\t\t\t\t180\n+#define GP3_CLK_SRC\t\t\t\t\t181\n+#define DDRSS_SMS_SLOW_CLK_SRC\t\t\t\t182\n+#define GCC_XO_CLK_SRC\t\t\t\t\t183\n+#define GCC_XO_CLK\t\t\t\t\t184\n+#define GCC_NSSNOC_QOSGEN_REF_CLK\t\t\t185\n+#define GCC_NSSNOC_TIMEOUT_REF_CLK\t\t\t186\n+#define GCC_XO_DIV4_CLK\t\t\t\t\t187\n+#define GCC_UNIPHY0_SYS_CLK\t\t\t\t188\n+#define GCC_UNIPHY1_SYS_CLK\t\t\t\t189\n+#define GCC_UNIPHY2_SYS_CLK\t\t\t\t190\n+#define GCC_CMN_12GPLL_SYS_CLK\t\t\t\t191\n+#define GCC_NSSNOC_XO_DCD_CLK\t\t\t\t192\n+#define GCC_Q6SS_BOOT_CLK\t\t\t\t193\n+#define UNIPHY_SYS_CLK_SRC\t\t\t\t194\n+#define NSS_TS_CLK_SRC\t\t\t\t\t195\n+#define GCC_ANOC_PCIE0_1LANE_M_CLK\t\t\t196\n+#define GCC_ANOC_PCIE1_1LANE_M_CLK\t\t\t197\n+#define GCC_ANOC_PCIE2_2LANE_M_CLK\t\t\t198\n+#define GCC_ANOC_PCIE3_2LANE_M_CLK\t\t\t199\n+#define GCC_SNOC_PCIE0_1LANE_S_CLK\t\t\t200\n+#define GCC_SNOC_PCIE1_1LANE_S_CLK\t\t\t201\n+#define GCC_SNOC_PCIE2_2LANE_S_CLK\t\t\t202\n+#define GCC_SNOC_PCIE3_2LANE_S_CLK\t\t\t203\n+#endif\ndiff --git a/include/dt-bindings/reset/qcom,ipq9574-gcc.h b/include/dt-bindings/reset/qcom,ipq9574-gcc.h\nnew file mode 100644\nindex 000000000000..d01dc6a24cf1\n--- /dev/null\n+++ b/include/dt-bindings/reset/qcom,ipq9574-gcc.h\n@@ -0,0 +1,164 @@\n+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */\n+/*\n+ * Copyright (c) 2018-2023, The Linux Foundation. All rights reserved.\n+ */\n+\n+#ifndef _DT_BINDINGS_RESET_IPQ_GCC_9574_H\n+#define _DT_BINDINGS_RESET_IPQ_GCC_9574_H\n+\n+#define GCC_ADSS_BCR\t\t\t\t\t\t0\n+#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR\t\t\t1\n+#define GCC_BLSP1_BCR\t\t\t\t\t\t2\n+#define GCC_BLSP1_QUP1_BCR\t\t\t\t\t3\n+#define GCC_BLSP1_QUP2_BCR\t\t\t\t\t4\n+#define GCC_BLSP1_QUP3_BCR\t\t\t\t\t5\n+#define GCC_BLSP1_QUP4_BCR\t\t\t\t\t6\n+#define GCC_BLSP1_QUP5_BCR\t\t\t\t\t7\n+#define GCC_BLSP1_QUP6_BCR\t\t\t\t\t8\n+#define GCC_BLSP1_UART1_BCR\t\t\t\t\t9\n+#define GCC_BLSP1_UART2_BCR\t\t\t\t\t10\n+#define GCC_BLSP1_UART3_BCR\t\t\t\t\t11\n+#define GCC_BLSP1_UART4_BCR\t\t\t\t\t12\n+#define GCC_BLSP1_UART5_BCR\t\t\t\t\t13\n+#define GCC_BLSP1_UART6_BCR\t\t\t\t\t14\n+#define GCC_BOOT_ROM_BCR\t\t\t\t\t15\n+#define GCC_MDIO_BCR\t\t\t\t\t\t16\n+#define GCC_NSS_BCR\t\t\t\t\t\t17\n+#define GCC_NSS_TBU_BCR\t\t\t\t\t\t18\n+#define GCC_PCIE0_BCR\t\t\t\t\t\t19\n+#define GCC_PCIE0_LINK_DOWN_BCR\t\t\t\t\t20\n+#define GCC_PCIE0_PHY_BCR\t\t\t\t\t21\n+#define GCC_PCIE0PHY_PHY_BCR\t\t\t\t\t22\n+#define GCC_PCIE1_BCR\t\t\t\t\t\t23\n+#define GCC_PCIE1_LINK_DOWN_BCR\t\t\t\t\t24\n+#define GCC_PCIE1_PHY_BCR\t\t\t\t\t25\n+#define GCC_PCIE1PHY_PHY_BCR\t\t\t\t\t26\n+#define GCC_PCIE2_BCR\t\t\t\t\t\t27\n+#define GCC_PCIE2_LINK_DOWN_BCR\t\t\t\t\t28\n+#define GCC_PCIE2_PHY_BCR\t\t\t\t\t29\n+#define GCC_PCIE2PHY_PHY_BCR\t\t\t\t\t30\n+#define GCC_PCIE3_BCR\t\t\t\t\t\t31\n+#define GCC_PCIE3_LINK_DOWN_BCR\t\t\t\t\t32\n+#define GCC_PCIE3_PHY_BCR\t\t\t\t\t33\n+#define GCC_PCIE3PHY_PHY_BCR\t\t\t\t\t34\n+#define GCC_PRNG_BCR\t\t\t\t\t\t35\n+#define GCC_QUSB2_0_PHY_BCR\t\t\t\t\t36\n+#define GCC_SDCC_BCR\t\t\t\t\t\t37\n+#define GCC_TLMM_BCR\t\t\t\t\t\t38\n+#define GCC_UNIPHY0_BCR\t\t\t\t\t\t39\n+#define GCC_UNIPHY1_BCR\t\t\t\t\t\t40\n+#define GCC_UNIPHY2_BCR\t\t\t\t\t\t41\n+#define GCC_USB0_PHY_BCR\t\t\t\t\t42\n+#define GCC_USB3PHY_0_PHY_BCR\t\t\t\t\t43\n+#define GCC_USB_BCR\t\t\t\t\t\t44\n+#define GCC_ANOC0_TBU_BCR\t\t\t\t\t45\n+#define GCC_ANOC1_TBU_BCR\t\t\t\t\t46\n+#define GCC_ANOC_BCR\t\t\t\t\t\t47\n+#define GCC_APSS_TCU_BCR\t\t\t\t\t48\n+#define GCC_CMN_BLK_BCR\t\t\t\t\t\t49\n+#define GCC_CMN_BLK_AHB_ARES\t\t\t\t\t50\n+#define GCC_CMN_BLK_SYS_ARES\t\t\t\t\t51\n+#define GCC_CMN_BLK_APU_ARES\t\t\t\t\t52\n+#define GCC_DCC_BCR\t\t\t\t\t\t53\n+#define GCC_DDRSS_BCR\t\t\t\t\t\t54\n+#define GCC_IMEM_BCR\t\t\t\t\t\t55\n+#define GCC_LPASS_BCR\t\t\t\t\t\t56\n+#define GCC_MPM_BCR\t\t\t\t\t\t57\n+#define GCC_MSG_RAM_BCR\t\t\t\t\t\t58\n+#define GCC_NSSNOC_MEMNOC_1_ARES\t\t\t\t59\n+#define GCC_NSSNOC_PCNOC_1_ARES\t\t\t\t\t60\n+#define GCC_NSSNOC_SNOC_1_ARES\t\t\t\t\t61\n+#define GCC_NSSNOC_XO_DCD_ARES\t\t\t\t\t62\n+#define GCC_NSSNOC_TS_ARES\t\t\t\t\t63\n+#define GCC_NSSCC_ARES\t\t\t\t\t\t64\n+#define GCC_NSSNOC_NSSCC_ARES\t\t\t\t\t65\n+#define GCC_NSSNOC_ATB_ARES\t\t\t\t\t66\n+#define GCC_NSSNOC_MEMNOC_ARES\t\t\t\t\t67\n+#define GCC_NSSNOC_QOSGEN_REF_ARES\t\t\t\t68\n+#define GCC_NSSNOC_SNOC_ARES\t\t\t\t\t69\n+#define GCC_NSSNOC_TIMEOUT_REF_ARES\t\t\t\t70\n+#define GCC_NSS_CFG_ARES\t\t\t\t\t71\n+#define GCC_UBI0_DBG_ARES\t\t\t\t\t72\n+#define GCC_PCIE0_AHB_ARES\t\t\t\t\t73\n+#define GCC_PCIE0_AUX_ARES\t\t\t\t\t74\n+#define GCC_PCIE0_AXI_M_ARES\t\t\t\t\t75\n+#define GCC_PCIE0_AXI_M_STICKY_ARES\t\t\t\t76\n+#define GCC_PCIE0_AXI_S_ARES\t\t\t\t\t77\n+#define GCC_PCIE0_AXI_S_STICKY_ARES\t\t\t\t78\n+#define GCC_PCIE0_CORE_STICKY_ARES\t\t\t\t79\n+#define GCC_PCIE0_PIPE_ARES\t\t\t\t\t80\n+#define GCC_PCIE1_AHB_ARES\t\t\t\t\t81\n+#define GCC_PCIE1_AUX_ARES\t\t\t\t\t82\n+#define GCC_PCIE1_AXI_M_ARES\t\t\t\t\t83\n+#define GCC_PCIE1_AXI_M_STICKY_ARES\t\t\t\t84\n+#define GCC_PCIE1_AXI_S_ARES\t\t\t\t\t85\n+#define GCC_PCIE1_AXI_S_STICKY_ARES\t\t\t\t86\n+#define GCC_PCIE1_CORE_STICKY_ARES\t\t\t\t87\n+#define GCC_PCIE1_PIPE_ARES\t\t\t\t\t88\n+#define GCC_PCIE2_AHB_ARES\t\t\t\t\t89\n+#define GCC_PCIE2_AUX_ARES\t\t\t\t\t90\n+#define GCC_PCIE2_AXI_M_ARES\t\t\t\t\t91\n+#define GCC_PCIE2_AXI_M_STICKY_ARES\t\t\t\t92\n+#define GCC_PCIE2_AXI_S_ARES\t\t\t\t\t93\n+#define GCC_PCIE2_AXI_S_STICKY_ARES\t\t\t\t94\n+#define GCC_PCIE2_CORE_STICKY_ARES\t\t\t\t95\n+#define GCC_PCIE2_PIPE_ARES\t\t\t\t\t96\n+#define GCC_PCIE3_AHB_ARES\t\t\t\t\t97\n+#define GCC_PCIE3_AUX_ARES\t\t\t\t\t98\n+#define GCC_PCIE3_AXI_M_ARES\t\t\t\t\t99\n+#define GCC_PCIE3_AXI_M_STICKY_ARES\t\t\t\t100\n+#define GCC_PCIE3_AXI_S_ARES\t\t\t\t\t101\n+#define GCC_PCIE3_AXI_S_STICKY_ARES\t\t\t\t102\n+#define GCC_PCIE3_CORE_STICKY_ARES\t\t\t\t103\n+#define GCC_PCIE3_PIPE_ARES\t\t\t\t\t104\n+#define GCC_PCNOC_BCR\t\t\t\t\t\t105\n+#define GCC_PCNOC_BUS_TIMEOUT0_BCR\t\t\t\t106\n+#define GCC_PCNOC_BUS_TIMEOUT1_BCR\t\t\t\t107\n+#define GCC_PCNOC_BUS_TIMEOUT2_BCR\t\t\t\t108\n+#define GCC_PCNOC_BUS_TIMEOUT3_BCR\t\t\t\t109\n+#define GCC_PCNOC_BUS_TIMEOUT4_BCR\t\t\t\t110\n+#define GCC_PCNOC_BUS_TIMEOUT5_BCR\t\t\t\t111\n+#define GCC_PCNOC_BUS_TIMEOUT6_BCR\t\t\t\t112\n+#define GCC_PCNOC_BUS_TIMEOUT7_BCR\t\t\t\t113\n+#define GCC_PCNOC_BUS_TIMEOUT8_BCR\t\t\t\t114\n+#define GCC_PCNOC_BUS_TIMEOUT9_BCR\t\t\t\t115\n+#define GCC_PCNOC_TBU_BCR\t\t\t\t\t116\n+#define GCC_Q6SS_DBG_ARES\t\t\t\t\t117\n+#define GCC_Q6_AHB_ARES\t\t\t\t\t\t118\n+#define GCC_Q6_AHB_S_ARES\t\t\t\t\t119\n+#define GCC_Q6_AXIM2_ARES\t\t\t\t\t120\n+#define GCC_Q6_AXIM_ARES\t\t\t\t\t121\n+#define GCC_QDSS_BCR\t\t\t\t\t\t122\n+#define GCC_QPIC_BCR\t\t\t\t\t\t123\n+#define GCC_QPIC_AHB_ARES\t\t\t\t\t124\n+#define GCC_QPIC_ARES\t\t\t\t\t\t125\n+#define GCC_RBCPR_BCR\t\t\t\t\t\t126\n+#define GCC_RBCPR_MX_BCR\t\t\t\t\t127\n+#define GCC_SEC_CTRL_BCR\t\t\t\t\t128\n+#define GCC_SMMU_CFG_BCR\t\t\t\t\t129\n+#define GCC_SNOC_BCR\t\t\t\t\t\t130\n+#define GCC_SPDM_BCR\t\t\t\t\t\t131\n+#define GCC_TME_BCR\t\t\t\t\t\t132\n+#define GCC_UNIPHY0_SYS_RESET\t\t\t\t\t133\n+#define GCC_UNIPHY0_AHB_RESET\t\t\t\t\t134\n+#define GCC_UNIPHY0_XPCS_RESET\t\t\t\t\t135\n+#define GCC_UNIPHY1_SYS_RESET\t\t\t\t\t136\n+#define GCC_UNIPHY1_AHB_RESET\t\t\t\t\t137\n+#define GCC_UNIPHY1_XPCS_RESET\t\t\t\t\t138\n+#define GCC_UNIPHY2_SYS_RESET\t\t\t\t\t139\n+#define GCC_UNIPHY2_AHB_RESET\t\t\t\t\t140\n+#define GCC_UNIPHY2_XPCS_RESET\t\t\t\t\t141\n+#define GCC_USB_MISC_RESET\t\t\t\t\t142\n+#define GCC_WCSSAON_RESET\t\t\t\t\t143\n+#define GCC_WCSS_ACMT_ARES\t\t\t\t\t144\n+#define GCC_WCSS_AHB_S_ARES\t\t\t\t\t145\n+#define GCC_WCSS_AXI_M_ARES\t\t\t\t\t146\n+#define GCC_WCSS_BCR\t\t\t\t\t\t147\n+#define GCC_WCSS_DBG_ARES\t\t\t\t\t148\n+#define GCC_WCSS_DBG_BDG_ARES\t\t\t\t\t149\n+#define GCC_WCSS_ECAHB_ARES\t\t\t\t\t150\n+#define GCC_WCSS_Q6_BCR\t\t\t\t\t\t151\n+#define GCC_WCSS_Q6_TBU_BCR\t\t\t\t\t152\n+#define GCC_TCSR_BCR\t\t\t\t\t\t153\n+\n+#endif\n", "prefixes": [ "V10", "1/4" ] }