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GET /api/patches/1757751/?format=api
{ "id": 1757751, "url": "http://patchwork.ozlabs.org/api/patches/1757751/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20230316072940.29137-5-quic_devipriy@quicinc.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20230316072940.29137-5-quic_devipriy@quicinc.com>", "list_archive_url": null, "date": "2023-03-16T07:29:38", "name": "[V9,4/6] pinctrl: qcom: Add IPQ9574 pinctrl driver", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "91b680086742cfc294f152b9f70d35b08fdb5902", "submitter": { "id": 85567, "url": "http://patchwork.ozlabs.org/api/people/85567/?format=api", "name": "Devi Priya", "email": "quic_devipriy@quicinc.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20230316072940.29137-5-quic_devipriy@quicinc.com/mbox/", "series": [ { "id": 346538, "url": "http://patchwork.ozlabs.org/api/series/346538/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=346538", "date": "2023-03-16T07:29:34", "name": "Add minimal boot support for IPQ9574", "version": 9, "mbox": "http://patchwork.ozlabs.org/series/346538/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1757751/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1757751/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-gpio-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2620:137:e000::1:20; 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Thu, 16 Mar 2023 00:30:39 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=qcppdkim1;\n bh=7R83jxLjf081NF+T4D7GceGmOnogIqHITrKxRB0ZDLQ=;\n b=G+cxFjuj2I4vgFqtdNCXzsps80en5y9UKmtbim2MqrHJYZBFdKanuPRGED/gnj4yvljo\n S+ZGdPCCnJA18oT1olMMkuq7TSVOlRt+eHFwEPhXOa/W2kwTVsdq1/nPGE/9rah9RkT+\n lz4lyv4q9bJZN00yDcRd8KH2dxj9T+zhHn+jiBNM7zDFwcgFNhj54eGbcmBmRvUgr5yy\n o/IHunA5PCvy4Hfg0XBrmY/ytfVJYt0A3T9XYc6QSxsVLEW9KGwl2CoJOxxdTZHx8oV6\n E0OCzxsDV9TFd1fpHkkUS/VfHjcPCUzLvDC/Ks6ZxKLLXsRz8R36MThURDxCctCDAVdK sw==", "From": "Devi Priya <quic_devipriy@quicinc.com>", "To": "<agross@kernel.org>, <andersson@kernel.org>,\n <konrad.dybcio@linaro.org>, <robh+dt@kernel.org>,\n <krzysztof.kozlowski+dt@linaro.org>, <mturquette@baylibre.com>,\n <sboyd@kernel.org>, <linus.walleij@linaro.org>,\n <catalin.marinas@arm.com>, <will@kernel.org>,\n <p.zabel@pengutronix.de>, <shawnguo@kernel.org>, <arnd@arndb.de>,\n <marcel.ziswiler@toradex.com>, <dmitry.baryshkov@linaro.org>,\n <nfraprado@collabora.com>, <broonie@kernel.org>,\n <linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>,\n <linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>,\n <linux-gpio@vger.kernel.org>,\n <linux-arm-kernel@lists.infradead.org>", "CC": "<quic_srichara@quicinc.com>, <quic_gokulsri@quicinc.com>,\n <quic_sjaganat@quicinc.com>, <quic_kathirav@quicinc.com>,\n <quic_arajkuma@quicinc.com>, <quic_anusha@quicinc.com>,\n <quic_poovendh@quicinc.com>", "Subject": "[PATCH V9 4/6] pinctrl: qcom: Add IPQ9574 pinctrl driver", "Date": "Thu, 16 Mar 2023 12:59:38 +0530", "Message-ID": "<20230316072940.29137-5-quic_devipriy@quicinc.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20230316072940.29137-1-quic_devipriy@quicinc.com>", "References": "<20230316072940.29137-1-quic_devipriy@quicinc.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.80.80.8]", "X-ClientProxiedBy": "nasanex01a.na.qualcomm.com (10.52.223.231) To\n nalasex01a.na.qualcomm.com (10.47.209.196)", "X-QCInternal": "smtphost", "X-Proofpoint-Virus-Version": [ "vendor=nai engine=6200 definitions=5800\n signatures=585085", "vendor=baseguard\n engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22\n definitions=2023-03-16_05,2023-03-15_01,2023-02-09_01" ], "X-Proofpoint-GUID": "BRGbSQGCp309t7sd62BnYRLB6143LEzW", "X-Proofpoint-ORIG-GUID": "BRGbSQGCp309t7sd62BnYRLB6143LEzW", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n spamscore=0\n priorityscore=1501 phishscore=0 malwarescore=0 lowpriorityscore=0\n adultscore=0 impostorscore=0 mlxscore=0 bulkscore=0 clxscore=1015\n mlxlogscore=999 suspectscore=0 classifier=spam adjust=0 reason=mlx\n scancount=1 engine=8.12.0-2303150002 definitions=main-2303160063", "X-Spam-Status": "No, score=-2.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_LOW,SPF_HELO_NONE,\n SPF_PASS autolearn=ham autolearn_force=no version=3.4.6", "X-Spam-Checker-Version": "SpamAssassin 3.4.6 (2021-04-09) on\n lindbergh.monkeyblade.net", "Precedence": "bulk", "List-ID": "<linux-gpio.vger.kernel.org>", "X-Mailing-List": "linux-gpio@vger.kernel.org" }, "content": "Add pinctrl definitions for the TLMM of IPQ9574\n\nReviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>\nCo-developed-by: Anusha Rao <quic_anusha@quicinc.com>\nSigned-off-by: Anusha Rao <quic_anusha@quicinc.com>\nSigned-off-by: Devi Priya <quic_devipriy@quicinc.com>\n---\n Changes in V9:\n\t- Added COMPILE_TEST for non-OF configurations in config PINCTRL_IPQ9574\n\t- Unwrapped the lines for PINGROUP 34 & 62 in ipq9574_groups\n\t- Removed the comma from terminator line in ipq9574_pinctrl_of_match[] array\n\t- Moved the MODULE_DEVICE_TABLE entry just below the array\n\t ipq9574_pinctrl_of_match[]\n\n drivers/pinctrl/qcom/Kconfig | 11 +\n drivers/pinctrl/qcom/Makefile | 1 +\n drivers/pinctrl/qcom/pinctrl-ipq9574.c | 826 +++++++++++++++++++++++++\n 3 files changed, 838 insertions(+)\n create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq9574.c", "diff": "diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig\nindex 62d4810cfee1..cdd509e7a535 100644\n--- a/drivers/pinctrl/qcom/Kconfig\n+++ b/drivers/pinctrl/qcom/Kconfig\n@@ -80,6 +80,17 @@ config PINCTRL_IPQ6018\n \t Qualcomm Technologies Inc. IPQ6018 platform. Select this for\n \t IPQ6018.\n \n+config PINCTRL_IPQ9574\n+\ttristate \"Qualcomm Technologies, Inc. IPQ9574 pin controller driver\"\n+\tdepends on OF || COMPILE_TEST\n+\tdepends on ARM64 || COMPILE_TEST\n+\tdepends on PINCTRL_MSM\n+\thelp\n+\t This is the pinctrl, pinmux, pinconf and gpiolib driver for\n+ the Qualcomm Technologies Inc. TLMM block found on the\n+ Qualcomm Technologies Inc. IPQ9574 platform. Select this for\n+ IPQ9574.\n+\n config PINCTRL_MSM8226\n \ttristate \"Qualcomm 8226 pin controller driver\"\n \tdepends on OF\ndiff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile\nindex bea53b52275b..7a78cf4c3c6c 100644\n--- a/drivers/pinctrl/qcom/Makefile\n+++ b/drivers/pinctrl/qcom/Makefile\n@@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_IPQ8064)\t+= pinctrl-ipq8064.o\n obj-$(CONFIG_PINCTRL_IPQ5332)\t+= pinctrl-ipq5332.o\n obj-$(CONFIG_PINCTRL_IPQ8074)\t+= pinctrl-ipq8074.o\n obj-$(CONFIG_PINCTRL_IPQ6018)\t+= pinctrl-ipq6018.o\n+obj-$(CONFIG_PINCTRL_IPQ9574)\t+= pinctrl-ipq9574.o\n obj-$(CONFIG_PINCTRL_MSM8226)\t+= pinctrl-msm8226.o\n obj-$(CONFIG_PINCTRL_MSM8660)\t+= pinctrl-msm8660.o\n obj-$(CONFIG_PINCTRL_MSM8960)\t+= pinctrl-msm8960.o\ndiff --git a/drivers/pinctrl/qcom/pinctrl-ipq9574.c b/drivers/pinctrl/qcom/pinctrl-ipq9574.c\nnew file mode 100644\nindex 000000000000..7f057b62475f\n--- /dev/null\n+++ b/drivers/pinctrl/qcom/pinctrl-ipq9574.c\n@@ -0,0 +1,826 @@\n+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+/*\n+ * Copyright (c) 2023 The Linux Foundation. All rights reserved.\n+ */\n+\n+#include <linux/module.h>\n+#include <linux/of.h>\n+#include <linux/platform_device.h>\n+#include <linux/pinctrl/pinctrl.h>\n+\n+#include \"pinctrl-msm.h\"\n+\n+#define FUNCTION(fname)\t\t\t \\\n+\t[msm_mux_##fname] = {\t\t \\\n+\t\t.name = #fname,\t\t\t\t\\\n+\t\t.groups = fname##_groups, \\\n+\t\t.ngroups = ARRAY_SIZE(fname##_groups),\t\\\n+\t}\n+\n+#define REG_SIZE 0x1000\n+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9)\t\\\n+\t{\t\t\t\t\t \\\n+\t\t.name = \"gpio\" #id,\t\t\t\\\n+\t\t.pins = gpio##id##_pins,\t\t\\\n+\t\t.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins),\t\\\n+\t\t.funcs = (int[]){\t\t\t\\\n+\t\t\tmsm_mux_gpio, /* gpio mode */\t\\\n+\t\t\tmsm_mux_##f1,\t\t\t\\\n+\t\t\tmsm_mux_##f2,\t\t\t\\\n+\t\t\tmsm_mux_##f3,\t\t\t\\\n+\t\t\tmsm_mux_##f4,\t\t\t\\\n+\t\t\tmsm_mux_##f5,\t\t\t\\\n+\t\t\tmsm_mux_##f6,\t\t\t\\\n+\t\t\tmsm_mux_##f7,\t\t\t\\\n+\t\t\tmsm_mux_##f8,\t\t\t\\\n+\t\t\tmsm_mux_##f9\t\t\t\\\n+\t\t},\t\t\t\t \\\n+\t\t.nfuncs = 10,\t\t\t\t\\\n+\t\t.ctl_reg = REG_SIZE * id,\t\t\t\\\n+\t\t.io_reg = 0x4 + REG_SIZE * id,\t\t\\\n+\t\t.intr_cfg_reg = 0x8 + REG_SIZE * id,\t\t\\\n+\t\t.intr_status_reg = 0xc + REG_SIZE * id,\t\\\n+\t\t.intr_target_reg = 0x8 + REG_SIZE * id,\t\\\n+\t\t.mux_bit = 2,\t\t\t\\\n+\t\t.pull_bit = 0,\t\t\t\\\n+\t\t.drv_bit = 6,\t\t\t\\\n+\t\t.oe_bit = 9,\t\t\t\\\n+\t\t.in_bit = 0,\t\t\t\\\n+\t\t.out_bit = 1,\t\t\t\\\n+\t\t.intr_enable_bit = 0,\t\t\\\n+\t\t.intr_status_bit = 0,\t\t\\\n+\t\t.intr_target_bit = 5,\t\t\\\n+\t\t.intr_target_kpss_val = 3,\t\\\n+\t\t.intr_raw_status_bit = 4,\t\\\n+\t\t.intr_polarity_bit = 1,\t\t\\\n+\t\t.intr_detection_bit = 2,\t\\\n+\t\t.intr_detection_width = 2,\t\\\n+\t}\n+\n+static const struct pinctrl_pin_desc ipq9574_pins[] = {\n+\tPINCTRL_PIN(0, \"GPIO_0\"),\n+\tPINCTRL_PIN(1, \"GPIO_1\"),\n+\tPINCTRL_PIN(2, \"GPIO_2\"),\n+\tPINCTRL_PIN(3, \"GPIO_3\"),\n+\tPINCTRL_PIN(4, \"GPIO_4\"),\n+\tPINCTRL_PIN(5, \"GPIO_5\"),\n+\tPINCTRL_PIN(6, \"GPIO_6\"),\n+\tPINCTRL_PIN(7, \"GPIO_7\"),\n+\tPINCTRL_PIN(8, \"GPIO_8\"),\n+\tPINCTRL_PIN(9, \"GPIO_9\"),\n+\tPINCTRL_PIN(10, \"GPIO_10\"),\n+\tPINCTRL_PIN(11, \"GPIO_11\"),\n+\tPINCTRL_PIN(12, \"GPIO_12\"),\n+\tPINCTRL_PIN(13, \"GPIO_13\"),\n+\tPINCTRL_PIN(14, \"GPIO_14\"),\n+\tPINCTRL_PIN(15, \"GPIO_15\"),\n+\tPINCTRL_PIN(16, \"GPIO_16\"),\n+\tPINCTRL_PIN(17, \"GPIO_17\"),\n+\tPINCTRL_PIN(18, \"GPIO_18\"),\n+\tPINCTRL_PIN(19, \"GPIO_19\"),\n+\tPINCTRL_PIN(20, \"GPIO_20\"),\n+\tPINCTRL_PIN(21, \"GPIO_21\"),\n+\tPINCTRL_PIN(22, \"GPIO_22\"),\n+\tPINCTRL_PIN(23, \"GPIO_23\"),\n+\tPINCTRL_PIN(24, \"GPIO_24\"),\n+\tPINCTRL_PIN(25, \"GPIO_25\"),\n+\tPINCTRL_PIN(26, \"GPIO_26\"),\n+\tPINCTRL_PIN(27, \"GPIO_27\"),\n+\tPINCTRL_PIN(28, \"GPIO_28\"),\n+\tPINCTRL_PIN(29, \"GPIO_29\"),\n+\tPINCTRL_PIN(30, \"GPIO_30\"),\n+\tPINCTRL_PIN(31, \"GPIO_31\"),\n+\tPINCTRL_PIN(32, \"GPIO_32\"),\n+\tPINCTRL_PIN(33, \"GPIO_33\"),\n+\tPINCTRL_PIN(34, \"GPIO_34\"),\n+\tPINCTRL_PIN(35, \"GPIO_35\"),\n+\tPINCTRL_PIN(36, \"GPIO_36\"),\n+\tPINCTRL_PIN(37, \"GPIO_37\"),\n+\tPINCTRL_PIN(38, \"GPIO_38\"),\n+\tPINCTRL_PIN(39, \"GPIO_39\"),\n+\tPINCTRL_PIN(40, \"GPIO_40\"),\n+\tPINCTRL_PIN(41, \"GPIO_41\"),\n+\tPINCTRL_PIN(42, \"GPIO_42\"),\n+\tPINCTRL_PIN(43, \"GPIO_43\"),\n+\tPINCTRL_PIN(44, \"GPIO_44\"),\n+\tPINCTRL_PIN(45, \"GPIO_45\"),\n+\tPINCTRL_PIN(46, \"GPIO_46\"),\n+\tPINCTRL_PIN(47, \"GPIO_47\"),\n+\tPINCTRL_PIN(48, \"GPIO_48\"),\n+\tPINCTRL_PIN(49, \"GPIO_49\"),\n+\tPINCTRL_PIN(50, \"GPIO_50\"),\n+\tPINCTRL_PIN(51, \"GPIO_51\"),\n+\tPINCTRL_PIN(52, \"GPIO_52\"),\n+\tPINCTRL_PIN(53, \"GPIO_53\"),\n+\tPINCTRL_PIN(54, \"GPIO_54\"),\n+\tPINCTRL_PIN(55, \"GPIO_55\"),\n+\tPINCTRL_PIN(56, \"GPIO_56\"),\n+\tPINCTRL_PIN(57, \"GPIO_57\"),\n+\tPINCTRL_PIN(58, \"GPIO_58\"),\n+\tPINCTRL_PIN(59, \"GPIO_59\"),\n+\tPINCTRL_PIN(60, \"GPIO_60\"),\n+\tPINCTRL_PIN(61, \"GPIO_61\"),\n+\tPINCTRL_PIN(62, \"GPIO_62\"),\n+\tPINCTRL_PIN(63, \"GPIO_63\"),\n+\tPINCTRL_PIN(64, \"GPIO_64\"),\n+};\n+\n+#define DECLARE_MSM_GPIO_PINS(pin) \\\n+\tstatic const unsigned int gpio##pin##_pins[] = { pin }\n+DECLARE_MSM_GPIO_PINS(0);\n+DECLARE_MSM_GPIO_PINS(1);\n+DECLARE_MSM_GPIO_PINS(2);\n+DECLARE_MSM_GPIO_PINS(3);\n+DECLARE_MSM_GPIO_PINS(4);\n+DECLARE_MSM_GPIO_PINS(5);\n+DECLARE_MSM_GPIO_PINS(6);\n+DECLARE_MSM_GPIO_PINS(7);\n+DECLARE_MSM_GPIO_PINS(8);\n+DECLARE_MSM_GPIO_PINS(9);\n+DECLARE_MSM_GPIO_PINS(10);\n+DECLARE_MSM_GPIO_PINS(11);\n+DECLARE_MSM_GPIO_PINS(12);\n+DECLARE_MSM_GPIO_PINS(13);\n+DECLARE_MSM_GPIO_PINS(14);\n+DECLARE_MSM_GPIO_PINS(15);\n+DECLARE_MSM_GPIO_PINS(16);\n+DECLARE_MSM_GPIO_PINS(17);\n+DECLARE_MSM_GPIO_PINS(18);\n+DECLARE_MSM_GPIO_PINS(19);\n+DECLARE_MSM_GPIO_PINS(20);\n+DECLARE_MSM_GPIO_PINS(21);\n+DECLARE_MSM_GPIO_PINS(22);\n+DECLARE_MSM_GPIO_PINS(23);\n+DECLARE_MSM_GPIO_PINS(24);\n+DECLARE_MSM_GPIO_PINS(25);\n+DECLARE_MSM_GPIO_PINS(26);\n+DECLARE_MSM_GPIO_PINS(27);\n+DECLARE_MSM_GPIO_PINS(28);\n+DECLARE_MSM_GPIO_PINS(29);\n+DECLARE_MSM_GPIO_PINS(30);\n+DECLARE_MSM_GPIO_PINS(31);\n+DECLARE_MSM_GPIO_PINS(32);\n+DECLARE_MSM_GPIO_PINS(33);\n+DECLARE_MSM_GPIO_PINS(34);\n+DECLARE_MSM_GPIO_PINS(35);\n+DECLARE_MSM_GPIO_PINS(36);\n+DECLARE_MSM_GPIO_PINS(37);\n+DECLARE_MSM_GPIO_PINS(38);\n+DECLARE_MSM_GPIO_PINS(39);\n+DECLARE_MSM_GPIO_PINS(40);\n+DECLARE_MSM_GPIO_PINS(41);\n+DECLARE_MSM_GPIO_PINS(42);\n+DECLARE_MSM_GPIO_PINS(43);\n+DECLARE_MSM_GPIO_PINS(44);\n+DECLARE_MSM_GPIO_PINS(45);\n+DECLARE_MSM_GPIO_PINS(46);\n+DECLARE_MSM_GPIO_PINS(47);\n+DECLARE_MSM_GPIO_PINS(48);\n+DECLARE_MSM_GPIO_PINS(49);\n+DECLARE_MSM_GPIO_PINS(50);\n+DECLARE_MSM_GPIO_PINS(51);\n+DECLARE_MSM_GPIO_PINS(52);\n+DECLARE_MSM_GPIO_PINS(53);\n+DECLARE_MSM_GPIO_PINS(54);\n+DECLARE_MSM_GPIO_PINS(55);\n+DECLARE_MSM_GPIO_PINS(56);\n+DECLARE_MSM_GPIO_PINS(57);\n+DECLARE_MSM_GPIO_PINS(58);\n+DECLARE_MSM_GPIO_PINS(59);\n+DECLARE_MSM_GPIO_PINS(60);\n+DECLARE_MSM_GPIO_PINS(61);\n+DECLARE_MSM_GPIO_PINS(62);\n+DECLARE_MSM_GPIO_PINS(63);\n+DECLARE_MSM_GPIO_PINS(64);\n+\n+enum ipq9574_functions {\n+\tmsm_mux_atest_char,\n+\tmsm_mux_atest_char0,\n+\tmsm_mux_atest_char1,\n+\tmsm_mux_atest_char2,\n+\tmsm_mux_atest_char3,\n+\tmsm_mux_audio_pdm0,\n+\tmsm_mux_audio_pdm1,\n+\tmsm_mux_audio_pri,\n+\tmsm_mux_audio_sec,\n+\tmsm_mux_blsp0_spi,\n+\tmsm_mux_blsp0_uart,\n+\tmsm_mux_blsp1_i2c,\n+\tmsm_mux_blsp1_spi,\n+\tmsm_mux_blsp1_uart,\n+\tmsm_mux_blsp2_i2c,\n+\tmsm_mux_blsp2_spi,\n+\tmsm_mux_blsp2_uart,\n+\tmsm_mux_blsp3_i2c,\n+\tmsm_mux_blsp3_spi,\n+\tmsm_mux_blsp3_uart,\n+\tmsm_mux_blsp4_i2c,\n+\tmsm_mux_blsp4_spi,\n+\tmsm_mux_blsp4_uart,\n+\tmsm_mux_blsp5_i2c,\n+\tmsm_mux_blsp5_uart,\n+\tmsm_mux_cri_trng0,\n+\tmsm_mux_cri_trng1,\n+\tmsm_mux_cri_trng2,\n+\tmsm_mux_cri_trng3,\n+\tmsm_mux_cxc0,\n+\tmsm_mux_cxc1,\n+\tmsm_mux_dbg_out,\n+\tmsm_mux_dwc_ddrphy,\n+\tmsm_mux_gcc_plltest,\n+\tmsm_mux_gcc_tlmm,\n+\tmsm_mux_gpio,\n+\tmsm_mux_mac,\n+\tmsm_mux_mdc,\n+\tmsm_mux_mdio,\n+\tmsm_mux_pcie0_clk,\n+\tmsm_mux_pcie0_wake,\n+\tmsm_mux_pcie1_clk,\n+\tmsm_mux_pcie1_wake,\n+\tmsm_mux_pcie2_clk,\n+\tmsm_mux_pcie2_wake,\n+\tmsm_mux_pcie3_clk,\n+\tmsm_mux_pcie3_wake,\n+\tmsm_mux_prng_rosc0,\n+\tmsm_mux_prng_rosc1,\n+\tmsm_mux_prng_rosc2,\n+\tmsm_mux_prng_rosc3,\n+\tmsm_mux_pta,\n+\tmsm_mux_pwm,\n+\tmsm_mux_qdss_cti_trig_in_a0,\n+\tmsm_mux_qdss_cti_trig_in_a1,\n+\tmsm_mux_qdss_cti_trig_in_b0,\n+\tmsm_mux_qdss_cti_trig_in_b1,\n+\tmsm_mux_qdss_cti_trig_out_a0,\n+\tmsm_mux_qdss_cti_trig_out_a1,\n+\tmsm_mux_qdss_cti_trig_out_b0,\n+\tmsm_mux_qdss_cti_trig_out_b1,\n+\tmsm_mux_qdss_traceclk_a,\n+\tmsm_mux_qdss_traceclk_b,\n+\tmsm_mux_qdss_tracectl_a,\n+\tmsm_mux_qdss_tracectl_b,\n+\tmsm_mux_qdss_tracedata_a,\n+\tmsm_mux_qdss_tracedata_b,\n+\tmsm_mux_qspi_data,\n+\tmsm_mux_qspi_clk,\n+\tmsm_mux_qspi_cs,\n+\tmsm_mux_rx0,\n+\tmsm_mux_rx1,\n+\tmsm_mux_sdc_data,\n+\tmsm_mux_sdc_clk,\n+\tmsm_mux_sdc_cmd,\n+\tmsm_mux_sdc_rclk,\n+\tmsm_mux_tsens_max,\n+\tmsm_mux_wci20,\n+\tmsm_mux_wci21,\n+\tmsm_mux_wsa_swrm,\n+\tmsm_mux__,\n+};\n+\n+static const char * const gpio_groups[] = {\n+\t\"gpio0\", \"gpio1\", \"gpio2\", \"gpio3\", \"gpio4\", \"gpio5\", \"gpio6\", \"gpio7\",\n+\t\"gpio8\", \"gpio9\", \"gpio10\", \"gpio11\", \"gpio12\", \"gpio13\", \"gpio14\",\n+\t\"gpio15\", \"gpio16\", \"gpio17\", \"gpio18\", \"gpio19\", \"gpio20\", \"gpio21\",\n+\t\"gpio22\", \"gpio23\", \"gpio24\", \"gpio25\", \"gpio26\", \"gpio27\", \"gpio28\",\n+\t\"gpio29\", \"gpio30\", \"gpio31\", \"gpio32\", \"gpio33\", \"gpio34\", \"gpio35\",\n+\t\"gpio36\", \"gpio37\", \"gpio38\", \"gpio39\", \"gpio40\", \"gpio41\", \"gpio42\",\n+\t\"gpio43\", \"gpio44\", \"gpio45\", \"gpio46\", \"gpio47\", \"gpio48\", \"gpio49\",\n+\t\"gpio50\", \"gpio51\", \"gpio52\", \"gpio53\", \"gpio54\", \"gpio55\", \"gpio56\",\n+\t\"gpio57\", \"gpio58\", \"gpio59\", \"gpio60\", \"gpio61\", \"gpio62\", \"gpio63\",\n+\t\"gpio64\",\n+};\n+\n+static const char * const sdc_data_groups[] = {\n+\t\"gpio0\",\n+\t\"gpio1\",\n+\t\"gpio2\",\n+\t\"gpio3\",\n+\t\"gpio6\",\n+\t\"gpio7\",\n+\t\"gpio8\",\n+\t\"gpio9\",\n+};\n+\n+static const char * const qspi_data_groups[] = {\n+\t\"gpio0\",\n+\t\"gpio1\",\n+\t\"gpio2\",\n+\t\"gpio3\",\n+};\n+\n+static const char * const qdss_traceclk_b_groups[] = {\n+\t\"gpio0\",\n+};\n+\n+static const char * const qdss_tracectl_b_groups[] = {\n+\t\"gpio1\",\n+};\n+\n+static const char * const qdss_tracedata_b_groups[] = {\n+\t\"gpio2\", \"gpio3\", \"gpio4\", \"gpio5\", \"gpio6\", \"gpio7\", \"gpio8\", \"gpio9\",\n+\t\"gpio10\", \"gpio11\", \"gpio12\", \"gpio13\", \"gpio14\", \"gpio15\", \"gpio16\",\n+\t\"gpio17\",\n+};\n+\n+static const char * const sdc_cmd_groups[] = {\n+\t\"gpio4\",\n+};\n+\n+static const char * const qspi_cs_groups[] = {\n+\t\"gpio4\",\n+};\n+\n+static const char * const sdc_clk_groups[] = {\n+\t\"gpio5\",\n+};\n+\n+static const char * const qspi_clk_groups[] = {\n+\t\"gpio5\",\n+};\n+\n+static const char * const sdc_rclk_groups[] = {\n+\t\"gpio10\",\n+};\n+\n+static const char * const blsp0_spi_groups[] = {\n+\t\"gpio11\", \"gpio12\", \"gpio13\", \"gpio14\",\n+};\n+\n+static const char * const blsp0_uart_groups[] = {\n+\t\"gpio11\", \"gpio12\", \"gpio13\", \"gpio14\",\n+};\n+\n+static const char * const blsp3_spi_groups[] = {\n+\t\"gpio15\", \"gpio16\", \"gpio17\", \"gpio18\", \"gpio19\", \"gpio20\", \"gpio21\",\n+};\n+\n+static const char * const blsp3_i2c_groups[] = {\n+\t\"gpio15\", \"gpio16\",\n+};\n+\n+static const char * const blsp3_uart_groups[] = {\n+\t\"gpio15\", \"gpio16\", \"gpio17\", \"gpio18\",\n+};\n+\n+static const char * const dbg_out_groups[] = {\n+\t\"gpio17\",\n+};\n+\n+static const char * const cri_trng0_groups[] = {\n+\t\"gpio20\", \"gpio38\",\n+};\n+\n+static const char * const cri_trng1_groups[] = {\n+\t\"gpio21\", \"gpio34\",\n+};\n+\n+static const char * const pcie0_clk_groups[] = {\n+\t\"gpio22\",\n+};\n+\n+static const char * const pta_groups[] = {\n+\t\"gpio22\", \"gpio23\", \"gpio24\", \"gpio54\", \"gpio55\", \"gpio56\", \"gpio61\",\n+\t\"gpio62\", \"gpio63\",\n+};\n+\n+static const char * const wci21_groups[] = {\n+\t\"gpio23\", \"gpio24\",\n+};\n+\n+static const char * const cxc0_groups[] = {\n+\t\"gpio23\", \"gpio24\",\n+};\n+\n+static const char * const pcie0_wake_groups[] = {\n+\t\"gpio24\",\n+};\n+\n+static const char * const qdss_cti_trig_out_b0_groups[] = {\n+\t\"gpio24\",\n+};\n+\n+static const char * const pcie1_clk_groups[] = {\n+\t\"gpio25\",\n+};\n+\n+static const char * const qdss_cti_trig_in_b0_groups[] = {\n+\t\"gpio25\",\n+};\n+\n+static const char * const atest_char0_groups[] = {\n+\t\"gpio26\",\n+};\n+\n+static const char * const qdss_cti_trig_out_b1_groups[] = {\n+\t\"gpio26\",\n+};\n+\n+static const char * const pcie1_wake_groups[] = {\n+\t\"gpio27\",\n+};\n+\n+static const char * const atest_char1_groups[] = {\n+\t\"gpio27\",\n+};\n+\n+static const char * const qdss_cti_trig_in_b1_groups[] = {\n+\t\"gpio27\",\n+};\n+\n+static const char * const pcie2_clk_groups[] = {\n+\t\"gpio28\",\n+};\n+\n+static const char * const atest_char2_groups[] = {\n+\t\"gpio28\",\n+};\n+\n+static const char * const atest_char3_groups[] = {\n+\t\"gpio29\",\n+};\n+\n+static const char * const pcie2_wake_groups[] = {\n+\t\"gpio30\",\n+};\n+\n+static const char * const pwm_groups[] = {\n+\t\"gpio30\", \"gpio31\", \"gpio32\", \"gpio33\", \"gpio44\", \"gpio45\", \"gpio46\",\n+\t\"gpio47\", \"gpio50\", \"gpio51\", \"gpio52\", \"gpio53\", \"gpio54\", \"gpio55\",\n+\t\"gpio56\", \"gpio57\", \"gpio58\", \"gpio59\", \"gpio60\",\n+};\n+\n+static const char * const atest_char_groups[] = {\n+\t\"gpio30\",\n+};\n+\n+static const char * const pcie3_clk_groups[] = {\n+\t\"gpio31\",\n+};\n+\n+static const char * const qdss_cti_trig_in_a1_groups[] = {\n+\t\"gpio31\",\n+};\n+\n+static const char * const qdss_cti_trig_out_a1_groups[] = {\n+\t\"gpio32\",\n+};\n+\n+static const char * const pcie3_wake_groups[] = {\n+\t\"gpio33\",\n+};\n+\n+static const char * const qdss_cti_trig_in_a0_groups[] = {\n+\t\"gpio33\",\n+};\n+\n+static const char * const blsp2_uart_groups[] = {\n+\t\"gpio34\", \"gpio35\",\n+};\n+\n+static const char * const blsp2_i2c_groups[] = {\n+\t\"gpio34\", \"gpio35\",\n+};\n+\n+static const char * const blsp2_spi_groups[] = {\n+\t\"gpio34\", \"gpio35\", \"gpio36\", \"gpio37\",\n+};\n+\n+static const char * const blsp1_uart_groups[] = {\n+\t\"gpio34\", \"gpio35\", \"gpio36\", \"gpio37\",\n+};\n+\n+static const char * const qdss_cti_trig_out_a0_groups[] = {\n+\t\"gpio34\",\n+};\n+\n+static const char * const cri_trng2_groups[] = {\n+\t\"gpio35\",\n+};\n+\n+static const char * const blsp1_i2c_groups[] = {\n+\t\"gpio36\", \"gpio37\",\n+};\n+\n+static const char * const cri_trng3_groups[] = {\n+\t\"gpio36\",\n+};\n+\n+static const char * const dwc_ddrphy_groups[] = {\n+\t\"gpio37\",\n+};\n+\n+static const char * const mdc_groups[] = {\n+\t\"gpio38\",\n+};\n+\n+static const char * const mdio_groups[] = {\n+\t\"gpio39\",\n+};\n+\n+static const char * const audio_pri_groups[] = {\n+\t\"gpio40\", \"gpio41\", \"gpio42\", \"gpio43\", \"gpio61\", \"gpio61\",\n+};\n+\n+static const char * const audio_pdm0_groups[] = {\n+\t\"gpio40\", \"gpio41\", \"gpio42\", \"gpio43\",\n+};\n+\n+static const char * const qdss_traceclk_a_groups[] = {\n+\t\"gpio43\",\n+};\n+\n+static const char * const audio_sec_groups[] = {\n+\t\"gpio44\", \"gpio45\", \"gpio46\", \"gpio47\", \"gpio62\", \"gpio62\",\n+};\n+\n+static const char * const wsa_swrm_groups[] = {\n+\t\"gpio44\", \"gpio45\",\n+};\n+\n+static const char * const qdss_tracectl_a_groups[] = {\n+\t\"gpio44\",\n+};\n+\n+static const char * const qdss_tracedata_a_groups[] = {\n+\t\"gpio45\", \"gpio46\", \"gpio47\", \"gpio48\", \"gpio49\", \"gpio50\", \"gpio51\",\n+\t\"gpio52\", \"gpio53\", \"gpio54\", \"gpio55\", \"gpio56\", \"gpio57\", \"gpio58\",\n+\t\"gpio59\", \"gpio60\",\n+};\n+\n+static const char * const rx1_groups[] = {\n+\t\"gpio46\",\n+};\n+\n+static const char * const mac_groups[] = {\n+\t\"gpio46\", \"gpio47\", \"gpio57\", \"gpio58\",\n+};\n+\n+static const char * const blsp5_i2c_groups[] = {\n+\t\"gpio48\", \"gpio49\",\n+};\n+\n+static const char * const blsp5_uart_groups[] = {\n+\t\"gpio48\", \"gpio49\",\n+};\n+\n+static const char * const blsp4_uart_groups[] = {\n+\t\"gpio50\", \"gpio51\", \"gpio52\", \"gpio53\",\n+};\n+\n+static const char * const blsp4_i2c_groups[] = {\n+\t\"gpio50\", \"gpio51\",\n+};\n+\n+static const char * const blsp4_spi_groups[] = {\n+\t\"gpio50\", \"gpio51\", \"gpio52\", \"gpio53\",\n+};\n+\n+static const char * const wci20_groups[] = {\n+\t\"gpio57\", \"gpio58\",\n+};\n+\n+static const char * const cxc1_groups[] = {\n+\t\"gpio57\", \"gpio58\",\n+};\n+\n+static const char * const rx0_groups[] = {\n+\t\"gpio59\",\n+};\n+\n+static const char * const prng_rosc0_groups[] = {\n+\t\"gpio60\",\n+};\n+\n+static const char * const gcc_plltest_groups[] = {\n+\t\"gpio60\", \"gpio62\",\n+};\n+\n+static const char * const blsp1_spi_groups[] = {\n+\t\"gpio61\", \"gpio62\", \"gpio63\", \"gpio64\",\n+};\n+\n+static const char * const audio_pdm1_groups[] = {\n+\t\"gpio61\", \"gpio62\", \"gpio63\", \"gpio64\",\n+};\n+\n+static const char * const prng_rosc1_groups[] = {\n+\t\"gpio61\",\n+};\n+\n+static const char * const gcc_tlmm_groups[] = {\n+\t\"gpio61\",\n+};\n+\n+static const char * const prng_rosc2_groups[] = {\n+\t\"gpio62\",\n+};\n+\n+static const char * const prng_rosc3_groups[] = {\n+\t\"gpio63\",\n+};\n+\n+static const char * const tsens_max_groups[] = {\n+\t\"gpio64\",\n+};\n+\n+static const struct msm_function ipq9574_functions[] = {\n+\tFUNCTION(atest_char),\n+\tFUNCTION(atest_char0),\n+\tFUNCTION(atest_char1),\n+\tFUNCTION(atest_char2),\n+\tFUNCTION(atest_char3),\n+\tFUNCTION(audio_pdm0),\n+\tFUNCTION(audio_pdm1),\n+\tFUNCTION(audio_pri),\n+\tFUNCTION(audio_sec),\n+\tFUNCTION(blsp0_spi),\n+\tFUNCTION(blsp0_uart),\n+\tFUNCTION(blsp1_i2c),\n+\tFUNCTION(blsp1_spi),\n+\tFUNCTION(blsp1_uart),\n+\tFUNCTION(blsp2_i2c),\n+\tFUNCTION(blsp2_spi),\n+\tFUNCTION(blsp2_uart),\n+\tFUNCTION(blsp3_i2c),\n+\tFUNCTION(blsp3_spi),\n+\tFUNCTION(blsp3_uart),\n+\tFUNCTION(blsp4_i2c),\n+\tFUNCTION(blsp4_spi),\n+\tFUNCTION(blsp4_uart),\n+\tFUNCTION(blsp5_i2c),\n+\tFUNCTION(blsp5_uart),\n+\tFUNCTION(cri_trng0),\n+\tFUNCTION(cri_trng1),\n+\tFUNCTION(cri_trng2),\n+\tFUNCTION(cri_trng3),\n+\tFUNCTION(cxc0),\n+\tFUNCTION(cxc1),\n+\tFUNCTION(dbg_out),\n+\tFUNCTION(dwc_ddrphy),\n+\tFUNCTION(gcc_plltest),\n+\tFUNCTION(gcc_tlmm),\n+\tFUNCTION(gpio),\n+\tFUNCTION(mac),\n+\tFUNCTION(mdc),\n+\tFUNCTION(mdio),\n+\tFUNCTION(pcie0_clk),\n+\tFUNCTION(pcie0_wake),\n+\tFUNCTION(pcie1_clk),\n+\tFUNCTION(pcie1_wake),\n+\tFUNCTION(pcie2_clk),\n+\tFUNCTION(pcie2_wake),\n+\tFUNCTION(pcie3_clk),\n+\tFUNCTION(pcie3_wake),\n+\tFUNCTION(prng_rosc0),\n+\tFUNCTION(prng_rosc1),\n+\tFUNCTION(prng_rosc2),\n+\tFUNCTION(prng_rosc3),\n+\tFUNCTION(pta),\n+\tFUNCTION(pwm),\n+\tFUNCTION(qdss_cti_trig_in_a0),\n+\tFUNCTION(qdss_cti_trig_in_a1),\n+\tFUNCTION(qdss_cti_trig_in_b0),\n+\tFUNCTION(qdss_cti_trig_in_b1),\n+\tFUNCTION(qdss_cti_trig_out_a0),\n+\tFUNCTION(qdss_cti_trig_out_a1),\n+\tFUNCTION(qdss_cti_trig_out_b0),\n+\tFUNCTION(qdss_cti_trig_out_b1),\n+\tFUNCTION(qdss_traceclk_a),\n+\tFUNCTION(qdss_traceclk_b),\n+\tFUNCTION(qdss_tracectl_a),\n+\tFUNCTION(qdss_tracectl_b),\n+\tFUNCTION(qdss_tracedata_a),\n+\tFUNCTION(qdss_tracedata_b),\n+\tFUNCTION(qspi_data),\n+\tFUNCTION(qspi_clk),\n+\tFUNCTION(qspi_cs),\n+\tFUNCTION(rx0),\n+\tFUNCTION(rx1),\n+\tFUNCTION(sdc_data),\n+\tFUNCTION(sdc_clk),\n+\tFUNCTION(sdc_cmd),\n+\tFUNCTION(sdc_rclk),\n+\tFUNCTION(tsens_max),\n+\tFUNCTION(wci20),\n+\tFUNCTION(wci21),\n+\tFUNCTION(wsa_swrm),\n+};\n+\n+static const struct msm_pingroup ipq9574_groups[] = {\n+\tPINGROUP(0, sdc_data, qspi_data, qdss_traceclk_b, _, _, _, _, _, _),\n+\tPINGROUP(1, sdc_data, qspi_data, qdss_tracectl_b, _, _, _, _, _, _),\n+\tPINGROUP(2, sdc_data, qspi_data, qdss_tracedata_b, _, _, _, _, _, _),\n+\tPINGROUP(3, sdc_data, qspi_data, qdss_tracedata_b, _, _, _, _, _, _),\n+\tPINGROUP(4, sdc_cmd, qspi_cs, qdss_tracedata_b, _, _, _, _, _, _),\n+\tPINGROUP(5, sdc_clk, qspi_clk, qdss_tracedata_b, _, _, _, _, _, _),\n+\tPINGROUP(6, sdc_data, qdss_tracedata_b, _, _, _, _, _, _, _),\n+\tPINGROUP(7, sdc_data, qdss_tracedata_b, _, _, _, _, _, _, _),\n+\tPINGROUP(8, sdc_data, qdss_tracedata_b, _, _, _, _, _, _, _),\n+\tPINGROUP(9, sdc_data, qdss_tracedata_b, _, _, _, _, _, _, _),\n+\tPINGROUP(10, sdc_rclk, qdss_tracedata_b, _, _, _, _, _, _, _),\n+\tPINGROUP(11, blsp0_spi, blsp0_uart, qdss_tracedata_b, _, _, _, _, _, _),\n+\tPINGROUP(12, blsp0_spi, blsp0_uart, qdss_tracedata_b, _, _, _, _, _, _),\n+\tPINGROUP(13, blsp0_spi, blsp0_uart, qdss_tracedata_b, _, _, _, _, _, _),\n+\tPINGROUP(14, blsp0_spi, blsp0_uart, qdss_tracedata_b, _, _, _, _, _, _),\n+\tPINGROUP(15, blsp3_spi, blsp3_i2c, blsp3_uart, qdss_tracedata_b, _, _, _, _, _),\n+\tPINGROUP(16, blsp3_spi, blsp3_i2c, blsp3_uart, qdss_tracedata_b, _, _, _, _, _),\n+\tPINGROUP(17, blsp3_spi, blsp3_uart, dbg_out, qdss_tracedata_b, _, _, _, _, _),\n+\tPINGROUP(18, blsp3_spi, blsp3_uart, _, _, _, _, _, _, _),\n+\tPINGROUP(19, blsp3_spi, _, _, _, _, _, _, _, _),\n+\tPINGROUP(20, blsp3_spi, _, cri_trng0, _, _, _, _, _, _),\n+\tPINGROUP(21, blsp3_spi, _, cri_trng1, _, _, _, _, _, _),\n+\tPINGROUP(22, pcie0_clk, _, pta, _, _, _, _, _, _),\n+\tPINGROUP(23, _, pta, wci21, cxc0, _, _, _, _, _),\n+\tPINGROUP(24, pcie0_wake, _, pta, wci21, cxc0, _, qdss_cti_trig_out_b0, _, _),\n+\tPINGROUP(25, pcie1_clk, _, _, qdss_cti_trig_in_b0, _, _, _, _, _),\n+\tPINGROUP(26, _, atest_char0, _, qdss_cti_trig_out_b1, _, _, _, _, _),\n+\tPINGROUP(27, pcie1_wake, _, atest_char1, qdss_cti_trig_in_b1, _, _, _, _, _),\n+\tPINGROUP(28, pcie2_clk, atest_char2, _, _, _, _, _, _, _),\n+\tPINGROUP(29, atest_char3, _, _, _, _, _, _, _, _),\n+\tPINGROUP(30, pcie2_wake, pwm, atest_char, _, _, _, _, _, _),\n+\tPINGROUP(31, pcie3_clk, pwm, _, qdss_cti_trig_in_a1, _, _, _, _, _),\n+\tPINGROUP(32, pwm, _, qdss_cti_trig_out_a1, _, _, _, _, _, _),\n+\tPINGROUP(33, pcie3_wake, pwm, _, qdss_cti_trig_in_a0, _, _, _, _, _),\n+\tPINGROUP(34, blsp2_uart, blsp2_i2c, blsp2_spi, blsp1_uart, _, cri_trng1, qdss_cti_trig_out_a0, _, _),\n+\tPINGROUP(35, blsp2_uart, blsp2_i2c, blsp2_spi, blsp1_uart, _, cri_trng2, _, _, _),\n+\tPINGROUP(36, blsp1_uart, blsp1_i2c, blsp2_spi, _, cri_trng3, _, _, _, _),\n+\tPINGROUP(37, blsp1_uart, blsp1_i2c, blsp2_spi, _, dwc_ddrphy, _, _, _, _),\n+\tPINGROUP(38, mdc, _, cri_trng0, _, _, _, _, _, _),\n+\tPINGROUP(39, mdio, _, _, _, _, _, _, _, _),\n+\tPINGROUP(40, audio_pri, audio_pdm0, _, _, _, _, _, _, _),\n+\tPINGROUP(41, audio_pri, audio_pdm0, _, _, _, _, _, _, _),\n+\tPINGROUP(42, audio_pri, audio_pdm0, _, _, _, _, _, _, _),\n+\tPINGROUP(43, audio_pri, audio_pdm0, _, qdss_traceclk_a, _, _, _, _, _),\n+\tPINGROUP(44, pwm, audio_sec, wsa_swrm, _, qdss_tracectl_a, _, _, _, _),\n+\tPINGROUP(45, pwm, audio_sec, wsa_swrm, _, qdss_tracedata_a, _, _, _, _),\n+\tPINGROUP(46, pwm, audio_sec, rx1, mac, _, qdss_tracedata_a, _, _, _),\n+\tPINGROUP(47, pwm, audio_sec, mac, _, qdss_tracedata_a, _, _, _, _),\n+\tPINGROUP(48, blsp5_i2c, blsp5_uart, _, qdss_tracedata_a, _, _, _, _, _),\n+\tPINGROUP(49, blsp5_i2c, blsp5_uart, _, qdss_tracedata_a, _, _, _, _, _),\n+\tPINGROUP(50, blsp4_uart, blsp4_i2c, blsp4_spi, pwm, qdss_tracedata_a, _, _, _, _),\n+\tPINGROUP(51, blsp4_uart, blsp4_i2c, blsp4_spi, pwm, qdss_tracedata_a, _, _, _, _),\n+\tPINGROUP(52, blsp4_uart, blsp4_spi, pwm, qdss_tracedata_a, _, _, _, _, _),\n+\tPINGROUP(53, blsp4_uart, blsp4_spi, pwm, qdss_tracedata_a, _, _, _, _, _),\n+\tPINGROUP(54, pta, pwm, qdss_tracedata_a, _, _, _, _, _, _),\n+\tPINGROUP(55, pta, pwm, qdss_tracedata_a, _, _, _, _, _, _),\n+\tPINGROUP(56, pta, pwm, qdss_tracedata_a, _, _, _, _, _, _),\n+\tPINGROUP(57, wci20, cxc1, mac, pwm, qdss_tracedata_a, _, _, _, _),\n+\tPINGROUP(58, wci20, cxc1, mac, pwm, qdss_tracedata_a, _, _, _, _),\n+\tPINGROUP(59, rx0, pwm, qdss_tracedata_a, _, _, _, _, _, _),\n+\tPINGROUP(60, pwm, prng_rosc0, qdss_tracedata_a, _, gcc_plltest, _, _, _, _),\n+\tPINGROUP(61, blsp1_spi, audio_pri, audio_pdm1, audio_pri, pta, prng_rosc1, gcc_tlmm, _, _),\n+\tPINGROUP(62, blsp1_spi, audio_sec, audio_pdm1, audio_sec, pta, prng_rosc2, gcc_plltest, _, _),\n+\tPINGROUP(63, blsp1_spi, audio_pdm1, pta, prng_rosc3, _, _, _, _, _),\n+\tPINGROUP(64, blsp1_spi, audio_pdm1, tsens_max, _, _, _, _, _, _),\n+};\n+\n+/* Reserving GPIO59 for controlling the QFPROM LDO regulator */\n+static const int ipq9574_reserved_gpios[] = {\n+\t59, -1\n+};\n+\n+static const struct msm_pinctrl_soc_data ipq9574_pinctrl = {\n+\t.pins = ipq9574_pins,\n+\t.npins = ARRAY_SIZE(ipq9574_pins),\n+\t.functions = ipq9574_functions,\n+\t.nfunctions = ARRAY_SIZE(ipq9574_functions),\n+\t.groups = ipq9574_groups,\n+\t.ngroups = ARRAY_SIZE(ipq9574_groups),\n+\t.reserved_gpios = ipq9574_reserved_gpios,\n+\t.ngpios = 65,\n+};\n+\n+static int ipq9574_pinctrl_probe(struct platform_device *pdev)\n+{\n+\treturn msm_pinctrl_probe(pdev, &ipq9574_pinctrl);\n+}\n+\n+static const struct of_device_id ipq9574_pinctrl_of_match[] = {\n+\t{ .compatible = \"qcom,ipq9574-tlmm\", },\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(of, ipq9574_pinctrl_of_match);\n+\n+static struct platform_driver ipq9574_pinctrl_driver = {\n+\t.driver = {\n+\t\t.name = \"ipq9574-tlmm\",\n+\t\t.of_match_table = ipq9574_pinctrl_of_match,\n+\t},\n+\t.probe = ipq9574_pinctrl_probe,\n+\t.remove = msm_pinctrl_remove,\n+};\n+\n+static int __init ipq9574_pinctrl_init(void)\n+{\n+\treturn platform_driver_register(&ipq9574_pinctrl_driver);\n+}\n+arch_initcall(ipq9574_pinctrl_init);\n+\n+static void __exit ipq9574_pinctrl_exit(void)\n+{\n+\tplatform_driver_unregister(&ipq9574_pinctrl_driver);\n+}\n+module_exit(ipq9574_pinctrl_exit);\n+\n+MODULE_DESCRIPTION(\"QTI IPQ9574 TLMM driver\");\n+MODULE_LICENSE(\"GPL\");\n", "prefixes": [ "V9", "4/6" ] }