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{
    "id": 1744102,
    "url": "http://patchwork.ozlabs.org/api/patches/1744102/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20230217075835.460-4-quic_kathirav@quicinc.com/",
    "project": {
        "id": 42,
        "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api",
        "name": "Linux GPIO development",
        "link_name": "linux-gpio",
        "list_id": "linux-gpio.vger.kernel.org",
        "list_email": "linux-gpio@vger.kernel.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": "",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20230217075835.460-4-quic_kathirav@quicinc.com>",
    "list_archive_url": null,
    "date": "2023-02-17T07:58:31",
    "name": "[V5,3/7] clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "c39579cf79bf526295e0a38a08102f94653b65d1",
    "submitter": {
        "id": 83327,
        "url": "http://patchwork.ozlabs.org/api/people/83327/?format=api",
        "name": "Kathiravan Thirumoorthy",
        "email": "quic_kathirav@quicinc.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20230217075835.460-4-quic_kathirav@quicinc.com/mbox/",
    "series": [
        {
            "id": 342454,
            "url": "http://patchwork.ozlabs.org/api/series/342454/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=342454",
            "date": "2023-02-17T07:58:28",
            "name": "Add minimal boot support for IPQ5332",
            "version": 5,
            "mbox": "http://patchwork.ozlabs.org/series/342454/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/1744102/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/1744102/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Kathiravan T <quic_kathirav@quicinc.com>",
        "To": "<krzysztof.kozlowski@linaro.org>, <agross@kernel.org>,\n        <andersson@kernel.org>, <konrad.dybcio@linaro.org>,\n        <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,\n        <mturquette@baylibre.com>, <sboyd@kernel.org>,\n        <linus.walleij@linaro.org>, <catalin.marinas@arm.com>,\n        <will@kernel.org>, <shawnguo@kernel.org>, <arnd@arndb.de>,\n        <dmitry.baryshkov@linaro.org>, <marcel.ziswiler@toradex.com>,\n        <nfraprado@collabora.com>, <robimarko@gmail.com>,\n        <quic_gurus@quicinc.com>, <linux-arm-msm@vger.kernel.org>,\n        <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n        <linux-clk@vger.kernel.org>, <linux-gpio@vger.kernel.org>,\n        <linux-arm-kernel@lists.infradead.org>",
        "CC": "<quic_varada@quicinc.com>, <quic_srichara@quicinc.com>,\n        Kathiravan T <quic_kathirav@quicinc.com>",
        "Subject": "[PATCH V5 3/7] clk: qcom: add Global Clock controller (GCC) driver\n for IPQ5332 SoC",
        "Date": "Fri, 17 Feb 2023 13:28:31 +0530",
        "Message-ID": "<20230217075835.460-4-quic_kathirav@quicinc.com>",
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        "References": "<20230217075835.460-1-quic_kathirav@quicinc.com>",
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        "X-Mailing-List": "linux-gpio@vger.kernel.org"
    },
    "content": "Add support for the global clock controller found on IPQ5332 SoC.\n\nSigned-off-by: Kathiravan T <quic_kathirav@quicinc.com>\n---\nChanges in V5:\n\t- There was one instance where the parent_data is used, replaced\n\t  that parent_hws\n\nChanges in V4:\n\t- Used clk_regmap_phy_mux and its corresponding ops\n\t  clk_regmap_phy_mux_ops for USB and PCIE pipe clocks\n\t- Due to the above change, removed the unused the parent_data and\n\t  parent_map structures\n\t- Replaced parent_names with parent_hws\n\t- Fixed the DT_PCIE_2LANE_PHY_PIPE_X1_CLK name to match with\n\t  binding\n\t- Added a space between ')' and '{' throughout the file\n\nChanges in V3:\n\t- As I mentined the bindings, changes need to be done in V2 got\n\t  missed out and same has been done in V3, to call out\n\t  specifically dropped the CLK_IS_CRITICAL and dropped the\n\t  gcc_apss_ahb_clk, its source clock and gcc_apss_axi_clk\n\t- Used gcc_parent_data_xo wherever applicable and dropped the\n\t  duplicate entries\n\t- dropped the unused parent_map_10 and parent_data_10\n\t- Used qcom_cc_probe instead of qcom_cc_really_probe\n\nChanges in V2:\n\t- Added the 'dependes on' for Kconfig symbol\n\t- Dropped the CLK_IS_CRITICAL flag throughout the file\n\t- Dropped the gcc_apss_ahb_clk and gcc_apss_axi_clk as these are\n\t  managed by bootloaders\n\n drivers/clk/qcom/Kconfig       |    8 +\n drivers/clk/qcom/Makefile      |    1 +\n drivers/clk/qcom/gcc-ipq5332.c | 3813 ++++++++++++++++++++++++++++++++\n 3 files changed, 3822 insertions(+)\n create mode 100644 drivers/clk/qcom/gcc-ipq5332.c",
    "diff": "diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig\nindex 5ab4b7dfe3c2..10da46fa702e 100644\n--- a/drivers/clk/qcom/Kconfig\n+++ b/drivers/clk/qcom/Kconfig\n@@ -141,6 +141,14 @@ config IPQ_GCC_4019\n \t  Say Y if you want to use peripheral devices such as UART, SPI,\n \t  i2c, USB, SD/eMMC, etc.\n \n+config IPQ_GCC_5332\n+\ttristate \"IPQ5332 Global Clock Controller\"\n+\tdepends on ARM64 || COMPILE_TEST\n+\thelp\n+\t  Support for the global clock controller on ipq5332 devices.\n+\t  Say Y if you want to use peripheral devices such as UART, SPI,\n+\t  i2c, USB, SD/eMMC, etc.\n+\n config IPQ_GCC_6018\n \ttristate \"IPQ6018 Global Clock Controller\"\n \thelp\ndiff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile\nindex c743805a9cbb..d7aa0f086805 100644\n--- a/drivers/clk/qcom/Makefile\n+++ b/drivers/clk/qcom/Makefile\n@@ -24,6 +24,7 @@ obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o\n obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o\n obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o\n obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o\n+obj-$(CONFIG_IPQ_GCC_5332) += gcc-ipq5332.o\n obj-$(CONFIG_IPQ_GCC_6018) += gcc-ipq6018.o\n obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o\n obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o\ndiff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c\nnew file mode 100644\nindex 000000000000..9e4baea33937\n--- /dev/null\n+++ b/drivers/clk/qcom/gcc-ipq5332.c\n@@ -0,0 +1,3813 @@\n+// SPDX-License-Identifier: GPL-2.0-only\n+/*\n+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.\n+ */\n+\n+#include <linux/clk-provider.h>\n+#include <linux/module.h>\n+#include <linux/of_device.h>\n+#include <linux/regmap.h>\n+\n+#include <dt-bindings/clock/qcom,ipq5332-gcc.h>\n+\n+#include \"clk-alpha-pll.h\"\n+#include \"clk-branch.h\"\n+#include \"clk-rcg.h\"\n+#include \"clk-regmap.h\"\n+#include \"clk-regmap-divider.h\"\n+#include \"clk-regmap-mux.h\"\n+#include \"clk-regmap-phy-mux.h\"\n+#include \"reset.h\"\n+\n+enum {\n+\tDT_SLEEP_CLK,\n+\tDT_XO,\n+\tDT_PCIE_2LANE_PHY_PIPE_CLK,\n+\tDT_PCIE_2LANE_PHY_PIPE_CLK_X1,\n+\tDT_USB_PCIE_WRAPPER_PIPE_CLK,\n+};\n+\n+enum {\n+\tP_PCIE3X2_PIPE,\n+\tP_PCIE3X1_0_PIPE,\n+\tP_PCIE3X1_1_PIPE,\n+\tP_USB3PHY_0_PIPE,\n+\tP_CORE_BI_PLL_TEST_SE,\n+\tP_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC,\n+\tP_GPLL0_OUT_AUX,\n+\tP_GPLL0_OUT_MAIN,\n+\tP_GPLL2_OUT_AUX,\n+\tP_GPLL2_OUT_MAIN,\n+\tP_GPLL4_OUT_AUX,\n+\tP_GPLL4_OUT_MAIN,\n+\tP_SLEEP_CLK,\n+\tP_XO,\n+};\n+\n+static const struct clk_parent_data gcc_parent_data_xo = { .index = DT_XO };\n+\n+static struct clk_alpha_pll gpll0_main = {\n+\t.offset = 0x20000,\n+\t.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],\n+\t.clkr = {\n+\t\t.enable_reg = 0xb000,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gpll0_main\",\n+\t\t\t.parent_data = &gcc_parent_data_xo,\n+\t\t\t.num_parents = 1,\n+\t\t\t.ops = &clk_alpha_pll_stromer_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_fixed_factor gpll0_div2 = {\n+\t.mult = 1,\n+\t.div = 2,\n+\t.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"gpll0_div2\",\n+\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gpll0_main.clkr.hw },\n+\t\t.num_parents = 1,\n+\t\t.ops = &clk_fixed_factor_ops,\n+\t\t.flags = CLK_SET_RATE_PARENT,\n+\t},\n+};\n+\n+static struct clk_alpha_pll_postdiv gpll0 = {\n+\t.offset = 0x20000,\n+\t.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],\n+\t.width = 4,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"gpll0\",\n+\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gpll0_main.clkr.hw },\n+\t\t.num_parents = 1,\n+\t\t.ops = &clk_alpha_pll_postdiv_ro_ops,\n+\t\t.flags = CLK_SET_RATE_PARENT,\n+\t},\n+};\n+\n+static struct clk_alpha_pll gpll2_main = {\n+\t.offset = 0x21000,\n+\t.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],\n+\t.clkr = {\n+\t\t.enable_reg = 0xb000,\n+\t\t.enable_mask = BIT(1),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gpll2\",\n+\t\t\t.parent_data = &gcc_parent_data_xo,\n+\t\t\t.num_parents = 1,\n+\t\t\t.ops = &clk_alpha_pll_stromer_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_alpha_pll_postdiv gpll2 = {\n+\t.offset = 0x21000,\n+\t.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],\n+\t.width = 4,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"gpll2_main\",\n+\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gpll2_main.clkr.hw },\n+\t\t.num_parents = 1,\n+\t\t.ops = &clk_alpha_pll_postdiv_ro_ops,\n+\t\t.flags = CLK_SET_RATE_PARENT,\n+\t},\n+};\n+\n+static struct clk_alpha_pll gpll4_main = {\n+\t.offset = 0x22000,\n+\t.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],\n+\t.clkr = {\n+\t\t.enable_reg = 0xb000,\n+\t\t.enable_mask = BIT(2),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gpll4_main\",\n+\t\t\t.parent_data = &gcc_parent_data_xo,\n+\t\t\t.num_parents = 1,\n+\t\t\t.ops = &clk_alpha_pll_stromer_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_alpha_pll_postdiv gpll4 = {\n+\t.offset = 0x22000,\n+\t.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],\n+\t.width = 4,\n+\t.clkr.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"gpll4\",\n+\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gpll4_main.clkr.hw },\n+\t\t.num_parents = 1,\n+\t\t.ops = &clk_alpha_pll_postdiv_ro_ops,\n+\t\t.flags = CLK_SET_RATE_PARENT,\n+\t},\n+};\n+\n+static const struct parent_map gcc_parent_map_xo[] = {\n+\t{ P_XO, 0 },\n+};\n+\n+static const struct parent_map gcc_parent_map_0[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0_OUT_MAIN, 1 },\n+\t{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },\n+};\n+\n+static const struct clk_parent_data gcc_parent_data_0[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .hw = &gpll0_div2.hw },\n+};\n+\n+static const struct parent_map gcc_parent_map_1[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0_OUT_MAIN, 1 },\n+};\n+\n+static const struct clk_parent_data gcc_parent_data_1[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll0.clkr.hw },\n+};\n+\n+static const struct parent_map gcc_parent_map_2[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0_OUT_MAIN, 1 },\n+\t{ P_GPLL4_OUT_MAIN, 2 },\n+};\n+\n+static const struct clk_parent_data gcc_parent_data_2[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .hw = &gpll4.clkr.hw },\n+};\n+\n+static const struct parent_map gcc_parent_map_3[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0_OUT_MAIN, 1 },\n+\t{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },\n+\t{ P_SLEEP_CLK, 6 },\n+};\n+\n+static const struct clk_parent_data gcc_parent_data_3[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .hw = &gpll0_div2.hw },\n+\t{ .index = DT_SLEEP_CLK },\n+};\n+\n+static const struct parent_map gcc_parent_map_4[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL4_OUT_MAIN, 1 },\n+\t{ P_GPLL0_OUT_AUX, 2 },\n+\t{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },\n+};\n+\n+static const struct clk_parent_data gcc_parent_data_4[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll4.clkr.hw },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .hw = &gpll0_div2.hw },\n+};\n+\n+static const struct parent_map gcc_parent_map_5[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0_OUT_MAIN, 1 },\n+\t{ P_GPLL2_OUT_AUX, 2 },\n+\t{ P_GPLL4_OUT_AUX, 3 },\n+\t{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },\n+\t{ P_GPLL0_OUT_AUX, 5 },\n+};\n+\n+static const struct clk_parent_data gcc_parent_data_5[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .hw = &gpll2.clkr.hw },\n+\t{ .hw = &gpll4.clkr.hw },\n+\t{ .hw = &gpll0_div2.hw },\n+\t{ .hw = &gpll0.clkr.hw },\n+};\n+\n+static const struct parent_map gcc_parent_map_6[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0_OUT_MAIN, 1 },\n+\t{ P_GPLL0_OUT_AUX, 2 },\n+\t{ P_SLEEP_CLK, 6 },\n+};\n+\n+static const struct clk_parent_data gcc_parent_data_6[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .index = DT_SLEEP_CLK },\n+};\n+\n+static const struct parent_map gcc_parent_map_7[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0_OUT_MAIN, 1 },\n+\t{ P_GPLL2_OUT_AUX, 2 },\n+\t{ P_GPLL4_OUT_AUX, 3 },\n+\t{ P_SLEEP_CLK, 6 },\n+};\n+\n+static const struct clk_parent_data gcc_parent_data_7[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .hw = &gpll2.clkr.hw },\n+\t{ .hw = &gpll4.clkr.hw },\n+\t{ .index = DT_SLEEP_CLK },\n+};\n+\n+static const struct parent_map gcc_parent_map_8[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0_OUT_MAIN, 1 },\n+\t{ P_GPLL2_OUT_AUX, 2 },\n+};\n+\n+static const struct clk_parent_data gcc_parent_data_8[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .hw = &gpll2.clkr.hw },\n+};\n+\n+static const struct parent_map gcc_parent_map_9[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0_OUT_MAIN, 1 },\n+\t{ P_GPLL2_OUT_MAIN, 2 },\n+\t{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },\n+};\n+\n+static const struct clk_parent_data gcc_parent_data_9[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .hw = &gpll2.clkr.hw },\n+\t{ .hw = &gpll0_div2.hw },\n+};\n+\n+static const struct parent_map gcc_parent_map_10[] = {\n+\t{ P_SLEEP_CLK, 6 },\n+};\n+\n+static const struct clk_parent_data gcc_parent_data_10[] = {\n+\t{ .index = DT_SLEEP_CLK },\n+};\n+\n+static const struct parent_map gcc_parent_map_11[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0_OUT_MAIN, 1 },\n+\t{ P_GPLL4_OUT_MAIN, 2 },\n+\t{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 3 },\n+};\n+\n+static const struct clk_parent_data gcc_parent_data_11[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .hw = &gpll4.clkr.hw },\n+\t{ .hw = &gpll0_div2.hw },\n+};\n+\n+static const struct parent_map gcc_parent_map_12[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL0_OUT_AUX, 2 },\n+\t{ P_SLEEP_CLK, 6 },\n+};\n+\n+static const struct clk_parent_data gcc_parent_data_12[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .index = DT_SLEEP_CLK },\n+};\n+\n+static const struct parent_map gcc_parent_map_13[] = {\n+\t{ P_XO, 0 },\n+\t{ P_GPLL4_OUT_AUX, 1 },\n+\t{ P_GPLL0_OUT_MAIN, 3 },\n+\t{ P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 4 },\n+};\n+\n+static const struct clk_parent_data gcc_parent_data_13[] = {\n+\t{ .index = DT_XO },\n+\t{ .hw = &gpll4.clkr.hw },\n+\t{ .hw = &gpll0.clkr.hw },\n+\t{ .hw = &gpll0_div2.hw },\n+};\n+\n+static const struct freq_tbl ftbl_gcc_adss_pwm_clk_src[] = {\n+\tF(24000000, P_XO, 1, 0, 0),\n+\tF(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 gcc_adss_pwm_clk_src = {\n+\t.cmd_rcgr = 0x1c004,\n+\t.mnd_width = 0,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_1,\n+\t.freq_tbl = ftbl_gcc_adss_pwm_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_adss_pwm_clk_src\",\n+\t\t.parent_data = gcc_parent_data_1,\n+\t\t.num_parents = ARRAY_SIZE(gcc_parent_data_1),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_gcc_apss_axi_clk_src[] = {\n+\tF(480000000, P_GPLL4_OUT_MAIN, 2.5, 0, 0),\n+\tF(533333333, P_GPLL0_OUT_MAIN, 1.5, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 gcc_apss_axi_clk_src = {\n+\t.cmd_rcgr = 0x24004,\n+\t.mnd_width = 0,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_5,\n+\t.freq_tbl = ftbl_gcc_apss_axi_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_apss_axi_clk_src\",\n+\t\t.parent_data = gcc_parent_data_5,\n+\t\t.num_parents = ARRAY_SIZE(gcc_parent_data_5),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_gcc_blsp1_qup1_spi_apps_clk_src[] = {\n+\tF(960000, P_XO, 1, 1, 25),\n+\tF(4800000, P_XO, 5, 0, 0),\n+\tF(9600000, P_XO, 2.5, 0, 0),\n+\tF(16000000, P_GPLL0_OUT_MAIN, 10, 1, 5),\n+\tF(24000000, P_XO, 1, 0, 0),\n+\tF(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),\n+\tF(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 gcc_blsp1_qup1_spi_apps_clk_src = {\n+\t.cmd_rcgr = 0x2004,\n+\t.mnd_width = 8,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_0,\n+\t.freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_blsp1_qup1_spi_apps_clk_src\",\n+\t\t.parent_data = gcc_parent_data_0,\n+\t\t.num_parents = ARRAY_SIZE(gcc_parent_data_0),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 gcc_blsp1_qup2_spi_apps_clk_src = {\n+\t.cmd_rcgr = 0x3004,\n+\t.mnd_width = 8,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_0,\n+\t.freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_blsp1_qup2_spi_apps_clk_src\",\n+\t\t.parent_data = gcc_parent_data_0,\n+\t\t.num_parents = ARRAY_SIZE(gcc_parent_data_0),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 gcc_blsp1_qup3_spi_apps_clk_src = {\n+\t.cmd_rcgr = 0x4004,\n+\t.mnd_width = 8,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_0,\n+\t.freq_tbl = ftbl_gcc_blsp1_qup1_spi_apps_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_blsp1_qup3_spi_apps_clk_src\",\n+\t\t.parent_data = gcc_parent_data_0,\n+\t\t.num_parents = ARRAY_SIZE(gcc_parent_data_0),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_gcc_blsp1_uart1_apps_clk_src[] = {\n+\tF(3686400, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 144, 15625),\n+\tF(7372800, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 288, 15625),\n+\tF(14745600, P_GCC_GPLL0_OUT_MAIN_DIV_CLK_SRC, 1, 576, 15625),\n+\tF(24000000, P_XO, 1, 0, 0),\n+\tF(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),\n+\tF(32000000, P_GPLL0_OUT_MAIN, 1, 1, 25),\n+\tF(40000000, P_GPLL0_OUT_MAIN, 1, 1, 20),\n+\tF(46400000, P_GPLL0_OUT_MAIN, 1, 29, 500),\n+\tF(48000000, P_GPLL0_OUT_MAIN, 1, 3, 50),\n+\tF(51200000, P_GPLL0_OUT_MAIN, 1, 8, 125),\n+\tF(56000000, P_GPLL0_OUT_MAIN, 1, 7, 100),\n+\tF(58982400, P_GPLL0_OUT_MAIN, 1, 1152, 15625),\n+\tF(60000000, P_GPLL0_OUT_MAIN, 1, 3, 40),\n+\tF(64000000, P_GPLL0_OUT_MAIN, 12.5, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 gcc_blsp1_uart1_apps_clk_src = {\n+\t.cmd_rcgr = 0x202c,\n+\t.mnd_width = 16,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_0,\n+\t.freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_blsp1_uart1_apps_clk_src\",\n+\t\t.parent_data = gcc_parent_data_0,\n+\t\t.num_parents = ARRAY_SIZE(gcc_parent_data_0),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 gcc_blsp1_uart2_apps_clk_src = {\n+\t.cmd_rcgr = 0x302c,\n+\t.mnd_width = 16,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_0,\n+\t.freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_blsp1_uart2_apps_clk_src\",\n+\t\t.parent_data = gcc_parent_data_0,\n+\t\t.num_parents = ARRAY_SIZE(gcc_parent_data_0),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 gcc_blsp1_uart3_apps_clk_src = {\n+\t.cmd_rcgr = 0x402c,\n+\t.mnd_width = 16,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_0,\n+\t.freq_tbl = ftbl_gcc_blsp1_uart1_apps_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_blsp1_uart3_apps_clk_src\",\n+\t\t.parent_data = gcc_parent_data_0,\n+\t\t.num_parents = ARRAY_SIZE(gcc_parent_data_0),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_gcc_gp1_clk_src[] = {\n+\tF(24000000, P_XO, 1, 0, 0),\n+\tF(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 gcc_gp1_clk_src = {\n+\t.cmd_rcgr = 0x8004,\n+\t.mnd_width = 8,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_3,\n+\t.freq_tbl = ftbl_gcc_gp1_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_gp1_clk_src\",\n+\t\t.parent_data = gcc_parent_data_3,\n+\t\t.num_parents = ARRAY_SIZE(gcc_parent_data_3),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 gcc_gp2_clk_src = {\n+\t.cmd_rcgr = 0x9004,\n+\t.mnd_width = 8,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_3,\n+\t.freq_tbl = ftbl_gcc_gp1_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_gp2_clk_src\",\n+\t\t.parent_data = gcc_parent_data_3,\n+\t\t.num_parents = ARRAY_SIZE(gcc_parent_data_3),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_gcc_lpass_sway_clk_src[] = {\n+\tF(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 gcc_lpass_sway_clk_src = {\n+\t.cmd_rcgr = 0x27004,\n+\t.mnd_width = 0,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_1,\n+\t.freq_tbl = ftbl_gcc_lpass_sway_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_lpass_sway_clk_src\",\n+\t\t.parent_data = gcc_parent_data_1,\n+\t\t.num_parents = ARRAY_SIZE(gcc_parent_data_1),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_gcc_nss_ts_clk_src[] = {\n+\tF(24000000, P_XO, 1, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 gcc_nss_ts_clk_src = {\n+\t.cmd_rcgr = 0x17088,\n+\t.mnd_width = 0,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_xo,\n+\t.freq_tbl = ftbl_gcc_nss_ts_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_nss_ts_clk_src\",\n+\t\t.parent_data = &gcc_parent_data_xo,\n+\t\t.num_parents = 1,\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_gcc_pcie3x1_0_axi_clk_src[] = {\n+\tF(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 gcc_pcie3x1_0_axi_clk_src = {\n+\t.cmd_rcgr = 0x29018,\n+\t.mnd_width = 0,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_2,\n+\t.freq_tbl = ftbl_gcc_pcie3x1_0_axi_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_pcie3x1_0_axi_clk_src\",\n+\t\t.parent_data = gcc_parent_data_2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_parent_data_2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 gcc_pcie3x1_0_rchg_clk_src = {\n+\t.cmd_rcgr = 0x2907c,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_0,\n+\t.freq_tbl = ftbl_gcc_adss_pwm_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_pcie3x1_0_rchg_clk_src\",\n+\t\t.parent_data = gcc_parent_data_0,\n+\t\t.num_parents = ARRAY_SIZE(gcc_parent_data_0),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie3x1_0_rchg_clk = {\n+\t.halt_reg = 0x2907c,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2907c,\n+\t\t.enable_mask = BIT(1),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie3x1_0_rchg_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t\t&gcc_pcie3x1_0_rchg_clk_src.clkr.hw },\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_rcg2 gcc_pcie3x1_1_axi_clk_src = {\n+\t.cmd_rcgr = 0x2a004,\n+\t.mnd_width = 0,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_2,\n+\t.freq_tbl = ftbl_gcc_pcie3x1_0_axi_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_pcie3x1_1_axi_clk_src\",\n+\t\t.parent_data = gcc_parent_data_2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_parent_data_2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 gcc_pcie3x1_1_rchg_clk_src = {\n+\t.cmd_rcgr = 0x2a078,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_0,\n+\t.freq_tbl = ftbl_gcc_adss_pwm_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_pcie3x1_1_rchg_clk_src\",\n+\t\t.parent_data = gcc_parent_data_0,\n+\t\t.num_parents = ARRAY_SIZE(gcc_parent_data_0),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie3x1_1_rchg_clk = {\n+\t.halt_reg = 0x2a078,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2a078,\n+\t\t.enable_mask = BIT(1),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie3x1_1_rchg_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t\t&gcc_pcie3x1_1_rchg_clk_src.clkr.hw },\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_gcc_pcie3x2_axi_m_clk_src[] = {\n+\tF(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 gcc_pcie3x2_axi_m_clk_src = {\n+\t.cmd_rcgr = 0x28018,\n+\t.mnd_width = 0,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_2,\n+\t.freq_tbl = ftbl_gcc_pcie3x2_axi_m_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_pcie3x2_axi_m_clk_src\",\n+\t\t.parent_data = gcc_parent_data_2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_parent_data_2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 gcc_pcie3x2_axi_s_clk_src = {\n+\t.cmd_rcgr = 0x28084,\n+\t.mnd_width = 0,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_2,\n+\t.freq_tbl = ftbl_gcc_pcie3x1_0_axi_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_pcie3x2_axi_s_clk_src\",\n+\t\t.parent_data = gcc_parent_data_2,\n+\t\t.num_parents = ARRAY_SIZE(gcc_parent_data_2),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 gcc_pcie3x2_rchg_clk_src = {\n+\t.cmd_rcgr = 0x28078,\n+\t.mnd_width = 0,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_0,\n+\t.freq_tbl = ftbl_gcc_adss_pwm_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_pcie3x2_rchg_clk_src\",\n+\t\t.parent_data = gcc_parent_data_0,\n+\t\t.num_parents = ARRAY_SIZE(gcc_parent_data_0),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie3x2_rchg_clk = {\n+\t.halt_reg = 0x28078,\n+\t.clkr = {\n+\t\t.enable_reg = 0x28078,\n+\t\t.enable_mask = BIT(1),\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie3x2_rchg_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t\t&gcc_pcie3x2_rchg_clk_src.clkr.hw },\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_gcc_pcie_aux_clk_src[] = {\n+\tF(2000000, P_XO, 12, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 gcc_pcie_aux_clk_src = {\n+\t.cmd_rcgr = 0x28004,\n+\t.mnd_width = 16,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_6,\n+\t.freq_tbl = ftbl_gcc_pcie_aux_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_pcie_aux_clk_src\",\n+\t\t.parent_data = gcc_parent_data_6,\n+\t\t.num_parents = ARRAY_SIZE(gcc_parent_data_6),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_regmap_phy_mux gcc_pcie3x2_pipe_clk_src = {\n+\t.reg = 0x28064,\n+\t.clkr = {\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie3x2_pipe_clk_src\",\n+\t\t\t.parent_data = &(const struct clk_parent_data) {\n+\t\t\t\t.index = DT_PCIE_2LANE_PHY_PIPE_CLK,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.ops = &clk_regmap_phy_mux_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_regmap_phy_mux gcc_pcie3x1_0_pipe_clk_src = {\n+\t.reg = 0x29064,\n+\t.clkr = {\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie3x1_0_pipe_clk_src\",\n+\t\t\t.parent_data = &(const struct clk_parent_data) {\n+\t\t\t\t.index = DT_USB_PCIE_WRAPPER_PIPE_CLK,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.ops = &clk_regmap_phy_mux_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_regmap_phy_mux gcc_pcie3x1_1_pipe_clk_src = {\n+\t.reg = 0x2a064,\n+\t.clkr = {\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie3x1_1_pipe_clk_src\",\n+\t\t\t.parent_data = &(const struct clk_parent_data) {\n+\t\t\t\t.index = DT_PCIE_2LANE_PHY_PIPE_CLK_X1,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.ops = &clk_regmap_phy_mux_ops,\n+\t\t},\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_gcc_pcnoc_bfdcd_clk_src[] = {\n+\tF(24000000, P_XO, 1, 0, 0),\n+\tF(50000000, P_GPLL0_OUT_MAIN, 16, 0, 0),\n+\tF(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 gcc_pcnoc_bfdcd_clk_src = {\n+\t.cmd_rcgr = 0x31004,\n+\t.mnd_width = 0,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_0,\n+\t.freq_tbl = ftbl_gcc_pcnoc_bfdcd_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_pcnoc_bfdcd_clk_src\",\n+\t\t.parent_data = gcc_parent_data_0,\n+\t\t.num_parents = ARRAY_SIZE(gcc_parent_data_0),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 gcc_q6_axim_clk_src = {\n+\t.cmd_rcgr = 0x25004,\n+\t.mnd_width = 0,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_7,\n+\t.freq_tbl = ftbl_gcc_apss_axi_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_q6_axim_clk_src\",\n+\t\t.parent_data = gcc_parent_data_7,\n+\t\t.num_parents = ARRAY_SIZE(gcc_parent_data_7),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_gcc_qdss_at_clk_src[] = {\n+\tF(240000000, P_GPLL4_OUT_MAIN, 5, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 gcc_qdss_at_clk_src = {\n+\t.cmd_rcgr = 0x2d004,\n+\t.mnd_width = 0,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_4,\n+\t.freq_tbl = ftbl_gcc_qdss_at_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_qdss_at_clk_src\",\n+\t\t.parent_data = gcc_parent_data_4,\n+\t\t.num_parents = ARRAY_SIZE(gcc_parent_data_4),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_gcc_qdss_tsctr_clk_src[] = {\n+\tF(600000000, P_GPLL4_OUT_MAIN, 2, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 gcc_qdss_tsctr_clk_src = {\n+\t.cmd_rcgr = 0x2d01c,\n+\t.mnd_width = 0,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_4,\n+\t.freq_tbl = ftbl_gcc_qdss_tsctr_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_qdss_tsctr_clk_src\",\n+\t\t.parent_data = gcc_parent_data_4,\n+\t\t.num_parents = ARRAY_SIZE(gcc_parent_data_4),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_fixed_factor gcc_qdss_tsctr_div2_clk_src = {\n+\t.mult = 1,\n+\t.div = 2,\n+\t.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"gcc_qdss_tsctr_div2_clk_src\",\n+\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gcc_qdss_tsctr_clk_src.clkr.hw },\n+\t\t.num_parents = 1,\n+\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t.ops = &clk_fixed_factor_ops,\n+\t},\n+};\n+\n+static struct clk_fixed_factor gcc_qdss_tsctr_div3_clk_src = {\n+\t.mult = 1,\n+\t.div = 3,\n+\t.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"gcc_qdss_tsctr_div3_clk_src\",\n+\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gcc_qdss_tsctr_clk_src.clkr.hw },\n+\t\t.num_parents = 1,\n+\t\t.ops = &clk_fixed_factor_ops,\n+\t},\n+};\n+\n+static struct clk_fixed_factor gcc_qdss_tsctr_div4_clk_src = {\n+\t.mult = 1,\n+\t.div = 4,\n+\t.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"gcc_qdss_tsctr_div4_clk_src\",\n+\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gcc_qdss_tsctr_clk_src.clkr.hw },\n+\t\t.num_parents = 1,\n+\t\t.ops = &clk_fixed_factor_ops,\n+\t},\n+};\n+\n+static struct clk_fixed_factor gcc_qdss_tsctr_div8_clk_src = {\n+\t.mult = 1,\n+\t.div = 8,\n+\t.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"gcc_qdss_tsctr_div8_clk_src\",\n+\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gcc_qdss_tsctr_clk_src.clkr.hw },\n+\t\t.num_parents = 1,\n+\t\t.ops = &clk_fixed_factor_ops,\n+\t},\n+};\n+\n+static struct clk_fixed_factor gcc_qdss_tsctr_div16_clk_src = {\n+\t.mult = 1,\n+\t.div = 16,\n+\t.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"gcc_qdss_tsctr_div16_clk_src\",\n+\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gcc_qdss_tsctr_clk_src.clkr.hw },\n+\t\t.num_parents = 1,\n+\t\t.ops = &clk_fixed_factor_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_gcc_qpic_io_macro_clk_src[] = {\n+\tF(24000000, P_XO, 1, 0, 0),\n+\tF(100000000, P_GPLL0_OUT_MAIN, 8, 0, 0),\n+\tF(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),\n+\tF(320000000, P_GPLL0_OUT_MAIN, 2.5, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 gcc_qpic_io_macro_clk_src = {\n+\t.cmd_rcgr = 0x32004,\n+\t.mnd_width = 0,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_8,\n+\t.freq_tbl = ftbl_gcc_qpic_io_macro_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_qpic_io_macro_clk_src\",\n+\t\t.parent_data = gcc_parent_data_8,\n+\t\t.num_parents = ARRAY_SIZE(gcc_parent_data_8),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_gcc_sdcc1_apps_clk_src[] = {\n+\tF(143713, P_XO, 1, 1, 167),\n+\tF(400000, P_XO, 1, 1, 60),\n+\tF(24000000, P_XO, 1, 0, 0),\n+\tF(48000000, P_GPLL2_OUT_MAIN, 12, 1, 2),\n+\tF(96000000, P_GPLL2_OUT_MAIN, 12, 0, 0),\n+\tF(177777778, P_GPLL0_OUT_MAIN, 4.5, 0, 0),\n+\tF(192000000, P_GPLL2_OUT_MAIN, 6, 0, 0),\n+\tF(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 gcc_sdcc1_apps_clk_src = {\n+\t.cmd_rcgr = 0x33004,\n+\t.mnd_width = 8,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_9,\n+\t.freq_tbl = ftbl_gcc_sdcc1_apps_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_sdcc1_apps_clk_src\",\n+\t\t.parent_data = gcc_parent_data_9,\n+\t\t.num_parents = ARRAY_SIZE(gcc_parent_data_9),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_gcc_sleep_clk_src[] = {\n+\tF(32000, P_SLEEP_CLK, 1, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 gcc_sleep_clk_src = {\n+\t.cmd_rcgr = 0x3400c,\n+\t.mnd_width = 0,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_10,\n+\t.freq_tbl = ftbl_gcc_sleep_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_sleep_clk_src\",\n+\t\t.parent_data = gcc_parent_data_10,\n+\t\t.num_parents = ARRAY_SIZE(gcc_parent_data_10),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_gcc_system_noc_bfdcd_clk_src[] = {\n+\tF(24000000, P_XO, 1, 0, 0),\n+\tF(133333333, P_GPLL0_OUT_MAIN, 6, 0, 0),\n+\tF(200000000, P_GPLL0_OUT_MAIN, 4, 0, 0),\n+\tF(266666667, P_GPLL4_OUT_MAIN, 4.5, 0, 0),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 gcc_system_noc_bfdcd_clk_src = {\n+\t.cmd_rcgr = 0x2e004,\n+\t.mnd_width = 0,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_11,\n+\t.freq_tbl = ftbl_gcc_system_noc_bfdcd_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_system_noc_bfdcd_clk_src\",\n+\t\t.parent_data = gcc_parent_data_11,\n+\t\t.num_parents = ARRAY_SIZE(gcc_parent_data_11),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_fixed_factor gcc_system_noc_bfdcd_div2_clk_src = {\n+\t.mult = 1,\n+\t.div = 2,\n+\t.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"gcc_system_noc_bfdcd_div2_clk_src\",\n+\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gcc_system_noc_bfdcd_clk_src.clkr.hw },\n+\t\t.num_parents = 1,\n+\t\t.ops = &clk_fixed_factor_ops,\n+\t\t.flags = CLK_SET_RATE_PARENT,\n+\t},\n+};\n+\n+static struct clk_rcg2 gcc_uniphy_sys_clk_src = {\n+\t.cmd_rcgr = 0x16004,\n+\t.mnd_width = 0,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_xo,\n+\t.freq_tbl = ftbl_gcc_nss_ts_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_uniphy_sys_clk_src\",\n+\t\t.parent_data = &gcc_parent_data_xo,\n+\t\t.num_parents = 1,\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 gcc_usb0_aux_clk_src = {\n+\t.cmd_rcgr = 0x2c018,\n+\t.mnd_width = 16,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_12,\n+\t.freq_tbl = ftbl_gcc_pcie_aux_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_usb0_aux_clk_src\",\n+\t\t.parent_data = gcc_parent_data_12,\n+\t\t.num_parents = ARRAY_SIZE(gcc_parent_data_12),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_gcc_usb0_lfps_clk_src[] = {\n+\tF(25000000, P_GPLL0_OUT_MAIN, 16, 1, 2),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 gcc_usb0_lfps_clk_src = {\n+\t.cmd_rcgr = 0x2c07c,\n+\t.mnd_width = 8,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_1,\n+\t.freq_tbl = ftbl_gcc_usb0_lfps_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_usb0_lfps_clk_src\",\n+\t\t.parent_data = gcc_parent_data_1,\n+\t\t.num_parents = ARRAY_SIZE(gcc_parent_data_1),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 gcc_usb0_master_clk_src = {\n+\t.cmd_rcgr = 0x2c004,\n+\t.mnd_width = 8,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_0,\n+\t.freq_tbl = ftbl_gcc_gp1_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_usb0_master_clk_src\",\n+\t\t.parent_data = gcc_parent_data_0,\n+\t\t.num_parents = ARRAY_SIZE(gcc_parent_data_0),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static const struct freq_tbl ftbl_gcc_usb0_mock_utmi_clk_src[] = {\n+\tF(60000000, P_GPLL4_OUT_AUX, 10, 1, 2),\n+\t{ }\n+};\n+\n+static struct clk_rcg2 gcc_usb0_mock_utmi_clk_src = {\n+\t.cmd_rcgr = 0x2c02c,\n+\t.mnd_width = 8,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_13,\n+\t.freq_tbl = ftbl_gcc_usb0_mock_utmi_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_usb0_mock_utmi_clk_src\",\n+\t\t.parent_data = gcc_parent_data_13,\n+\t\t.num_parents = ARRAY_SIZE(gcc_parent_data_13),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_regmap_phy_mux gcc_usb0_pipe_clk_src = {\n+\t.reg = 0x2c074,\n+\t.clkr = {\n+\t\t.hw.init = &(struct clk_init_data) {\n+\t\t\t.name = \"gcc_usb0_pipe_clk_src\",\n+\t\t\t.parent_data = &(const struct clk_parent_data) {\n+\t\t\t\t.index = DT_USB_PCIE_WRAPPER_PIPE_CLK,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.ops = &clk_regmap_phy_mux_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_rcg2 gcc_wcss_ahb_clk_src = {\n+\t.cmd_rcgr = 0x25030,\n+\t.mnd_width = 0,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_1,\n+\t.freq_tbl = ftbl_gcc_lpass_sway_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_wcss_ahb_clk_src\",\n+\t\t.parent_data = gcc_parent_data_1,\n+\t\t.num_parents = ARRAY_SIZE(gcc_parent_data_1),\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_rcg2 gcc_xo_clk_src = {\n+\t.cmd_rcgr = 0x34004,\n+\t.mnd_width = 0,\n+\t.hid_width = 5,\n+\t.parent_map = gcc_parent_map_xo,\n+\t.freq_tbl = ftbl_gcc_nss_ts_clk_src,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_xo_clk_src\",\n+\t\t.parent_data = &gcc_parent_data_xo,\n+\t\t.num_parents = 1,\n+\t\t.ops = &clk_rcg2_ops,\n+\t},\n+};\n+\n+static struct clk_fixed_factor gcc_xo_div4_clk_src = {\n+\t.mult = 1,\n+\t.div = 4,\n+\t.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"gcc_xo_div4_clk_src\",\n+\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gcc_xo_clk_src.clkr.hw },\n+\t\t.num_parents = 1,\n+\t\t.ops = &clk_fixed_factor_ops,\n+\t\t.flags = CLK_SET_RATE_PARENT,\n+\t},\n+};\n+\n+static struct clk_regmap_div gcc_qdss_dap_div_clk_src = {\n+\t.reg = 0x2d028,\n+\t.shift = 0,\n+\t.width = 4,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_qdss_dap_div_clk_src\",\n+\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t&gcc_qdss_tsctr_clk_src.clkr.hw,\n+\t\t},\n+\t\t.num_parents = 1,\n+\t\t.ops = &clk_regmap_div_ro_ops,\n+\t},\n+};\n+\n+static struct clk_regmap_div gcc_usb0_mock_utmi_div_clk_src = {\n+\t.reg = 0x2c040,\n+\t.shift = 0,\n+\t.width = 2,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_usb0_mock_utmi_div_clk_src\",\n+\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t&gcc_usb0_mock_utmi_clk_src.clkr.hw,\n+\t\t},\n+\t\t.num_parents = 1,\n+\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t.ops = &clk_regmap_div_ro_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_adss_pwm_clk = {\n+\t.halt_reg = 0x1c00c,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x1c00c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_adss_pwm_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_adss_pwm_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_ahb_clk = {\n+\t.halt_reg = 0x34024,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x34024,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcnoc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_ahb_clk = {\n+\t.halt_reg = 0x1008,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0xb004,\n+\t\t.enable_mask = BIT(4),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcnoc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_qup1_i2c_apps_clk = {\n+\t.halt_reg = 0x2024,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2024,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_qup1_i2c_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_blsp1_qup1_spi_apps_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_qup1_spi_apps_clk = {\n+\t.halt_reg = 0x2020,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2020,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_qup1_spi_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_blsp1_qup1_spi_apps_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_qup2_i2c_apps_clk = {\n+\t.halt_reg = 0x3024,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x3024,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_qup2_i2c_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_blsp1_qup2_spi_apps_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_qup2_spi_apps_clk = {\n+\t.halt_reg = 0x3020,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x3020,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_qup2_spi_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_blsp1_qup2_spi_apps_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_qup3_i2c_apps_clk = {\n+\t.halt_reg = 0x4024,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x4024,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_qup3_i2c_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_blsp1_qup3_spi_apps_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_qup3_spi_apps_clk = {\n+\t.halt_reg = 0x4020,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x4020,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_qup3_spi_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_blsp1_qup3_spi_apps_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_sleep_clk = {\n+\t.halt_reg = 0x1010,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0xb004,\n+\t\t.enable_mask = BIT(5),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_sleep_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_sleep_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_uart1_apps_clk = {\n+\t.halt_reg = 0x2040,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2040,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_uart1_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_blsp1_uart1_apps_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_uart2_apps_clk = {\n+\t.halt_reg = 0x3040,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x3040,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_uart2_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_blsp1_uart2_apps_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_blsp1_uart3_apps_clk = {\n+\t.halt_reg = 0x4054,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x4054,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_blsp1_uart3_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_blsp1_uart3_apps_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_ce_ahb_clk = {\n+\t.halt_reg = 0x25074,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x25074,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_ce_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_system_noc_bfdcd_div2_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_ce_axi_clk = {\n+\t.halt_reg = 0x25068,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x25068,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_ce_axi_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_system_noc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_ce_pcnoc_ahb_clk = {\n+\t.halt_reg = 0x25070,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x25070,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_ce_pcnoc_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcnoc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_cmn_12gpll_ahb_clk = {\n+\t.halt_reg = 0x3a004,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x3a004,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_cmn_12gpll_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcnoc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_cmn_12gpll_apu_clk = {\n+\t.halt_reg = 0x3a00c,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x3a00c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_cmn_12gpll_apu_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcnoc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_cmn_12gpll_sys_clk = {\n+\t.halt_reg = 0x3a008,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x3a008,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_cmn_12gpll_sys_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_uniphy_sys_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_gp1_clk = {\n+\t.halt_reg = 0x8018,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x8018,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_gp1_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_gp1_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_gp2_clk = {\n+\t.halt_reg = 0x9018,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x9018,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_gp2_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_gp2_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_lpass_core_axim_clk = {\n+\t.halt_reg = 0x27018,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x27018,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_lpass_core_axim_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_lpass_sway_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_lpass_sway_clk = {\n+\t.halt_reg = 0x27014,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x27014,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_lpass_sway_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_lpass_sway_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_mdio_ahb_clk = {\n+\t.halt_reg = 0x12004,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x12004,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_mdio_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcnoc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_mdio_slave_ahb_clk = {\n+\t.halt_reg = 0x1200c,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x1200c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_mdio_slave_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcnoc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_mem_noc_q6_axi_clk = {\n+\t.halt_reg = 0x19010,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x19010,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_mem_noc_q6_axi_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_q6_axim_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_mem_noc_ts_clk = {\n+\t.halt_reg = 0x19028,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x19028,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_mem_noc_ts_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_qdss_tsctr_div8_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_nss_ts_clk = {\n+\t.halt_reg = 0x17018,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x17018,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_nss_ts_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_nss_ts_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_nsscc_clk = {\n+\t.halt_reg = 0x17034,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x17034,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_nsscc_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcnoc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_nsscfg_clk = {\n+\t.halt_reg = 0x1702c,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x1702c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_nsscfg_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcnoc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_nssnoc_atb_clk = {\n+\t.halt_reg = 0x17014,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x17014,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_nssnoc_atb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_qdss_at_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_nssnoc_nsscc_clk = {\n+\t.halt_reg = 0x17030,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x17030,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_nssnoc_nsscc_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcnoc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_nssnoc_qosgen_ref_clk = {\n+\t.halt_reg = 0x1701c,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x1701c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_nssnoc_qosgen_ref_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_xo_div4_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_nssnoc_snoc_1_clk = {\n+\t.halt_reg = 0x1707c,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x1707c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_nssnoc_snoc_1_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_system_noc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_nssnoc_snoc_clk = {\n+\t.halt_reg = 0x17028,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x17028,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_nssnoc_snoc_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_system_noc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_nssnoc_timeout_ref_clk = {\n+\t.halt_reg = 0x17020,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x17020,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_nssnoc_timeout_ref_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_xo_div4_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_nssnoc_xo_dcd_clk = {\n+\t.halt_reg = 0x17074,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x17074,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_nssnoc_xo_dcd_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_xo_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie3x1_0_ahb_clk = {\n+\t.halt_reg = 0x29030,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x29030,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie3x1_0_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcnoc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie3x1_0_aux_clk = {\n+\t.halt_reg = 0x29070,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x29070,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie3x1_0_aux_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcie_aux_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie3x1_0_axi_m_clk = {\n+\t.halt_reg = 0x29038,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x29038,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie3x1_0_axi_m_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcie3x1_0_axi_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie3x1_0_axi_s_bridge_clk = {\n+\t.halt_reg = 0x29048,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x29048,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie3x1_0_axi_s_bridge_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcie3x1_0_axi_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie3x1_0_axi_s_clk = {\n+\t.halt_reg = 0x29040,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x29040,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie3x1_0_axi_s_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcie3x1_0_axi_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie3x1_0_pipe_clk = {\n+\t.halt_reg = 0x29068,\n+\t.halt_check = BRANCH_HALT_DELAY,\n+\t.clkr = {\n+\t\t.enable_reg = 0x29068,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie3x1_0_pipe_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcie3x1_0_pipe_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie3x1_1_ahb_clk = {\n+\t.halt_reg = 0x2a00c,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2a00c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie3x1_1_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcnoc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie3x1_1_aux_clk = {\n+\t.halt_reg = 0x2a070,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2a070,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie3x1_1_aux_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcie_aux_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie3x1_1_axi_m_clk = {\n+\t.halt_reg = 0x2a014,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2a014,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie3x1_1_axi_m_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcie3x1_1_axi_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie3x1_1_axi_s_bridge_clk = {\n+\t.halt_reg = 0x2a024,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2a024,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie3x1_1_axi_s_bridge_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcie3x1_1_axi_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie3x1_1_axi_s_clk = {\n+\t.halt_reg = 0x2a01c,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2a01c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie3x1_1_axi_s_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcie3x1_1_axi_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie3x1_1_pipe_clk = {\n+\t.halt_reg = 0x2a068,\n+\t.halt_check = BRANCH_HALT_DELAY,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2a068,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie3x1_1_pipe_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcie3x1_1_pipe_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie3x1_phy_ahb_clk = {\n+\t.halt_reg = 0x29078,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x29078,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie3x1_phy_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcnoc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie3x2_ahb_clk = {\n+\t.halt_reg = 0x28030,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x28030,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie3x2_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcnoc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie3x2_aux_clk = {\n+\t.halt_reg = 0x28070,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x28070,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie3x2_aux_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcie_aux_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie3x2_axi_m_clk = {\n+\t.halt_reg = 0x28038,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x28038,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie3x2_axi_m_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcie3x2_axi_m_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie3x2_axi_s_bridge_clk = {\n+\t.halt_reg = 0x28048,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x28048,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie3x2_axi_s_bridge_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcie3x2_axi_s_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie3x2_axi_s_clk = {\n+\t.halt_reg = 0x28040,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x28040,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie3x2_axi_s_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcie3x2_axi_s_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie3x2_phy_ahb_clk = {\n+\t.halt_reg = 0x28080,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x28080,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie3x2_phy_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcnoc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcie3x2_pipe_clk = {\n+\t.halt_reg = 0x28068,\n+\t.halt_check = BRANCH_HALT_DELAY,\n+\t.clkr = {\n+\t\t.enable_reg = 0x28068,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcie3x2_pipe_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcie3x2_pipe_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcnoc_at_clk = {\n+\t.halt_reg = 0x31024,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x31024,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcnoc_at_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_qdss_at_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_pcnoc_lpass_clk = {\n+\t.halt_reg = 0x31020,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x31020,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_pcnoc_lpass_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_lpass_sway_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_prng_ahb_clk = {\n+\t.halt_reg = 0x13024,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0xb004,\n+\t\t.enable_mask = BIT(10),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_prng_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcnoc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_q6_ahb_clk = {\n+\t.halt_reg = 0x25014,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x25014,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_q6_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_wcss_ahb_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_q6_ahb_s_clk = {\n+\t.halt_reg = 0x25018,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x25018,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_q6_ahb_s_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_wcss_ahb_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_q6_axim_clk = {\n+\t.halt_reg = 0x2500c,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2500c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_q6_axim_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_q6_axim_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_q6_axis_clk = {\n+\t.halt_reg = 0x25010,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x25010,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_q6_axis_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_system_noc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_q6_tsctr_1to2_clk = {\n+\t.halt_reg = 0x25020,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x25020,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_q6_tsctr_1to2_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_qdss_tsctr_div2_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_q6ss_atbm_clk = {\n+\t.halt_reg = 0x2501c,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2501c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_q6ss_atbm_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_qdss_at_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_q6ss_pclkdbg_clk = {\n+\t.halt_reg = 0x25024,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x25024,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_q6ss_pclkdbg_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_qdss_dap_div_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_q6ss_trig_clk = {\n+\t.halt_reg = 0x250a0,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x250a0,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_q6ss_trig_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_qdss_dap_div_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_qdss_at_clk = {\n+\t.halt_reg = 0x2d038,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2d038,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_qdss_at_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_qdss_at_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_qdss_cfg_ahb_clk = {\n+\t.halt_reg = 0x2d06c,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2d06c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_qdss_cfg_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcnoc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_qdss_dap_ahb_clk = {\n+\t.halt_reg = 0x2d068,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2d068,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_qdss_dap_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcnoc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_qdss_dap_clk = {\n+\t.halt_reg = 0x2d05c,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0xb004,\n+\t\t.enable_mask = BIT(2),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_qdss_dap_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_qdss_dap_div_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_qdss_etr_usb_clk = {\n+\t.halt_reg = 0x2d064,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2d064,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_qdss_etr_usb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_system_noc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_fixed_factor gcc_eud_at_div_clk_src = {\n+\t.mult = 1,\n+\t.div = 6,\n+\t.hw.init = &(struct clk_init_data) {\n+\t\t.name = \"gcc_eud_at_div_clk_src\",\n+\t\t.parent_hws = (const struct clk_hw *[]) {\n+\t\t\t\t&gcc_qdss_at_clk_src.clkr.hw },\n+\t\t.num_parents = 1,\n+\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t.ops = &clk_fixed_factor_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_qdss_eud_at_clk = {\n+\t.halt_reg = 0x2d070,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2d070,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_qdss_eud_at_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_eud_at_div_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_qpic_ahb_clk = {\n+\t.halt_reg = 0x32010,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x32010,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_qpic_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcnoc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_qpic_clk = {\n+\t.halt_reg = 0x32014,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x32014,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_qpic_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcnoc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_qpic_io_macro_clk = {\n+\t.halt_reg = 0x3200c,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x3200c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_qpic_io_macro_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_qpic_io_macro_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_qpic_sleep_clk = {\n+\t.halt_reg = 0x3201c,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x3201c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_qpic_sleep_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_sleep_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_sdcc1_ahb_clk = {\n+\t.halt_reg = 0x33034,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x33034,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_sdcc1_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcnoc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_sdcc1_apps_clk = {\n+\t.halt_reg = 0x3302c,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x3302c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_sdcc1_apps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_sdcc1_apps_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_snoc_lpass_cfg_clk = {\n+\t.halt_reg = 0x2e028,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2e028,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_snoc_lpass_cfg_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_lpass_sway_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_snoc_nssnoc_1_clk = {\n+\t.halt_reg = 0x17090,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x17090,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_snoc_nssnoc_1_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_system_noc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_snoc_nssnoc_clk = {\n+\t.halt_reg = 0x17084,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x17084,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_snoc_nssnoc_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_system_noc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_snoc_pcie3_1lane_1_m_clk = {\n+\t.halt_reg = 0x2e050,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2e050,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_snoc_pcie3_1lane_1_m_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcie3x1_1_axi_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_snoc_pcie3_1lane_1_s_clk = {\n+\t.halt_reg = 0x2e0ac,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2e0ac,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_snoc_pcie3_1lane_1_s_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcie3x1_1_axi_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_snoc_pcie3_1lane_m_clk = {\n+\t.halt_reg = 0x2e080,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2e080,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_snoc_pcie3_1lane_m_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcie3x1_0_axi_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_snoc_pcie3_1lane_s_clk = {\n+\t.halt_reg = 0x2e04c,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2e04c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_snoc_pcie3_1lane_s_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcie3x1_0_axi_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_snoc_pcie3_2lane_m_clk = {\n+\t.halt_reg = 0x2e07c,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2e07c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_snoc_pcie3_2lane_m_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcie3x2_axi_m_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_snoc_pcie3_2lane_s_clk = {\n+\t.halt_reg = 0x2e048,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2e048,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_snoc_pcie3_2lane_s_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcie3x2_axi_s_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_snoc_usb_clk = {\n+\t.halt_reg = 0x2e058,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2e058,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_snoc_usb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_usb0_master_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_sys_noc_at_clk = {\n+\t.halt_reg = 0x2e038,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2e038,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_sys_noc_at_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_qdss_at_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_sys_noc_wcss_ahb_clk = {\n+\t.halt_reg = 0x2e030,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2e030,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_sys_noc_wcss_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_wcss_ahb_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_uniphy0_ahb_clk = {\n+\t.halt_reg = 0x16010,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x16010,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_uniphy0_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcnoc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_uniphy0_sys_clk = {\n+\t.halt_reg = 0x1600c,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x1600c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_uniphy0_sys_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_uniphy_sys_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_uniphy1_ahb_clk = {\n+\t.halt_reg = 0x1601c,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x1601c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_uniphy1_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcnoc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_uniphy1_sys_clk = {\n+\t.halt_reg = 0x16018,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x16018,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_uniphy1_sys_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_uniphy_sys_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_usb0_aux_clk = {\n+\t.halt_reg = 0x2c050,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2c050,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_usb0_aux_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_usb0_aux_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_usb0_eud_at_clk = {\n+\t.halt_reg = 0x30004,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x30004,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_usb0_eud_at_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_eud_at_div_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_usb0_lfps_clk = {\n+\t.halt_reg = 0x2c090,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2c090,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_usb0_lfps_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_usb0_lfps_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_usb0_master_clk = {\n+\t.halt_reg = 0x2c048,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2c048,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_usb0_master_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_usb0_master_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_usb0_mock_utmi_clk = {\n+\t.halt_reg = 0x2c054,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2c054,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_usb0_mock_utmi_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_usb0_mock_utmi_div_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_usb0_phy_cfg_ahb_clk = {\n+\t.halt_reg = 0x2c05c,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2c05c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_usb0_phy_cfg_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcnoc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_usb0_pipe_clk = {\n+\t.halt_reg = 0x2c078,\n+\t.halt_check = BRANCH_HALT_DELAY,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2c078,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_usb0_pipe_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_usb0_pipe_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_usb0_sleep_clk = {\n+\t.halt_reg = 0x2c058,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2c058,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_usb0_sleep_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_sleep_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_wcss_axim_clk = {\n+\t.halt_reg = 0x2505c,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2505c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_wcss_axim_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_system_noc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_wcss_axis_clk = {\n+\t.halt_reg = 0x25060,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x25060,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_wcss_axis_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_system_noc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_wcss_dbg_ifc_apb_bdg_clk = {\n+\t.halt_reg = 0x25048,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x25048,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_wcss_dbg_ifc_apb_bdg_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_qdss_dap_div_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_wcss_dbg_ifc_apb_clk = {\n+\t.halt_reg = 0x25038,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x25038,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_wcss_dbg_ifc_apb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_qdss_dap_div_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_wcss_dbg_ifc_atb_bdg_clk = {\n+\t.halt_reg = 0x2504c,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2504c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_wcss_dbg_ifc_atb_bdg_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_qdss_at_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_wcss_dbg_ifc_atb_clk = {\n+\t.halt_reg = 0x2503c,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2503c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_wcss_dbg_ifc_atb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_qdss_at_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_wcss_dbg_ifc_nts_bdg_clk = {\n+\t.halt_reg = 0x25050,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x25050,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_wcss_dbg_ifc_nts_bdg_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_qdss_tsctr_div2_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_wcss_dbg_ifc_nts_clk = {\n+\t.halt_reg = 0x25040,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x25040,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_wcss_dbg_ifc_nts_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_qdss_tsctr_div2_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_wcss_ecahb_clk = {\n+\t.halt_reg = 0x25058,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x25058,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_wcss_ecahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_wcss_ahb_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_wcss_mst_async_bdg_clk = {\n+\t.halt_reg = 0x2e0b0,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2e0b0,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_wcss_mst_async_bdg_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_system_noc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_wcss_slv_async_bdg_clk = {\n+\t.halt_reg = 0x2e0b4,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x2e0b4,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_wcss_slv_async_bdg_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_system_noc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_xo_clk = {\n+\t.halt_reg = 0x34018,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x34018,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_xo_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_xo_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_xo_div4_clk = {\n+\t.halt_reg = 0x3401c,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x3401c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_xo_div4_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_xo_div4_clk_src.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_im_sleep_clk = {\n+\t.halt_reg = 0x34020,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x34020,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_im_sleep_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_sleep_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_nssnoc_pcnoc_1_clk = {\n+\t.halt_reg = 0x17080,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x17080,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_nssnoc_pcnoc_1_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcnoc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_mem_noc_ahb_clk = {\n+\t.halt_reg = 0x1900c,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x1900c,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_mem_noc_ahb_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_pcnoc_bfdcd_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_branch gcc_mem_noc_apss_axi_clk = {\n+\t.halt_reg = 0x1901c,\n+\t.halt_check = BRANCH_HALT_VOTED,\n+\t.clkr = {\n+\t\t.enable_reg = 0xb004,\n+\t\t.enable_mask = BIT(6),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_mem_noc_apss_axi_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_apss_axi_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_regmap_div gcc_snoc_qosgen_extref_div_clk_src = {\n+\t.reg = 0x2e010,\n+\t.shift = 0,\n+\t.width = 2,\n+\t.clkr.hw.init = &(const struct clk_init_data) {\n+\t\t.name = \"gcc_snoc_qosgen_extref_div_clk_src\",\n+\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t&gcc_xo_clk_src.clkr.hw,\n+\t\t},\n+\t\t.num_parents = 1,\n+\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t.ops = &clk_regmap_div_ro_ops,\n+\t},\n+};\n+\n+static struct clk_branch gcc_mem_noc_qosgen_extref_clk = {\n+\t.halt_reg = 0x19024,\n+\t.halt_check = BRANCH_HALT,\n+\t.clkr = {\n+\t\t.enable_reg = 0x19024,\n+\t\t.enable_mask = BIT(0),\n+\t\t.hw.init = &(const struct clk_init_data) {\n+\t\t\t.name = \"gcc_mem_noc_qosgen_extref_clk\",\n+\t\t\t.parent_hws = (const struct clk_hw*[]) {\n+\t\t\t\t&gcc_snoc_qosgen_extref_div_clk_src.clkr.hw,\n+\t\t\t},\n+\t\t\t.num_parents = 1,\n+\t\t\t.flags = CLK_SET_RATE_PARENT,\n+\t\t\t.ops = &clk_branch2_ops,\n+\t\t},\n+\t},\n+};\n+\n+static struct clk_regmap *gcc_ipq5332_clocks[] = {\n+\t[GPLL0_MAIN] = &gpll0_main.clkr,\n+\t[GPLL0] = &gpll0.clkr,\n+\t[GPLL2_MAIN] = &gpll2_main.clkr,\n+\t[GPLL2] = &gpll2.clkr,\n+\t[GPLL4_MAIN] = &gpll4_main.clkr,\n+\t[GPLL4] = &gpll4.clkr,\n+\t[GCC_ADSS_PWM_CLK] = &gcc_adss_pwm_clk.clkr,\n+\t[GCC_ADSS_PWM_CLK_SRC] = &gcc_adss_pwm_clk_src.clkr,\n+\t[GCC_AHB_CLK] = &gcc_ahb_clk.clkr,\n+\t[GCC_APSS_AXI_CLK_SRC] = &gcc_apss_axi_clk_src.clkr,\n+\t[GCC_BLSP1_AHB_CLK] = &gcc_blsp1_ahb_clk.clkr,\n+\t[GCC_BLSP1_QUP1_I2C_APPS_CLK] = &gcc_blsp1_qup1_i2c_apps_clk.clkr,\n+\t[GCC_BLSP1_QUP1_SPI_APPS_CLK] = &gcc_blsp1_qup1_spi_apps_clk.clkr,\n+\t[GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup1_spi_apps_clk_src.clkr,\n+\t[GCC_BLSP1_QUP2_I2C_APPS_CLK] = &gcc_blsp1_qup2_i2c_apps_clk.clkr,\n+\t[GCC_BLSP1_QUP2_SPI_APPS_CLK] = &gcc_blsp1_qup2_spi_apps_clk.clkr,\n+\t[GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup2_spi_apps_clk_src.clkr,\n+\t[GCC_BLSP1_QUP3_I2C_APPS_CLK] = &gcc_blsp1_qup3_i2c_apps_clk.clkr,\n+\t[GCC_BLSP1_QUP3_SPI_APPS_CLK] = &gcc_blsp1_qup3_spi_apps_clk.clkr,\n+\t[GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC] = &gcc_blsp1_qup3_spi_apps_clk_src.clkr,\n+\t[GCC_BLSP1_SLEEP_CLK] = &gcc_blsp1_sleep_clk.clkr,\n+\t[GCC_BLSP1_UART1_APPS_CLK] = &gcc_blsp1_uart1_apps_clk.clkr,\n+\t[GCC_BLSP1_UART1_APPS_CLK_SRC] = &gcc_blsp1_uart1_apps_clk_src.clkr,\n+\t[GCC_BLSP1_UART2_APPS_CLK] = &gcc_blsp1_uart2_apps_clk.clkr,\n+\t[GCC_BLSP1_UART2_APPS_CLK_SRC] = &gcc_blsp1_uart2_apps_clk_src.clkr,\n+\t[GCC_BLSP1_UART3_APPS_CLK] = &gcc_blsp1_uart3_apps_clk.clkr,\n+\t[GCC_BLSP1_UART3_APPS_CLK_SRC] = &gcc_blsp1_uart3_apps_clk_src.clkr,\n+\t[GCC_CE_AHB_CLK] = &gcc_ce_ahb_clk.clkr,\n+\t[GCC_CE_AXI_CLK] = &gcc_ce_axi_clk.clkr,\n+\t[GCC_CE_PCNOC_AHB_CLK] = &gcc_ce_pcnoc_ahb_clk.clkr,\n+\t[GCC_CMN_12GPLL_AHB_CLK] = &gcc_cmn_12gpll_ahb_clk.clkr,\n+\t[GCC_CMN_12GPLL_APU_CLK] = &gcc_cmn_12gpll_apu_clk.clkr,\n+\t[GCC_CMN_12GPLL_SYS_CLK] = &gcc_cmn_12gpll_sys_clk.clkr,\n+\t[GCC_GP1_CLK] = &gcc_gp1_clk.clkr,\n+\t[GCC_GP1_CLK_SRC] = &gcc_gp1_clk_src.clkr,\n+\t[GCC_GP2_CLK] = &gcc_gp2_clk.clkr,\n+\t[GCC_GP2_CLK_SRC] = &gcc_gp2_clk_src.clkr,\n+\t[GCC_LPASS_CORE_AXIM_CLK] = &gcc_lpass_core_axim_clk.clkr,\n+\t[GCC_LPASS_SWAY_CLK] = &gcc_lpass_sway_clk.clkr,\n+\t[GCC_LPASS_SWAY_CLK_SRC] = &gcc_lpass_sway_clk_src.clkr,\n+\t[GCC_MDIO_AHB_CLK] = &gcc_mdio_ahb_clk.clkr,\n+\t[GCC_MDIO_SLAVE_AHB_CLK] = &gcc_mdio_slave_ahb_clk.clkr,\n+\t[GCC_MEM_NOC_Q6_AXI_CLK] = &gcc_mem_noc_q6_axi_clk.clkr,\n+\t[GCC_MEM_NOC_TS_CLK] = &gcc_mem_noc_ts_clk.clkr,\n+\t[GCC_NSS_TS_CLK] = &gcc_nss_ts_clk.clkr,\n+\t[GCC_NSS_TS_CLK_SRC] = &gcc_nss_ts_clk_src.clkr,\n+\t[GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr,\n+\t[GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr,\n+\t[GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr,\n+\t[GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr,\n+\t[GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr,\n+\t[GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr,\n+\t[GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr,\n+\t[GCC_NSSNOC_TIMEOUT_REF_CLK] = &gcc_nssnoc_timeout_ref_clk.clkr,\n+\t[GCC_NSSNOC_XO_DCD_CLK] = &gcc_nssnoc_xo_dcd_clk.clkr,\n+\t[GCC_PCIE3X1_0_AHB_CLK] = &gcc_pcie3x1_0_ahb_clk.clkr,\n+\t[GCC_PCIE3X1_0_AUX_CLK] = &gcc_pcie3x1_0_aux_clk.clkr,\n+\t[GCC_PCIE3X1_0_AXI_CLK_SRC] = &gcc_pcie3x1_0_axi_clk_src.clkr,\n+\t[GCC_PCIE3X1_0_AXI_M_CLK] = &gcc_pcie3x1_0_axi_m_clk.clkr,\n+\t[GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK] = &gcc_pcie3x1_0_axi_s_bridge_clk.clkr,\n+\t[GCC_PCIE3X1_0_AXI_S_CLK] = &gcc_pcie3x1_0_axi_s_clk.clkr,\n+\t[GCC_PCIE3X1_0_PIPE_CLK] = &gcc_pcie3x1_0_pipe_clk.clkr,\n+\t[GCC_PCIE3X1_0_RCHG_CLK] = &gcc_pcie3x1_0_rchg_clk.clkr,\n+\t[GCC_PCIE3X1_0_RCHG_CLK_SRC] = &gcc_pcie3x1_0_rchg_clk_src.clkr,\n+\t[GCC_PCIE3X1_1_AHB_CLK] = &gcc_pcie3x1_1_ahb_clk.clkr,\n+\t[GCC_PCIE3X1_1_AUX_CLK] = &gcc_pcie3x1_1_aux_clk.clkr,\n+\t[GCC_PCIE3X1_1_AXI_CLK_SRC] = &gcc_pcie3x1_1_axi_clk_src.clkr,\n+\t[GCC_PCIE3X1_1_AXI_M_CLK] = &gcc_pcie3x1_1_axi_m_clk.clkr,\n+\t[GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK] = &gcc_pcie3x1_1_axi_s_bridge_clk.clkr,\n+\t[GCC_PCIE3X1_1_AXI_S_CLK] = &gcc_pcie3x1_1_axi_s_clk.clkr,\n+\t[GCC_PCIE3X1_1_PIPE_CLK] = &gcc_pcie3x1_1_pipe_clk.clkr,\n+\t[GCC_PCIE3X1_1_RCHG_CLK] = &gcc_pcie3x1_1_rchg_clk.clkr,\n+\t[GCC_PCIE3X1_1_RCHG_CLK_SRC] = &gcc_pcie3x1_1_rchg_clk_src.clkr,\n+\t[GCC_PCIE3X1_PHY_AHB_CLK] = &gcc_pcie3x1_phy_ahb_clk.clkr,\n+\t[GCC_PCIE3X2_AHB_CLK] = &gcc_pcie3x2_ahb_clk.clkr,\n+\t[GCC_PCIE3X2_AUX_CLK] = &gcc_pcie3x2_aux_clk.clkr,\n+\t[GCC_PCIE3X2_AXI_M_CLK] = &gcc_pcie3x2_axi_m_clk.clkr,\n+\t[GCC_PCIE3X2_AXI_M_CLK_SRC] = &gcc_pcie3x2_axi_m_clk_src.clkr,\n+\t[GCC_PCIE3X2_AXI_S_BRIDGE_CLK] = &gcc_pcie3x2_axi_s_bridge_clk.clkr,\n+\t[GCC_PCIE3X2_AXI_S_CLK] = &gcc_pcie3x2_axi_s_clk.clkr,\n+\t[GCC_PCIE3X2_AXI_S_CLK_SRC] = &gcc_pcie3x2_axi_s_clk_src.clkr,\n+\t[GCC_PCIE3X2_PHY_AHB_CLK] = &gcc_pcie3x2_phy_ahb_clk.clkr,\n+\t[GCC_PCIE3X2_PIPE_CLK] = &gcc_pcie3x2_pipe_clk.clkr,\n+\t[GCC_PCIE3X2_RCHG_CLK] = &gcc_pcie3x2_rchg_clk.clkr,\n+\t[GCC_PCIE3X2_RCHG_CLK_SRC] = &gcc_pcie3x2_rchg_clk_src.clkr,\n+\t[GCC_PCIE_AUX_CLK_SRC] = &gcc_pcie_aux_clk_src.clkr,\n+\t[GCC_PCNOC_AT_CLK] = &gcc_pcnoc_at_clk.clkr,\n+\t[GCC_PCNOC_BFDCD_CLK_SRC] = &gcc_pcnoc_bfdcd_clk_src.clkr,\n+\t[GCC_PCNOC_LPASS_CLK] = &gcc_pcnoc_lpass_clk.clkr,\n+\t[GCC_PRNG_AHB_CLK] = &gcc_prng_ahb_clk.clkr,\n+\t[GCC_Q6_AHB_CLK] = &gcc_q6_ahb_clk.clkr,\n+\t[GCC_Q6_AHB_S_CLK] = &gcc_q6_ahb_s_clk.clkr,\n+\t[GCC_Q6_AXIM_CLK] = &gcc_q6_axim_clk.clkr,\n+\t[GCC_Q6_AXIM_CLK_SRC] = &gcc_q6_axim_clk_src.clkr,\n+\t[GCC_Q6_AXIS_CLK] = &gcc_q6_axis_clk.clkr,\n+\t[GCC_Q6_TSCTR_1TO2_CLK] = &gcc_q6_tsctr_1to2_clk.clkr,\n+\t[GCC_Q6SS_ATBM_CLK] = &gcc_q6ss_atbm_clk.clkr,\n+\t[GCC_Q6SS_PCLKDBG_CLK] = &gcc_q6ss_pclkdbg_clk.clkr,\n+\t[GCC_Q6SS_TRIG_CLK] = &gcc_q6ss_trig_clk.clkr,\n+\t[GCC_QDSS_AT_CLK] = &gcc_qdss_at_clk.clkr,\n+\t[GCC_QDSS_AT_CLK_SRC] = &gcc_qdss_at_clk_src.clkr,\n+\t[GCC_QDSS_CFG_AHB_CLK] = &gcc_qdss_cfg_ahb_clk.clkr,\n+\t[GCC_QDSS_DAP_AHB_CLK] = &gcc_qdss_dap_ahb_clk.clkr,\n+\t[GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr,\n+\t[GCC_QDSS_DAP_DIV_CLK_SRC] = &gcc_qdss_dap_div_clk_src.clkr,\n+\t[GCC_QDSS_ETR_USB_CLK] = &gcc_qdss_etr_usb_clk.clkr,\n+\t[GCC_QDSS_EUD_AT_CLK] = &gcc_qdss_eud_at_clk.clkr,\n+\t[GCC_QPIC_AHB_CLK] = &gcc_qpic_ahb_clk.clkr,\n+\t[GCC_QPIC_CLK] = &gcc_qpic_clk.clkr,\n+\t[GCC_QPIC_IO_MACRO_CLK] = &gcc_qpic_io_macro_clk.clkr,\n+\t[GCC_QPIC_IO_MACRO_CLK_SRC] = &gcc_qpic_io_macro_clk_src.clkr,\n+\t[GCC_QPIC_SLEEP_CLK] = &gcc_qpic_sleep_clk.clkr,\n+\t[GCC_SDCC1_AHB_CLK] = &gcc_sdcc1_ahb_clk.clkr,\n+\t[GCC_SDCC1_APPS_CLK] = &gcc_sdcc1_apps_clk.clkr,\n+\t[GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr,\n+\t[GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr,\n+\t[GCC_SNOC_LPASS_CFG_CLK] = &gcc_snoc_lpass_cfg_clk.clkr,\n+\t[GCC_SNOC_NSSNOC_1_CLK] = &gcc_snoc_nssnoc_1_clk.clkr,\n+\t[GCC_SNOC_NSSNOC_CLK] = &gcc_snoc_nssnoc_clk.clkr,\n+\t[GCC_SNOC_PCIE3_1LANE_1_M_CLK] = &gcc_snoc_pcie3_1lane_1_m_clk.clkr,\n+\t[GCC_SNOC_PCIE3_1LANE_1_S_CLK] = &gcc_snoc_pcie3_1lane_1_s_clk.clkr,\n+\t[GCC_SNOC_PCIE3_1LANE_M_CLK] = &gcc_snoc_pcie3_1lane_m_clk.clkr,\n+\t[GCC_SNOC_PCIE3_1LANE_S_CLK] = &gcc_snoc_pcie3_1lane_s_clk.clkr,\n+\t[GCC_SNOC_PCIE3_2LANE_M_CLK] = &gcc_snoc_pcie3_2lane_m_clk.clkr,\n+\t[GCC_SNOC_PCIE3_2LANE_S_CLK] = &gcc_snoc_pcie3_2lane_s_clk.clkr,\n+\t[GCC_SNOC_USB_CLK] = &gcc_snoc_usb_clk.clkr,\n+\t[GCC_SYS_NOC_AT_CLK] = &gcc_sys_noc_at_clk.clkr,\n+\t[GCC_SYS_NOC_WCSS_AHB_CLK] = &gcc_sys_noc_wcss_ahb_clk.clkr,\n+\t[GCC_SYSTEM_NOC_BFDCD_CLK_SRC] = &gcc_system_noc_bfdcd_clk_src.clkr,\n+\t[GCC_UNIPHY0_AHB_CLK] = &gcc_uniphy0_ahb_clk.clkr,\n+\t[GCC_UNIPHY0_SYS_CLK] = &gcc_uniphy0_sys_clk.clkr,\n+\t[GCC_UNIPHY1_AHB_CLK] = &gcc_uniphy1_ahb_clk.clkr,\n+\t[GCC_UNIPHY1_SYS_CLK] = &gcc_uniphy1_sys_clk.clkr,\n+\t[GCC_UNIPHY_SYS_CLK_SRC] = &gcc_uniphy_sys_clk_src.clkr,\n+\t[GCC_USB0_AUX_CLK] = &gcc_usb0_aux_clk.clkr,\n+\t[GCC_USB0_AUX_CLK_SRC] = &gcc_usb0_aux_clk_src.clkr,\n+\t[GCC_USB0_EUD_AT_CLK] = &gcc_usb0_eud_at_clk.clkr,\n+\t[GCC_USB0_LFPS_CLK] = &gcc_usb0_lfps_clk.clkr,\n+\t[GCC_USB0_LFPS_CLK_SRC] = &gcc_usb0_lfps_clk_src.clkr,\n+\t[GCC_USB0_MASTER_CLK] = &gcc_usb0_master_clk.clkr,\n+\t[GCC_USB0_MASTER_CLK_SRC] = &gcc_usb0_master_clk_src.clkr,\n+\t[GCC_USB0_MOCK_UTMI_CLK] = &gcc_usb0_mock_utmi_clk.clkr,\n+\t[GCC_USB0_MOCK_UTMI_CLK_SRC] = &gcc_usb0_mock_utmi_clk_src.clkr,\n+\t[GCC_USB0_MOCK_UTMI_DIV_CLK_SRC] = &gcc_usb0_mock_utmi_div_clk_src.clkr,\n+\t[GCC_USB0_PHY_CFG_AHB_CLK] = &gcc_usb0_phy_cfg_ahb_clk.clkr,\n+\t[GCC_USB0_PIPE_CLK] = &gcc_usb0_pipe_clk.clkr,\n+\t[GCC_USB0_SLEEP_CLK] = &gcc_usb0_sleep_clk.clkr,\n+\t[GCC_WCSS_AHB_CLK_SRC] = &gcc_wcss_ahb_clk_src.clkr,\n+\t[GCC_WCSS_AXIM_CLK] = &gcc_wcss_axim_clk.clkr,\n+\t[GCC_WCSS_AXIS_CLK] = &gcc_wcss_axis_clk.clkr,\n+\t[GCC_WCSS_DBG_IFC_APB_BDG_CLK] = &gcc_wcss_dbg_ifc_apb_bdg_clk.clkr,\n+\t[GCC_WCSS_DBG_IFC_APB_CLK] = &gcc_wcss_dbg_ifc_apb_clk.clkr,\n+\t[GCC_WCSS_DBG_IFC_ATB_BDG_CLK] = &gcc_wcss_dbg_ifc_atb_bdg_clk.clkr,\n+\t[GCC_WCSS_DBG_IFC_ATB_CLK] = &gcc_wcss_dbg_ifc_atb_clk.clkr,\n+\t[GCC_WCSS_DBG_IFC_NTS_BDG_CLK] = &gcc_wcss_dbg_ifc_nts_bdg_clk.clkr,\n+\t[GCC_WCSS_DBG_IFC_NTS_CLK] = &gcc_wcss_dbg_ifc_nts_clk.clkr,\n+\t[GCC_WCSS_ECAHB_CLK] = &gcc_wcss_ecahb_clk.clkr,\n+\t[GCC_WCSS_MST_ASYNC_BDG_CLK] = &gcc_wcss_mst_async_bdg_clk.clkr,\n+\t[GCC_WCSS_SLV_ASYNC_BDG_CLK] = &gcc_wcss_slv_async_bdg_clk.clkr,\n+\t[GCC_XO_CLK] = &gcc_xo_clk.clkr,\n+\t[GCC_XO_CLK_SRC] = &gcc_xo_clk_src.clkr,\n+\t[GCC_XO_DIV4_CLK] = &gcc_xo_div4_clk.clkr,\n+\t[GCC_IM_SLEEP_CLK] = &gcc_im_sleep_clk.clkr,\n+\t[GCC_NSSNOC_PCNOC_1_CLK] = &gcc_nssnoc_pcnoc_1_clk.clkr,\n+\t[GCC_MEM_NOC_AHB_CLK] = &gcc_mem_noc_ahb_clk.clkr,\n+\t[GCC_MEM_NOC_APSS_AXI_CLK] = &gcc_mem_noc_apss_axi_clk.clkr,\n+\t[GCC_SNOC_QOSGEN_EXTREF_DIV_CLK_SRC] = &gcc_snoc_qosgen_extref_div_clk_src.clkr,\n+\t[GCC_MEM_NOC_QOSGEN_EXTREF_CLK] = &gcc_mem_noc_qosgen_extref_clk.clkr,\n+\t[GCC_PCIE3X2_PIPE_CLK_SRC] = &gcc_pcie3x2_pipe_clk_src.clkr,\n+\t[GCC_PCIE3X1_0_PIPE_CLK_SRC] = &gcc_pcie3x1_0_pipe_clk_src.clkr,\n+\t[GCC_PCIE3X1_1_PIPE_CLK_SRC] = &gcc_pcie3x1_1_pipe_clk_src.clkr,\n+\t[GCC_USB0_PIPE_CLK_SRC] = &gcc_usb0_pipe_clk_src.clkr,\n+};\n+\n+static const struct qcom_reset_map gcc_ipq5332_resets[] = {\n+\t[GCC_ADSS_BCR] = { 0x1c000 },\n+\t[GCC_ADSS_PWM_CLK_ARES] = { 0x1c00c, 2 },\n+\t[GCC_AHB_CLK_ARES] = { 0x34024, 2 },\n+\t[GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR] = { 0x38000 },\n+\t[GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_CLK_ARES] = { 0x3800c, 2 },\n+\t[GCC_APSS_AHB_CLK_ARES] = { 0x24018, 2 },\n+\t[GCC_APSS_AXI_CLK_ARES] = { 0x2401c, 2 },\n+\t[GCC_BLSP1_AHB_CLK_ARES] = { 0x1008, 2 },\n+\t[GCC_BLSP1_BCR] = { 0x1000 },\n+\t[GCC_BLSP1_QUP1_BCR] = { 0x2000 },\n+\t[GCC_BLSP1_QUP1_I2C_APPS_CLK_ARES] = { 0x2024, 2 },\n+\t[GCC_BLSP1_QUP1_SPI_APPS_CLK_ARES] = { 0x2020, 2 },\n+\t[GCC_BLSP1_QUP2_BCR] = { 0x3000 },\n+\t[GCC_BLSP1_QUP2_I2C_APPS_CLK_ARES] = { 0x3024, 2 },\n+\t[GCC_BLSP1_QUP2_SPI_APPS_CLK_ARES] = { 0x3020, 2 },\n+\t[GCC_BLSP1_QUP3_BCR] = { 0x4000 },\n+\t[GCC_BLSP1_QUP3_I2C_APPS_CLK_ARES] = { 0x4024, 2 },\n+\t[GCC_BLSP1_QUP3_SPI_APPS_CLK_ARES] = { 0x4020, 2 },\n+\t[GCC_BLSP1_SLEEP_CLK_ARES] = { 0x1010, 2 },\n+\t[GCC_BLSP1_UART1_APPS_CLK_ARES] = { 0x2040, 2 },\n+\t[GCC_BLSP1_UART1_BCR] = { 0x2028 },\n+\t[GCC_BLSP1_UART2_APPS_CLK_ARES] = { 0x3040, 2 },\n+\t[GCC_BLSP1_UART2_BCR] = { 0x3028 },\n+\t[GCC_BLSP1_UART3_APPS_CLK_ARES] = { 0x4054, 2 },\n+\t[GCC_BLSP1_UART3_BCR] = { 0x4028 },\n+\t[GCC_CE_BCR] = { 0x18008 },\n+\t[GCC_CMN_BLK_BCR] = { 0x3a000 },\n+\t[GCC_CMN_LDO0_BCR] = { 0x1d000 },\n+\t[GCC_CMN_LDO1_BCR] = { 0x1d008 },\n+\t[GCC_DCC_BCR] = { 0x35000 },\n+\t[GCC_GP1_CLK_ARES] = { 0x8018, 2 },\n+\t[GCC_GP2_CLK_ARES] = { 0x9018, 2 },\n+\t[GCC_LPASS_BCR] = { 0x27000 },\n+\t[GCC_LPASS_CORE_AXIM_CLK_ARES] = { 0x27018, 2 },\n+\t[GCC_LPASS_SWAY_CLK_ARES] = { 0x27014, 2 },\n+\t[GCC_MDIOM_BCR] = { 0x12000 },\n+\t[GCC_MDIOS_BCR] = { 0x12008 },\n+\t[GCC_NSS_BCR] = { 0x17000 },\n+\t[GCC_NSS_TS_CLK_ARES] = { 0x17018, 2 },\n+\t[GCC_NSSCC_CLK_ARES] = { 0x17034, 2 },\n+\t[GCC_NSSCFG_CLK_ARES] = { 0x1702c, 2 },\n+\t[GCC_NSSNOC_ATB_CLK_ARES] = { 0x17014, 2 },\n+\t[GCC_NSSNOC_NSSCC_CLK_ARES] = { 0x17030, 2 },\n+\t[GCC_NSSNOC_QOSGEN_REF_CLK_ARES] = { 0x1701c, 2 },\n+\t[GCC_NSSNOC_SNOC_1_CLK_ARES] = { 0x1707c, 2 },\n+\t[GCC_NSSNOC_SNOC_CLK_ARES] = { 0x17028, 2 },\n+\t[GCC_NSSNOC_TIMEOUT_REF_CLK_ARES] = { 0x17020, 2 },\n+\t[GCC_NSSNOC_XO_DCD_CLK_ARES] = { 0x17074, 2 },\n+\t[GCC_PCIE3X1_0_AHB_CLK_ARES] = { 0x29030, 2 },\n+\t[GCC_PCIE3X1_0_AUX_CLK_ARES] = { 0x29070, 2 },\n+\t[GCC_PCIE3X1_0_AXI_M_CLK_ARES] = { 0x29038, 2 },\n+\t[GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK_ARES] = { 0x29048, 2 },\n+\t[GCC_PCIE3X1_0_AXI_S_CLK_ARES] = { 0x29040, 2 },\n+\t[GCC_PCIE3X1_0_BCR] = { 0x29000 },\n+\t[GCC_PCIE3X1_0_LINK_DOWN_BCR] = { 0x29054 },\n+\t[GCC_PCIE3X1_0_PHY_BCR] = { 0x29060 },\n+\t[GCC_PCIE3X1_0_PHY_PHY_BCR] = { 0x2905c },\n+\t[GCC_PCIE3X1_1_AHB_CLK_ARES] = { 0x2a00c, 2 },\n+\t[GCC_PCIE3X1_1_AUX_CLK_ARES] = { 0x2a070, 2 },\n+\t[GCC_PCIE3X1_1_AXI_M_CLK_ARES] = { 0x2a014, 2 },\n+\t[GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK_ARES] = { 0x2a024, 2 },\n+\t[GCC_PCIE3X1_1_AXI_S_CLK_ARES] = { 0x2a01c, 2 },\n+\t[GCC_PCIE3X1_1_BCR] = { 0x2a000 },\n+\t[GCC_PCIE3X1_1_LINK_DOWN_BCR] = { 0x2a028 },\n+\t[GCC_PCIE3X1_1_PHY_BCR] = { 0x2a030 },\n+\t[GCC_PCIE3X1_1_PHY_PHY_BCR] = { 0x2a02c },\n+\t[GCC_PCIE3X1_PHY_AHB_CLK_ARES] = { 0x29078, 2 },\n+\t[GCC_PCIE3X2_AHB_CLK_ARES] = { 0x28030, 2 },\n+\t[GCC_PCIE3X2_AUX_CLK_ARES] = { 0x28070, 2 },\n+\t[GCC_PCIE3X2_AXI_M_CLK_ARES] = { 0x28038, 2 },\n+\t[GCC_PCIE3X2_AXI_S_BRIDGE_CLK_ARES] = { 0x28048, 2 },\n+\t[GCC_PCIE3X2_AXI_S_CLK_ARES] = { 0x28040, 2 },\n+\t[GCC_PCIE3X2_BCR] = { 0x28000 },\n+\t[GCC_PCIE3X2_LINK_DOWN_BCR] = { 0x28054 },\n+\t[GCC_PCIE3X2_PHY_AHB_CLK_ARES] = { 0x28080, 2 },\n+\t[GCC_PCIE3X2_PHY_BCR] = { 0x28060 },\n+\t[GCC_PCIE3X2PHY_PHY_BCR] = { 0x2805c },\n+\t[GCC_PCNOC_BCR] = { 0x31000 },\n+\t[GCC_PCNOC_LPASS_CLK_ARES] = { 0x31020, 2 },\n+\t[GCC_PRNG_AHB_CLK_ARES] = { 0x13024, 2 },\n+\t[GCC_PRNG_BCR] = { 0x13020 },\n+\t[GCC_Q6_AHB_CLK_ARES] = { 0x25014, 2 },\n+\t[GCC_Q6_AHB_S_CLK_ARES] = { 0x25018, 2 },\n+\t[GCC_Q6_AXIM_CLK_ARES] = { 0x2500c, 2 },\n+\t[GCC_Q6_AXIS_CLK_ARES] = { 0x25010, 2 },\n+\t[GCC_Q6_TSCTR_1TO2_CLK_ARES] = { 0x25020, 2 },\n+\t[GCC_Q6SS_ATBM_CLK_ARES] = { 0x2501c, 2 },\n+\t[GCC_Q6SS_PCLKDBG_CLK_ARES] = { 0x25024, 2 },\n+\t[GCC_Q6SS_TRIG_CLK_ARES] = { 0x250a0, 2 },\n+\t[GCC_QDSS_APB2JTAG_CLK_ARES] = { 0x2d060, 2 },\n+\t[GCC_QDSS_AT_CLK_ARES] = { 0x2d038, 2 },\n+\t[GCC_QDSS_BCR] = { 0x2d000 },\n+\t[GCC_QDSS_CFG_AHB_CLK_ARES] = { 0x2d06c, 2 },\n+\t[GCC_QDSS_DAP_AHB_CLK_ARES] = { 0x2d068, 2 },\n+\t[GCC_QDSS_DAP_CLK_ARES] = { 0x2d05c, 2 },\n+\t[GCC_QDSS_ETR_USB_CLK_ARES] = { 0x2d064, 2 },\n+\t[GCC_QDSS_EUD_AT_CLK_ARES] = { 0x2d070, 2 },\n+\t[GCC_QDSS_STM_CLK_ARES] = { 0x2d040, 2 },\n+\t[GCC_QDSS_TRACECLKIN_CLK_ARES] = { 0x2d044, 2 },\n+\t[GCC_QDSS_TS_CLK_ARES] = { 0x2d078, 2 },\n+\t[GCC_QDSS_TSCTR_DIV16_CLK_ARES] = { 0x2d058, 2 },\n+\t[GCC_QDSS_TSCTR_DIV2_CLK_ARES] = { 0x2d048, 2 },\n+\t[GCC_QDSS_TSCTR_DIV3_CLK_ARES] = { 0x2d04c, 2 },\n+\t[GCC_QDSS_TSCTR_DIV4_CLK_ARES] = { 0x2d050, 2 },\n+\t[GCC_QDSS_TSCTR_DIV8_CLK_ARES] = { 0x2d054, 2 },\n+\t[GCC_QPIC_AHB_CLK_ARES] = { 0x32010, 2 },\n+\t[GCC_QPIC_CLK_ARES] = { 0x32014, 2 },\n+\t[GCC_QPIC_BCR] = { 0x32000 },\n+\t[GCC_QPIC_IO_MACRO_CLK_ARES] = { 0x3200c, 2 },\n+\t[GCC_QPIC_SLEEP_CLK_ARES] = { 0x3201c, 2 },\n+\t[GCC_QUSB2_0_PHY_BCR] = { 0x2c068 },\n+\t[GCC_SDCC1_AHB_CLK_ARES] = { 0x33034, 2 },\n+\t[GCC_SDCC1_APPS_CLK_ARES] = { 0x3302c, 2 },\n+\t[GCC_SDCC_BCR] = { 0x33000 },\n+\t[GCC_SNOC_BCR] = { 0x2e000 },\n+\t[GCC_SNOC_LPASS_CFG_CLK_ARES] = { 0x2e028, 2 },\n+\t[GCC_SNOC_NSSNOC_1_CLK_ARES] = { 0x17090, 2 },\n+\t[GCC_SNOC_NSSNOC_CLK_ARES] = { 0x17084, 2 },\n+\t[GCC_SYS_NOC_QDSS_STM_AXI_CLK_ARES] = { 0x2e034, 2 },\n+\t[GCC_SYS_NOC_WCSS_AHB_CLK_ARES] = { 0x2e030, 2 },\n+\t[GCC_UNIPHY0_AHB_CLK_ARES] = { 0x16010, 2 },\n+\t[GCC_UNIPHY0_BCR] = { 0x16000 },\n+\t[GCC_UNIPHY0_SYS_CLK_ARES] = { 0x1600c, 2 },\n+\t[GCC_UNIPHY1_AHB_CLK_ARES] = { 0x1601c, 2 },\n+\t[GCC_UNIPHY1_BCR] = { 0x16014 },\n+\t[GCC_UNIPHY1_SYS_CLK_ARES] = { 0x16018, 2 },\n+\t[GCC_USB0_AUX_CLK_ARES] = { 0x2c050, 2 },\n+\t[GCC_USB0_EUD_AT_CLK_ARES] = { 0x30004, 2 },\n+\t[GCC_USB0_LFPS_CLK_ARES] = { 0x2c090, 2 },\n+\t[GCC_USB0_MASTER_CLK_ARES] = { 0x2c048, 2 },\n+\t[GCC_USB0_MOCK_UTMI_CLK_ARES] = { 0x2c054, 2 },\n+\t[GCC_USB0_PHY_BCR] = { 0x2c06c },\n+\t[GCC_USB0_PHY_CFG_AHB_CLK_ARES] = { 0x2c05c, 2 },\n+\t[GCC_USB0_SLEEP_CLK_ARES] = { 0x2c058, 2 },\n+\t[GCC_USB3PHY_0_PHY_BCR] = { 0x2c070 },\n+\t[GCC_USB_BCR] = { 0x2c000 },\n+\t[GCC_WCSS_AXIM_CLK_ARES] = { 0x2505c, 2 },\n+\t[GCC_WCSS_AXIS_CLK_ARES] = { 0x25060, 2 },\n+\t[GCC_WCSS_BCR] = { 0x18004 },\n+\t[GCC_WCSS_DBG_IFC_APB_BDG_CLK_ARES] = { 0x25048, 2 },\n+\t[GCC_WCSS_DBG_IFC_APB_CLK_ARES] = { 0x25038, 2 },\n+\t[GCC_WCSS_DBG_IFC_ATB_BDG_CLK_ARES] = { 0x2504c, 2 },\n+\t[GCC_WCSS_DBG_IFC_ATB_CLK_ARES] = { 0x2503c, 2 },\n+\t[GCC_WCSS_DBG_IFC_NTS_BDG_CLK_ARES] = { 0x25050, 2 },\n+\t[GCC_WCSS_DBG_IFC_NTS_CLK_ARES] = { 0x25040, 2 },\n+\t[GCC_WCSS_ECAHB_CLK_ARES] = { 0x25058, 2 },\n+\t[GCC_WCSS_MST_ASYNC_BDG_CLK_ARES] = { 0x2e0b0, 2 },\n+\t[GCC_WCSS_Q6_BCR] = { 0x18000 },\n+\t[GCC_WCSS_SLV_ASYNC_BDG_CLK_ARES] = { 0x2e0b4, 2 },\n+\t[GCC_XO_CLK_ARES] = { 0x34018, 2 },\n+\t[GCC_XO_DIV4_CLK_ARES] = { 0x3401c, 2 },\n+\t[GCC_Q6SS_DBG_ARES] = { 0x25094 },\n+\t[GCC_WCSS_DBG_BDG_ARES] = { 0x25098, 0 },\n+\t[GCC_WCSS_DBG_ARES] = { 0x25098, 1 },\n+\t[GCC_WCSS_AXI_S_ARES] = { 0x25098, 2 },\n+\t[GCC_WCSS_AXI_M_ARES] = { 0x25098, 3 },\n+\t[GCC_WCSSAON_ARES] = { 0x2509C },\n+\t[GCC_PCIE3X2_PIPE_ARES] = { 0x28058, 0 },\n+\t[GCC_PCIE3X2_CORE_STICKY_ARES] = { 0x28058, 1 },\n+\t[GCC_PCIE3X2_AXI_S_STICKY_ARES] = { 0x28058, 2 },\n+\t[GCC_PCIE3X2_AXI_M_STICKY_ARES] = { 0x28058, 3 },\n+\t[GCC_PCIE3X1_0_PIPE_ARES] = { 0x29058, 0 },\n+\t[GCC_PCIE3X1_0_CORE_STICKY_ARES] = { 0x29058, 1 },\n+\t[GCC_PCIE3X1_0_AXI_S_STICKY_ARES] = { 0x29058, 2 },\n+\t[GCC_PCIE3X1_0_AXI_M_STICKY_ARES] = { 0x29058, 3 },\n+\t[GCC_PCIE3X1_1_PIPE_ARES] = { 0x2a058, 0 },\n+\t[GCC_PCIE3X1_1_CORE_STICKY_ARES] = { 0x2a058, 1 },\n+\t[GCC_PCIE3X1_1_AXI_S_STICKY_ARES] = { 0x2a058, 2 },\n+\t[GCC_PCIE3X1_1_AXI_M_STICKY_ARES] = { 0x2a058, 3 },\n+\t[GCC_IM_SLEEP_CLK_ARES] = { 0x34020, 2 },\n+\t[GCC_NSSNOC_PCNOC_1_CLK_ARES] = { 0x17080, 2 },\n+\t[GCC_UNIPHY0_XPCS_ARES] = { 0x16050 },\n+\t[GCC_UNIPHY1_XPCS_ARES] = { 0x16060 },\n+};\n+\n+static const struct regmap_config gcc_ipq5332_regmap_config = {\n+\t.reg_bits = 32,\n+\t.reg_stride = 4,\n+\t.val_bits = 32,\n+\t.max_register = 0x3f024,\n+\t.fast_io = true,\n+};\n+\n+static struct clk_hw *gcc_ipq5332_hws[] = {\n+\t&gpll0_div2.hw,\n+\t&gcc_xo_div4_clk_src.hw,\n+\t&gcc_system_noc_bfdcd_div2_clk_src.hw,\n+\t&gcc_qdss_tsctr_div2_clk_src.hw,\n+\t&gcc_qdss_tsctr_div3_clk_src.hw,\n+\t&gcc_qdss_tsctr_div4_clk_src.hw,\n+\t&gcc_qdss_tsctr_div8_clk_src.hw,\n+\t&gcc_qdss_tsctr_div16_clk_src.hw,\n+\t&gcc_eud_at_div_clk_src.hw,\n+};\n+\n+static const struct qcom_cc_desc gcc_ipq5332_desc = {\n+\t.config = &gcc_ipq5332_regmap_config,\n+\t.clks = gcc_ipq5332_clocks,\n+\t.num_clks = ARRAY_SIZE(gcc_ipq5332_clocks),\n+\t.resets = gcc_ipq5332_resets,\n+\t.num_resets = ARRAY_SIZE(gcc_ipq5332_resets),\n+\t.clk_hws = gcc_ipq5332_hws,\n+\t.num_clk_hws = ARRAY_SIZE(gcc_ipq5332_hws),\n+};\n+\n+static int gcc_ipq5332_probe(struct platform_device *pdev)\n+{\n+\treturn qcom_cc_probe(pdev, &gcc_ipq5332_desc);\n+}\n+\n+static const struct of_device_id gcc_ipq5332_match_table[] = {\n+\t{ .compatible = \"qcom,ipq5332-gcc\" },\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(of, gcc_ipq5332_match_table);\n+\n+static struct platform_driver gcc_ipq5332_driver = {\n+\t.probe = gcc_ipq5332_probe,\n+\t.driver = {\n+\t\t.name = \"gcc-ipq5332\",\n+\t\t.of_match_table = gcc_ipq5332_match_table,\n+\t},\n+};\n+\n+static int __init gcc_ipq5332_init(void)\n+{\n+\treturn platform_driver_register(&gcc_ipq5332_driver);\n+}\n+core_initcall(gcc_ipq5332_init);\n+\n+static void __exit gcc_ipq5332_exit(void)\n+{\n+\tplatform_driver_unregister(&gcc_ipq5332_driver);\n+}\n+module_exit(gcc_ipq5332_exit);\n+\n+MODULE_DESCRIPTION(\"QTI GCC IPQ5332 Driver\");\n+MODULE_LICENSE(\"GPL\");\n",
    "prefixes": [
        "V5",
        "3/7"
    ]
}