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GET /api/patches/1744101/?format=api
{ "id": 1744101, "url": "http://patchwork.ozlabs.org/api/patches/1744101/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20230217075835.460-7-quic_kathirav@quicinc.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20230217075835.460-7-quic_kathirav@quicinc.com>", "list_archive_url": null, "date": "2023-02-17T07:58:34", "name": "[V5,6/7] arm64: dts: qcom: add IPQ5332 SoC and MI01.2 board support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6880f66dac411d1bf67b339fff7ccd1511a2f5d2", "submitter": { "id": 83327, "url": "http://patchwork.ozlabs.org/api/people/83327/?format=api", "name": "Kathiravan Thirumoorthy", "email": "quic_kathirav@quicinc.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20230217075835.460-7-quic_kathirav@quicinc.com/mbox/", "series": [ { "id": 342454, "url": "http://patchwork.ozlabs.org/api/series/342454/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=342454", "date": "2023-02-17T07:58:28", "name": "Add minimal boot support for IPQ5332", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/342454/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1744101/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1744101/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-gpio-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) 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SMTP Server\n (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id\n 15.2.986.41; Thu, 16 Feb 2023 23:59:42 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=qcppdkim1;\n bh=xoI1FhXa/XhlsIO13jf69H5n4wDMn1mp9WgbQNpWf1Y=;\n b=ThobjzJGZcSrzW00ks2eCC9rQai0hESOBPYpeKexXiwPPn4ICqEngPLE+e2HPKHWl/Ks\n mNQKVxU6x6todKkFfpmfTJklCyER1ri8UkKuxFI7kK+26WvevgUWu6x2WdSWtrGf0yKV\n MflKHIYYTuPmYgMl7OYMrODhq+qxptcl0rkP9pdiZUCiSbaoLOqQcG7rALbpaNtWKlxk\n iPWLH0RZA+mtUMKEisjyu4JNPqp1njVOPFFhoZRK9a7aAb6Gdar0gmJvyNKlXDKUBEZF\n MevPFbcoIf513y0MDiimaRcP3R+IFrdpbMpif2Kywuv26D0oWVGtDl3mIwKXfiOFuejL Sw==", "From": "Kathiravan T <quic_kathirav@quicinc.com>", "To": "<krzysztof.kozlowski@linaro.org>, <agross@kernel.org>,\n <andersson@kernel.org>, <konrad.dybcio@linaro.org>,\n <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,\n <mturquette@baylibre.com>, <sboyd@kernel.org>,\n <linus.walleij@linaro.org>, <catalin.marinas@arm.com>,\n <will@kernel.org>, <shawnguo@kernel.org>, <arnd@arndb.de>,\n <dmitry.baryshkov@linaro.org>, <marcel.ziswiler@toradex.com>,\n <nfraprado@collabora.com>, <robimarko@gmail.com>,\n <quic_gurus@quicinc.com>, <linux-arm-msm@vger.kernel.org>,\n <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n <linux-clk@vger.kernel.org>, <linux-gpio@vger.kernel.org>,\n <linux-arm-kernel@lists.infradead.org>", "CC": "<quic_varada@quicinc.com>, <quic_srichara@quicinc.com>,\n Kathiravan T <quic_kathirav@quicinc.com>", "Subject": "[PATCH V5 6/7] arm64: dts: qcom: add IPQ5332 SoC and MI01.2 board\n support", "Date": "Fri, 17 Feb 2023 13:28:34 +0530", "Message-ID": "<20230217075835.460-7-quic_kathirav@quicinc.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20230217075835.460-1-quic_kathirav@quicinc.com>", "References": "<20230217075835.460-1-quic_kathirav@quicinc.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.80.80.8]", "X-ClientProxiedBy": "nasanex01b.na.qualcomm.com (10.46.141.250) To\n nalasex01a.na.qualcomm.com (10.47.209.196)", "X-QCInternal": "smtphost", "X-Proofpoint-Virus-Version": [ "vendor=nai engine=6200 definitions=5800\n signatures=585085", "vendor=baseguard\n engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.170.22\n definitions=2023-02-17_04,2023-02-16_01,2023-02-09_01" ], "X-Proofpoint-ORIG-GUID": "Gzl61LAxkyy7JO9LXuYw39zUA3xMonh5", "X-Proofpoint-GUID": "Gzl61LAxkyy7JO9LXuYw39zUA3xMonh5", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n malwarescore=0 suspectscore=0\n bulkscore=0 spamscore=0 phishscore=0 impostorscore=0 mlxlogscore=999\n clxscore=1015 adultscore=0 lowpriorityscore=0 mlxscore=0\n priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1\n engine=8.12.0-2212070000 definitions=main-2302170071", "X-Spam-Status": "No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS\n autolearn=ham autolearn_force=no version=3.4.6", "X-Spam-Checker-Version": "SpamAssassin 3.4.6 (2021-04-09) on\n lindbergh.monkeyblade.net", "Precedence": "bulk", "List-ID": "<linux-gpio.vger.kernel.org>", "X-Mailing-List": "linux-gpio@vger.kernel.org" }, "content": "Add initial device tree support for the Qualcomm IPQ5332 SoC and\nMI01.2 board.\n\nSigned-off-by: Kathiravan T <quic_kathirav@quicinc.com>\n---\nChanges in V5:\n\t- Dropped the clock-names property in GCC node\n\nChanges in V4:\n\t- No changes\n\nChanges in V3:\n\t- Updated the V2M node name to reflect the proper address\n\t- In reserved-memory node, changed the order of the 'reg' and\n\t 'no-map' property\n\t- Moved the below properties to the board DTS\n\t\tbus-width = <4>;\n\t\tmax-frequency = <192000000>;\n\t\tmmc-ddr-1_8v;\n\t\tmmc-hs200-1_8v;\n\nChanges in V2:\n\t- Changed the license to BSD3 in the file ipq5332-mi01.2.dts\n\t- Updated the model name, not to include the foundry ID\n\t- Used the decimal notation instead of hex for 'cache-level'\n\t property\n\t- Dropped the blank line\n\t- Updated the node name for the TZ reserved region\n\t- Moved the 'compatible' property as first one in the node,\n\t wherever applicable\n\t- Used the decimal notation for *-cells property insrtead of\n\t hex\n\t- Reorganised the properties of memory mapped timer node as\n\t below\n\t\t- reg\n\t\t- interrupts\n\t\t- frame-number\n\t- Fixed the indentation in timer node\n\n arch/arm64/boot/dts/qcom/Makefile | 1 +\n arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts | 75 ++++++\n arch/arm64/boot/dts/qcom/ipq5332.dtsi | 263 ++++++++++++++++++++\n 3 files changed, 339 insertions(+)\n create mode 100644 arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts\n create mode 100644 arch/arm64/boot/dts/qcom/ipq5332.dtsi", "diff": "diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile\nindex 31aa54f0428c..cfebb1b3c2a2 100644\n--- a/arch/arm64/boot/dts/qcom/Makefile\n+++ b/arch/arm64/boot/dts/qcom/Makefile\n@@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_QCOM)\t+= apq8016-sbc.dtb\n dtb-$(CONFIG_ARCH_QCOM)\t+= apq8094-sony-xperia-kitakami-karin_windy.dtb\n dtb-$(CONFIG_ARCH_QCOM)\t+= apq8096-db820c.dtb\n dtb-$(CONFIG_ARCH_QCOM)\t+= apq8096-ifc6640.dtb\n+dtb-$(CONFIG_ARCH_QCOM)\t+= ipq5332-mi01.2.dtb\n dtb-$(CONFIG_ARCH_QCOM)\t+= ipq6018-cp01-c1.dtb\n dtb-$(CONFIG_ARCH_QCOM)\t+= ipq8074-hk01.dtb\n dtb-$(CONFIG_ARCH_QCOM)\t+= ipq8074-hk10-c1.dtb\ndiff --git a/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts b/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts\nnew file mode 100644\nindex 000000000000..702013b867d7\n--- /dev/null\n+++ b/arch/arm64/boot/dts/qcom/ipq5332-mi01.2.dts\n@@ -0,0 +1,75 @@\n+// SPDX-License-Identifier: BSD-3-Clause\n+/*\n+ * IPQ5332 AP-MI01.2 board device tree source\n+ *\n+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.\n+ */\n+\n+/dts-v1/;\n+\n+#include \"ipq5332.dtsi\"\n+\n+/ {\n+\tmodel = \"Qualcomm Technologies, Inc. IPQ5332 MI01.2\";\n+\tcompatible = \"qcom,ipq5332-ap-mi01.2\", \"qcom,ipq5332\";\n+\n+\taliases {\n+\t\tserial0 = &blsp1_uart0;\n+\t};\n+\n+\tchosen {\n+\t\tstdout-path = \"serial0\";\n+\t};\n+};\n+\n+&blsp1_uart0 {\n+\tpinctrl-0 = <&serial_0_pins>;\n+\tpinctrl-names = \"default\";\n+\tstatus = \"okay\";\n+};\n+\n+&sdhc {\n+\tbus-width = <4>;\n+\tmax-frequency = <192000000>;\n+\tmmc-ddr-1_8v;\n+\tmmc-hs200-1_8v;\n+\tnon-removable;\n+\tpinctrl-0 = <&sdc_default_state>;\n+\tpinctrl-names = \"default\";\n+\tstatus = \"okay\";\n+};\n+\n+&sleep_clk {\n+\tclock-frequency = <32000>;\n+};\n+\n+&xo_board {\n+\tclock-frequency = <24000000>;\n+};\n+\n+/* PINCTRL */\n+\n+&tlmm {\n+\tsdc_default_state: sdc-default-state {\n+\t\tclk-pins {\n+\t\t\tpins = \"gpio13\";\n+\t\t\tfunction = \"sdc_clk\";\n+\t\t\tdrive-strength = <8>;\n+\t\t\tbias-disable;\n+\t\t};\n+\n+\t\tcmd-pins {\n+\t\t\tpins = \"gpio12\";\n+\t\t\tfunction = \"sdc_cmd\";\n+\t\t\tdrive-strength = <8>;\n+\t\t\tbias-pull-up;\n+\t\t};\n+\n+\t\tdata-pins {\n+\t\t\tpins = \"gpio8\", \"gpio9\", \"gpio10\", \"gpio11\";\n+\t\t\tfunction = \"sdc_data\";\n+\t\t\tdrive-strength = <8>;\n+\t\t\tbias-pull-up;\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi\nnew file mode 100644\nindex 000000000000..a2ed54264d5c\n--- /dev/null\n+++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi\n@@ -0,0 +1,263 @@\n+// SPDX-License-Identifier: BSD-3-Clause\n+/*\n+ * IPQ5332 device tree source\n+ *\n+ * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.\n+ */\n+\n+#include <dt-bindings/clock/qcom,ipq5332-gcc.h>\n+#include <dt-bindings/interrupt-controller/arm-gic.h>\n+\n+/ {\n+\tinterrupt-parent = <&intc>;\n+\t#address-cells = <2>;\n+\t#size-cells = <2>;\n+\n+\tclocks {\n+\t\tsleep_clk: sleep-clk {\n+\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t#clock-cells = <0>;\n+\t\t};\n+\n+\t\txo_board: xo-board-clk {\n+\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t#clock-cells = <0>;\n+\t\t};\n+\t};\n+\n+\tcpus {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tCPU0: cpu@0 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a53\";\n+\t\t\treg = <0x0>;\n+\t\t\tenable-method = \"psci\";\n+\t\t\tnext-level-cache = <&L2_0>;\n+\t\t};\n+\n+\t\tCPU1: cpu@1 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a53\";\n+\t\t\treg = <0x1>;\n+\t\t\tenable-method = \"psci\";\n+\t\t\tnext-level-cache = <&L2_0>;\n+\t\t};\n+\n+\t\tCPU2: cpu@2 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a53\";\n+\t\t\treg = <0x2>;\n+\t\t\tenable-method = \"psci\";\n+\t\t\tnext-level-cache = <&L2_0>;\n+\t\t};\n+\n+\t\tCPU3: cpu@3 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"arm,cortex-a53\";\n+\t\t\treg = <0x3>;\n+\t\t\tenable-method = \"psci\";\n+\t\t\tnext-level-cache = <&L2_0>;\n+\t\t};\n+\n+\t\tL2_0: l2-cache {\n+\t\t\tcompatible = \"cache\";\n+\t\t\tcache-level = <2>;\n+\t\t};\n+\t};\n+\n+\tfirmware {\n+\t\tscm {\n+\t\t\tcompatible = \"qcom,scm-ipq5332\", \"qcom,scm\";\n+\t\t};\n+\t};\n+\n+\tmemory@40000000 {\n+\t\tdevice_type = \"memory\";\n+\t\t/* We expect the bootloader to fill in the size */\n+\t\treg = <0x0 0x40000000 0x0 0x0>;\n+\t};\n+\n+\tpmu {\n+\t\tcompatible = \"arm,cortex-a53-pmu\";\n+\t\tinterrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n+\t};\n+\n+\tpsci {\n+\t\tcompatible = \"arm,psci-1.0\";\n+\t\tmethod = \"smc\";\n+\t};\n+\n+\treserved-memory {\n+\t\t#address-cells = <2>;\n+\t\t#size-cells = <2>;\n+\t\tranges;\n+\n+\t\ttz_mem: tz@4a600000 {\n+\t\t\treg = <0x0 0x4a600000 0x0 0x200000>;\n+\t\t\tno-map;\n+\t\t};\n+\t};\n+\n+\tsoc@0 {\n+\t\tcompatible = \"simple-bus\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tranges = <0 0 0 0xffffffff>;\n+\n+\t\ttlmm: pinctrl@1000000 {\n+\t\t\tcompatible = \"qcom,ipq5332-tlmm\";\n+\t\t\treg = <0x01000000 0x300000>;\n+\t\t\tinterrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tgpio-controller;\n+\t\t\t#gpio-cells = <2>;\n+\t\t\tgpio-ranges = <&tlmm 0 0 53>;\n+\t\t\tinterrupt-controller;\n+\t\t\t#interrupt-cells = <2>;\n+\n+\t\t\tserial_0_pins: serial0-state {\n+\t\t\t\tpins = \"gpio18\", \"gpio19\";\n+\t\t\t\tfunction = \"blsp0_uart0\";\n+\t\t\t\tdrive-strength = <8>;\n+\t\t\t\tbias-pull-up;\n+\t\t\t};\n+\t\t};\n+\n+\t\tgcc: clock-controller@1800000 {\n+\t\t\tcompatible = \"qcom,ipq5332-gcc\";\n+\t\t\treg = <0x01800000 0x80000>;\n+\t\t\t#clock-cells = <1>;\n+\t\t\t#reset-cells = <1>;\n+\t\t\t#power-domain-cells = <1>;\n+\t\t\tclocks = <&xo_board>,\n+\t\t\t\t <&sleep_clk>,\n+\t\t\t\t <0>,\n+\t\t\t\t <0>,\n+\t\t\t\t <0>;\n+\t\t};\n+\n+\t\tsdhc: mmc@7804000 {\n+\t\t\tcompatible = \"qcom,ipq5332-sdhci\", \"qcom,sdhci-msm-v5\";\n+\t\t\treg = <0x07804000 0x1000>, <0x07805000 0x1000>;\n+\n+\t\t\tinterrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tinterrupt-names = \"hc_irq\", \"pwr_irq\";\n+\n+\t\t\tclocks = <&gcc GCC_SDCC1_AHB_CLK>,\n+\t\t\t\t <&gcc GCC_SDCC1_APPS_CLK>,\n+\t\t\t\t <&xo_board>;\n+\t\t\tclock-names = \"iface\", \"core\", \"xo\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tblsp1_uart0: serial@78af000 {\n+\t\t\tcompatible = \"qcom,msm-uartdm-v1.4\", \"qcom,msm-uartdm\";\n+\t\t\treg = <0x078af000 0x200>;\n+\t\t\tinterrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,\n+\t\t\t\t <&gcc GCC_BLSP1_AHB_CLK>;\n+\t\t\tclock-names = \"core\", \"iface\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tintc: interrupt-controller@b000000 {\n+\t\t\tcompatible = \"qcom,msm-qgic2\";\n+\t\t\treg = <0x0b000000 0x1000>,\t/* GICD */\n+\t\t\t <0x0b002000 0x1000>,\t/* GICC */\n+\t\t\t <0x0b001000 0x1000>,\t/* GICH */\n+\t\t\t <0x0b004000 0x1000>;\t/* GICV */\n+\t\t\tinterrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tinterrupt-controller;\n+\t\t\t#interrupt-cells = <3>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tranges = <0 0x0b00c000 0x3000>;\n+\n+\t\t\tv2m0: v2m@0 {\n+\t\t\t\tcompatible = \"arm,gic-v2m-frame\";\n+\t\t\t\treg = <0x00000000 0xffd>;\n+\t\t\t\tmsi-controller;\n+\t\t\t};\n+\n+\t\t\tv2m1: v2m@1000 {\n+\t\t\t\tcompatible = \"arm,gic-v2m-frame\";\n+\t\t\t\treg = <0x00001000 0xffd>;\n+\t\t\t\tmsi-controller;\n+\t\t\t};\n+\n+\t\t\tv2m2: v2m@2000 {\n+\t\t\t\tcompatible = \"arm,gic-v2m-frame\";\n+\t\t\t\treg = <0x00002000 0xffd>;\n+\t\t\t\tmsi-controller;\n+\t\t\t};\n+\t\t};\n+\n+\t\ttimer@b120000 {\n+\t\t\tcompatible = \"arm,armv7-timer-mem\";\n+\t\t\treg = <0x0b120000 0x1000>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tranges;\n+\n+\t\t\tframe@b120000 {\n+\t\t\t\treg = <0x0b121000 0x1000>,\n+\t\t\t\t <0x0b122000 0x1000>;\n+\t\t\t\tinterrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tframe-number = <0>;\n+\t\t\t};\n+\n+\t\t\tframe@b123000 {\n+\t\t\t\treg = <0x0b123000 0x1000>;\n+\t\t\t\tinterrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tframe-number = <1>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tframe@b124000 {\n+\t\t\t\treg = <0x0b124000 0x1000>;\n+\t\t\t\tinterrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tframe-number = <2>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tframe@b125000 {\n+\t\t\t\treg = <0x0b125000 0x1000>;\n+\t\t\t\tinterrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tframe-number = <3>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tframe@b126000 {\n+\t\t\t\treg = <0x0b126000 0x1000>;\n+\t\t\t\tinterrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tframe-number = <4>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tframe@b127000 {\n+\t\t\t\treg = <0x0b127000 0x1000>;\n+\t\t\t\tinterrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tframe-number = <5>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tframe@b128000 {\n+\t\t\t\treg = <0x0b128000 0x1000>;\n+\t\t\t\tinterrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tframe-number = <6>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\ttimer {\n+\t\tcompatible = \"arm,armv8-timer\";\n+\t\tinterrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,\n+\t\t\t <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,\n+\t\t\t <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,\n+\t\t\t <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;\n+\t};\n+};\n", "prefixes": [ "V5", "6/7" ] }