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GET /api/patches/1744096/?format=api
{ "id": 1744096, "url": "http://patchwork.ozlabs.org/api/patches/1744096/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20230217075835.460-3-quic_kathirav@quicinc.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20230217075835.460-3-quic_kathirav@quicinc.com>", "list_archive_url": null, "date": "2023-02-17T07:58:30", "name": "[V5,2/7] dt-bindings: clock: Add Qualcomm IPQ5332 GCC", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d29b71ae536a17ecdc24d1cc2a688aa02a39f9ca", "submitter": { "id": 83327, "url": "http://patchwork.ozlabs.org/api/people/83327/?format=api", "name": "Kathiravan Thirumoorthy", "email": "quic_kathirav@quicinc.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20230217075835.460-3-quic_kathirav@quicinc.com/mbox/", "series": [ { "id": 342454, "url": "http://patchwork.ozlabs.org/api/series/342454/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=342454", "date": "2023-02-17T07:58:28", "name": "Add minimal boot support for IPQ5332", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/342454/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1744096/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1744096/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-gpio-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2620:137:e000::1:20; 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Thu, 16 Feb 2023 23:59:10 -0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=qcppdkim1;\n bh=FHEJt8mU75cUaYFA6Aqtp4muUQj2B+iy5AAtTW8JVqk=;\n b=LJ/SDbG0U/yUrkAtdKoC5Kboui9Ehab86C82g0opWXINZvMn1KXvgo05IH5YCYNLW6mM\n EY3fDos6e7gYSgbv7XZ1oPrNUJMj9PFwmwbD6Gou84yhlh9FE5C5XnEDgrw266ie3ewY\n 1iCCAXxsG9jS5mpq7s6KoLUJacEEaLk1seRXIWO4nPA5QgdyROaoxxb++aYEZcZ5jSxy\n msSIWsE+yc7sjiKPd01kIv4T6CkfvHZXbcZzyP+rOS+SDPX53+WEwFtOKkfrnorb+vKP\n 6G5SCxNrNVLietnUejaw36OSNchP/FQNsKJbX4NGc0M5Hh7zL7tvqY4pKiYZzF6Y4CX9 rA==", "From": "Kathiravan T <quic_kathirav@quicinc.com>", "To": "<krzysztof.kozlowski@linaro.org>, <agross@kernel.org>,\n <andersson@kernel.org>, <konrad.dybcio@linaro.org>,\n <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,\n <mturquette@baylibre.com>, <sboyd@kernel.org>,\n <linus.walleij@linaro.org>, <catalin.marinas@arm.com>,\n <will@kernel.org>, <shawnguo@kernel.org>, <arnd@arndb.de>,\n <dmitry.baryshkov@linaro.org>, <marcel.ziswiler@toradex.com>,\n <nfraprado@collabora.com>, <robimarko@gmail.com>,\n <quic_gurus@quicinc.com>, <linux-arm-msm@vger.kernel.org>,\n <devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n <linux-clk@vger.kernel.org>, <linux-gpio@vger.kernel.org>,\n <linux-arm-kernel@lists.infradead.org>", "CC": "<quic_varada@quicinc.com>, <quic_srichara@quicinc.com>,\n Kathiravan T <quic_kathirav@quicinc.com>", "Subject": "[PATCH V5 2/7] dt-bindings: clock: Add Qualcomm IPQ5332 GCC", "Date": "Fri, 17 Feb 2023 13:28:30 +0530", "Message-ID": "<20230217075835.460-3-quic_kathirav@quicinc.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20230217075835.460-1-quic_kathirav@quicinc.com>", "References": "<20230217075835.460-1-quic_kathirav@quicinc.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[10.80.80.8]", "X-ClientProxiedBy": "nasanex01b.na.qualcomm.com (10.46.141.250) To\n nalasex01a.na.qualcomm.com (10.47.209.196)", "X-QCInternal": "smtphost", "X-Proofpoint-Virus-Version": [ "vendor=nai engine=6200 definitions=5800\n signatures=585085", "vendor=baseguard\n engine=ICAP:2.0.219,Aquarius:18.0.930,Hydra:6.0.562,FMLib:17.11.170.22\n definitions=2023-02-17_04,2023-02-16_01,2023-02-09_01" ], "X-Proofpoint-ORIG-GUID": "CYoBrNGvuplLE-mFVkkDdXzbUE4vI92V", "X-Proofpoint-GUID": "CYoBrNGvuplLE-mFVkkDdXzbUE4vI92V", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n malwarescore=0 suspectscore=0\n bulkscore=0 spamscore=0 phishscore=0 impostorscore=0 mlxlogscore=999\n clxscore=1015 adultscore=0 lowpriorityscore=0 mlxscore=0\n priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1\n engine=8.12.0-2212070000 definitions=main-2302170071", "X-Spam-Status": "No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS,\n UPPERCASE_50_75 autolearn=no autolearn_force=no version=3.4.6", "X-Spam-Checker-Version": "SpamAssassin 3.4.6 (2021-04-09) on\n lindbergh.monkeyblade.net", "Precedence": "bulk", "List-ID": "<linux-gpio.vger.kernel.org>", "X-Mailing-List": "linux-gpio@vger.kernel.org" }, "content": "Add binding for the Qualcomm IPQ5332 Global Clock Controller.\n\nReviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>\nSigned-off-by: Kathiravan T <quic_kathirav@quicinc.com>\n---\nChanges in V5:\n\t- Dropped the clock-names, as suggested by Bjorn in IPQ9574\n\t series\n\t- Made Bjorn as Maintainer\n\nChanges in V4:\n\t- Pick up the R-b tag\n\nChanges in V3:\n\t- Actually I missed to remove the clocks in V2 which are\n\t supposed to\n\t be removed. In V3 I have removed those and they are\n\t GCC_APSS_AHB_CLK, GCC_APSS_AHB_CLK_SRC, GCC_APSS_AXI_CLK\n\t- For the same, didn't add the Reviewed-By tags from Stephen and\n\t Krzysztof\n\nChanges in V2:\n\t- property 'clocks' is marked required\n\t- Renamed the include file name to match with compatible\n\n .../bindings/clock/qcom,ipq5332-gcc.yaml | 53 +++\n include/dt-bindings/clock/qcom,ipq5332-gcc.h | 356 ++++++++++++++++++\n 2 files changed, 409 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml\n create mode 100644 include/dt-bindings/clock/qcom,ipq5332-gcc.h", "diff": "diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml\nnew file mode 100644\nindex 000000000000..718fe0625424\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml\n@@ -0,0 +1,53 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Qualcomm Global Clock & Reset Controller on IPQ5332\n+\n+maintainers:\n+ - Bjorn Andersson <andersson@kernel.org>\n+\n+description: |\n+ Qualcomm global clock control module provides the clocks, resets and power\n+ domains on IPQ5332.\n+\n+ See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h\n+\n+allOf:\n+ - $ref: qcom,gcc.yaml#\n+\n+properties:\n+ compatible:\n+ const: qcom,ipq5332-gcc\n+\n+ clocks:\n+ items:\n+ - description: Board XO clock source\n+ - description: Sleep clock source\n+ - description: PCIE 2lane PHY pipe clock source\n+ - description: PCIE 2lane x1 PHY pipe clock source (For second lane)\n+ - description: USB PCIE wrapper pipe clock source\n+\n+required:\n+ - compatible\n+ - clocks\n+\n+unevaluatedProperties: false\n+\n+examples:\n+ - |\n+ clock-controller@1800000 {\n+ compatible = \"qcom,ipq5332-gcc\";\n+ reg = <0x01800000 0x80000>;\n+ clocks = <&xo_board>,\n+ <&sleep_clk>,\n+ <&pcie_2lane_phy_pipe_clk>,\n+ <&pcie_2lane_phy_pipe_clk_x1>,\n+ <&usb_pcie_wrapper_pipe_clk>;\n+ #clock-cells = <1>;\n+ #power-domain-cells = <1>;\n+ #reset-cells = <1>;\n+ };\n+...\ndiff --git a/include/dt-bindings/clock/qcom,ipq5332-gcc.h b/include/dt-bindings/clock/qcom,ipq5332-gcc.h\nnew file mode 100644\nindex 000000000000..8a405a0a96d0\n--- /dev/null\n+++ b/include/dt-bindings/clock/qcom,ipq5332-gcc.h\n@@ -0,0 +1,356 @@\n+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */\n+/*\n+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.\n+ */\n+\n+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_IPQ5332_H\n+#define _DT_BINDINGS_CLK_QCOM_GCC_IPQ5332_H\n+\n+#define GPLL0_MAIN\t\t\t\t\t0\n+#define GPLL0\t\t\t\t\t\t1\n+#define GPLL2_MAIN\t\t\t\t\t2\n+#define GPLL2\t\t\t\t\t\t3\n+#define GPLL4_MAIN\t\t\t\t\t4\n+#define GPLL4\t\t\t\t\t\t5\n+#define GCC_ADSS_PWM_CLK\t\t\t\t6\n+#define GCC_ADSS_PWM_CLK_SRC\t\t\t\t7\n+#define GCC_AHB_CLK\t\t\t\t\t8\n+#define GCC_APSS_AXI_CLK_SRC\t\t\t\t9\n+#define GCC_BLSP1_AHB_CLK\t\t\t\t10\n+#define GCC_BLSP1_QUP1_I2C_APPS_CLK\t\t\t11\n+#define GCC_BLSP1_QUP1_SPI_APPS_CLK\t\t\t12\n+#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC\t\t\t13\n+#define GCC_BLSP1_QUP2_I2C_APPS_CLK\t\t\t14\n+#define GCC_BLSP1_QUP2_SPI_APPS_CLK\t\t\t15\n+#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC\t\t\t16\n+#define GCC_BLSP1_QUP3_I2C_APPS_CLK\t\t\t17\n+#define GCC_BLSP1_QUP3_SPI_APPS_CLK\t\t\t18\n+#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC\t\t\t19\n+#define GCC_BLSP1_SLEEP_CLK\t\t\t\t20\n+#define GCC_BLSP1_UART1_APPS_CLK\t\t\t21\n+#define GCC_BLSP1_UART1_APPS_CLK_SRC\t\t\t22\n+#define GCC_BLSP1_UART2_APPS_CLK\t\t\t23\n+#define GCC_BLSP1_UART2_APPS_CLK_SRC\t\t\t24\n+#define GCC_BLSP1_UART3_APPS_CLK\t\t\t25\n+#define GCC_BLSP1_UART3_APPS_CLK_SRC\t\t\t26\n+#define GCC_CE_AHB_CLK\t\t\t\t\t27\n+#define GCC_CE_AXI_CLK\t\t\t\t\t28\n+#define GCC_CE_PCNOC_AHB_CLK\t\t\t\t29\n+#define GCC_CMN_12GPLL_AHB_CLK\t\t\t\t30\n+#define GCC_CMN_12GPLL_APU_CLK\t\t\t\t31\n+#define GCC_CMN_12GPLL_SYS_CLK\t\t\t\t32\n+#define GCC_GP1_CLK\t\t\t\t\t33\n+#define GCC_GP1_CLK_SRC\t\t\t\t\t34\n+#define GCC_GP2_CLK\t\t\t\t\t35\n+#define GCC_GP2_CLK_SRC\t\t\t\t\t36\n+#define GCC_LPASS_CORE_AXIM_CLK\t\t\t\t37\n+#define GCC_LPASS_SWAY_CLK\t\t\t\t38\n+#define GCC_LPASS_SWAY_CLK_SRC\t\t\t\t39\n+#define GCC_MDIO_AHB_CLK\t\t\t\t40\n+#define GCC_MDIO_SLAVE_AHB_CLK\t\t\t\t41\n+#define GCC_MEM_NOC_Q6_AXI_CLK\t\t\t\t42\n+#define GCC_MEM_NOC_TS_CLK\t\t\t\t43\n+#define GCC_NSS_TS_CLK\t\t\t\t\t44\n+#define GCC_NSS_TS_CLK_SRC\t\t\t\t45\n+#define GCC_NSSCC_CLK\t\t\t\t\t46\n+#define GCC_NSSCFG_CLK\t\t\t\t\t47\n+#define GCC_NSSNOC_ATB_CLK\t\t\t\t48\n+#define GCC_NSSNOC_NSSCC_CLK\t\t\t\t49\n+#define GCC_NSSNOC_QOSGEN_REF_CLK\t\t\t50\n+#define GCC_NSSNOC_SNOC_1_CLK\t\t\t\t51\n+#define GCC_NSSNOC_SNOC_CLK\t\t\t\t52\n+#define GCC_NSSNOC_TIMEOUT_REF_CLK\t\t\t53\n+#define GCC_NSSNOC_XO_DCD_CLK\t\t\t\t54\n+#define GCC_PCIE3X1_0_AHB_CLK\t\t\t\t55\n+#define GCC_PCIE3X1_0_AUX_CLK\t\t\t\t56\n+#define GCC_PCIE3X1_0_AXI_CLK_SRC\t\t\t57\n+#define GCC_PCIE3X1_0_AXI_M_CLK\t\t\t\t58\n+#define GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK\t\t\t59\n+#define GCC_PCIE3X1_0_AXI_S_CLK\t\t\t\t60\n+#define GCC_PCIE3X1_0_PIPE_CLK\t\t\t\t61\n+#define GCC_PCIE3X1_0_RCHG_CLK\t\t\t\t62\n+#define GCC_PCIE3X1_0_RCHG_CLK_SRC\t\t\t63\n+#define GCC_PCIE3X1_1_AHB_CLK\t\t\t\t64\n+#define GCC_PCIE3X1_1_AUX_CLK\t\t\t\t65\n+#define GCC_PCIE3X1_1_AXI_CLK_SRC\t\t\t66\n+#define GCC_PCIE3X1_1_AXI_M_CLK\t\t\t\t67\n+#define GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK\t\t\t68\n+#define GCC_PCIE3X1_1_AXI_S_CLK\t\t\t\t69\n+#define GCC_PCIE3X1_1_PIPE_CLK\t\t\t\t70\n+#define GCC_PCIE3X1_1_RCHG_CLK\t\t\t\t71\n+#define GCC_PCIE3X1_1_RCHG_CLK_SRC\t\t\t72\n+#define GCC_PCIE3X1_PHY_AHB_CLK\t\t\t\t73\n+#define GCC_PCIE3X2_AHB_CLK\t\t\t\t74\n+#define GCC_PCIE3X2_AUX_CLK\t\t\t\t75\n+#define GCC_PCIE3X2_AXI_M_CLK\t\t\t\t76\n+#define GCC_PCIE3X2_AXI_M_CLK_SRC\t\t\t77\n+#define GCC_PCIE3X2_AXI_S_BRIDGE_CLK\t\t\t78\n+#define GCC_PCIE3X2_AXI_S_CLK\t\t\t\t79\n+#define GCC_PCIE3X2_AXI_S_CLK_SRC\t\t\t80\n+#define GCC_PCIE3X2_PHY_AHB_CLK\t\t\t\t81\n+#define GCC_PCIE3X2_PIPE_CLK\t\t\t\t82\n+#define GCC_PCIE3X2_RCHG_CLK\t\t\t\t83\n+#define GCC_PCIE3X2_RCHG_CLK_SRC\t\t\t84\n+#define GCC_PCIE_AUX_CLK_SRC\t\t\t\t85\n+#define GCC_PCNOC_AT_CLK\t\t\t\t86\n+#define GCC_PCNOC_BFDCD_CLK_SRC\t\t\t\t87\n+#define GCC_PCNOC_LPASS_CLK\t\t\t\t88\n+#define GCC_PRNG_AHB_CLK\t\t\t\t89\n+#define GCC_Q6_AHB_CLK\t\t\t\t\t90\n+#define GCC_Q6_AHB_S_CLK\t\t\t\t91\n+#define GCC_Q6_AXIM_CLK\t\t\t\t\t92\n+#define GCC_Q6_AXIM_CLK_SRC\t\t\t\t93\n+#define GCC_Q6_AXIS_CLK\t\t\t\t\t94\n+#define GCC_Q6_TSCTR_1TO2_CLK\t\t\t\t95\n+#define GCC_Q6SS_ATBM_CLK\t\t\t\t96\n+#define GCC_Q6SS_PCLKDBG_CLK\t\t\t\t97\n+#define GCC_Q6SS_TRIG_CLK\t\t\t\t98\n+#define GCC_QDSS_AT_CLK\t\t\t\t\t99\n+#define GCC_QDSS_AT_CLK_SRC\t\t\t\t100\n+#define GCC_QDSS_CFG_AHB_CLK\t\t\t\t101\n+#define GCC_QDSS_DAP_AHB_CLK\t\t\t\t102\n+#define GCC_QDSS_DAP_CLK\t\t\t\t103\n+#define GCC_QDSS_DAP_DIV_CLK_SRC\t\t\t104\n+#define GCC_QDSS_ETR_USB_CLK\t\t\t\t105\n+#define GCC_QDSS_EUD_AT_CLK\t\t\t\t106\n+#define GCC_QDSS_TSCTR_CLK_SRC\t\t\t\t107\n+#define GCC_QPIC_AHB_CLK\t\t\t\t108\n+#define GCC_QPIC_CLK\t\t\t\t\t109\n+#define GCC_QPIC_IO_MACRO_CLK\t\t\t\t110\n+#define GCC_QPIC_IO_MACRO_CLK_SRC\t\t\t111\n+#define GCC_QPIC_SLEEP_CLK\t\t\t\t112\n+#define GCC_SDCC1_AHB_CLK\t\t\t\t113\n+#define GCC_SDCC1_APPS_CLK\t\t\t\t114\n+#define GCC_SDCC1_APPS_CLK_SRC\t\t\t\t115\n+#define GCC_SLEEP_CLK_SRC\t\t\t\t116\n+#define GCC_SNOC_LPASS_CFG_CLK\t\t\t\t117\n+#define GCC_SNOC_NSSNOC_1_CLK\t\t\t\t118\n+#define GCC_SNOC_NSSNOC_CLK\t\t\t\t119\n+#define GCC_SNOC_PCIE3_1LANE_1_M_CLK\t\t\t120\n+#define GCC_SNOC_PCIE3_1LANE_1_S_CLK\t\t\t121\n+#define GCC_SNOC_PCIE3_1LANE_M_CLK\t\t\t122\n+#define GCC_SNOC_PCIE3_1LANE_S_CLK\t\t\t123\n+#define GCC_SNOC_PCIE3_2LANE_M_CLK\t\t\t124\n+#define GCC_SNOC_PCIE3_2LANE_S_CLK\t\t\t125\n+#define GCC_SNOC_USB_CLK\t\t\t\t126\n+#define GCC_SYS_NOC_AT_CLK\t\t\t\t127\n+#define GCC_SYS_NOC_WCSS_AHB_CLK\t\t\t128\n+#define GCC_SYSTEM_NOC_BFDCD_CLK_SRC\t\t\t129\n+#define GCC_UNIPHY0_AHB_CLK\t\t\t\t130\n+#define GCC_UNIPHY0_SYS_CLK\t\t\t\t131\n+#define GCC_UNIPHY1_AHB_CLK\t\t\t\t132\n+#define GCC_UNIPHY1_SYS_CLK\t\t\t\t133\n+#define GCC_UNIPHY_SYS_CLK_SRC\t\t\t\t134\n+#define GCC_USB0_AUX_CLK\t\t\t\t135\n+#define GCC_USB0_AUX_CLK_SRC\t\t\t\t136\n+#define GCC_USB0_EUD_AT_CLK\t\t\t\t137\n+#define GCC_USB0_LFPS_CLK\t\t\t\t138\n+#define GCC_USB0_LFPS_CLK_SRC\t\t\t\t139\n+#define GCC_USB0_MASTER_CLK\t\t\t\t140\n+#define GCC_USB0_MASTER_CLK_SRC\t\t\t\t141\n+#define GCC_USB0_MOCK_UTMI_CLK\t\t\t\t142\n+#define GCC_USB0_MOCK_UTMI_CLK_SRC\t\t\t143\n+#define GCC_USB0_MOCK_UTMI_DIV_CLK_SRC\t\t\t144\n+#define GCC_USB0_PHY_CFG_AHB_CLK\t\t\t145\n+#define GCC_USB0_PIPE_CLK\t\t\t\t146\n+#define GCC_USB0_SLEEP_CLK\t\t\t\t147\n+#define GCC_WCSS_AHB_CLK_SRC\t\t\t\t148\n+#define GCC_WCSS_AXIM_CLK\t\t\t\t149\n+#define GCC_WCSS_AXIS_CLK\t\t\t\t150\n+#define GCC_WCSS_DBG_IFC_APB_BDG_CLK\t\t\t151\n+#define GCC_WCSS_DBG_IFC_APB_CLK\t\t\t152\n+#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK\t\t\t153\n+#define GCC_WCSS_DBG_IFC_ATB_CLK\t\t\t154\n+#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK\t\t\t155\n+#define GCC_WCSS_DBG_IFC_NTS_CLK\t\t\t156\n+#define GCC_WCSS_ECAHB_CLK\t\t\t\t157\n+#define GCC_WCSS_MST_ASYNC_BDG_CLK\t\t\t158\n+#define GCC_WCSS_SLV_ASYNC_BDG_CLK\t\t\t159\n+#define GCC_XO_CLK\t\t\t\t\t160\n+#define GCC_XO_CLK_SRC\t\t\t\t\t161\n+#define GCC_XO_DIV4_CLK\t\t\t\t\t162\n+#define GCC_IM_SLEEP_CLK\t\t\t\t163\n+#define GCC_NSSNOC_PCNOC_1_CLK\t\t\t\t164\n+#define GCC_MEM_NOC_AHB_CLK\t\t\t\t165\n+#define GCC_MEM_NOC_APSS_AXI_CLK\t\t\t166\n+#define GCC_SNOC_QOSGEN_EXTREF_DIV_CLK_SRC\t\t167\n+#define GCC_MEM_NOC_QOSGEN_EXTREF_CLK\t\t\t168\n+#define GCC_PCIE3X2_PIPE_CLK_SRC\t\t\t169\n+#define GCC_PCIE3X1_0_PIPE_CLK_SRC\t\t\t170\n+#define GCC_PCIE3X1_1_PIPE_CLK_SRC\t\t\t171\n+#define GCC_USB0_PIPE_CLK_SRC\t\t\t\t172\n+\n+#define GCC_ADSS_BCR\t\t\t\t\t0\n+#define GCC_ADSS_PWM_CLK_ARES\t\t\t\t1\n+#define GCC_AHB_CLK_ARES\t\t\t\t2\n+#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR\t\t3\n+#define GCC_APC0_VOLTAGE_DROOP_DETECTOR_GPLL0_CLK_ARES\t4\n+#define GCC_APSS_AHB_CLK_ARES\t\t\t\t5\n+#define GCC_APSS_AXI_CLK_ARES\t\t\t\t6\n+#define GCC_BLSP1_AHB_CLK_ARES\t\t\t\t7\n+#define GCC_BLSP1_BCR\t\t\t\t\t8\n+#define GCC_BLSP1_QUP1_BCR\t\t\t\t9\n+#define GCC_BLSP1_QUP1_I2C_APPS_CLK_ARES\t\t10\n+#define GCC_BLSP1_QUP1_SPI_APPS_CLK_ARES\t\t11\n+#define GCC_BLSP1_QUP2_BCR\t\t\t\t12\n+#define GCC_BLSP1_QUP2_I2C_APPS_CLK_ARES\t\t13\n+#define GCC_BLSP1_QUP2_SPI_APPS_CLK_ARES\t\t14\n+#define GCC_BLSP1_QUP3_BCR\t\t\t\t15\n+#define GCC_BLSP1_QUP3_I2C_APPS_CLK_ARES\t\t16\n+#define GCC_BLSP1_QUP3_SPI_APPS_CLK_ARES\t\t17\n+#define GCC_BLSP1_SLEEP_CLK_ARES\t\t\t18\n+#define GCC_BLSP1_UART1_APPS_CLK_ARES\t\t\t19\n+#define GCC_BLSP1_UART1_BCR\t\t\t\t20\n+#define GCC_BLSP1_UART2_APPS_CLK_ARES\t\t\t21\n+#define GCC_BLSP1_UART2_BCR\t\t\t\t22\n+#define GCC_BLSP1_UART3_APPS_CLK_ARES\t\t\t23\n+#define GCC_BLSP1_UART3_BCR\t\t\t\t24\n+#define GCC_CE_BCR\t\t\t\t\t25\n+#define GCC_CMN_BLK_BCR\t\t\t\t\t26\n+#define GCC_CMN_LDO0_BCR\t\t\t\t27\n+#define GCC_CMN_LDO1_BCR\t\t\t\t28\n+#define GCC_DCC_BCR\t\t\t\t\t29\n+#define GCC_GP1_CLK_ARES\t\t\t\t30\n+#define GCC_GP2_CLK_ARES\t\t\t\t31\n+#define GCC_LPASS_BCR\t\t\t\t\t32\n+#define GCC_LPASS_CORE_AXIM_CLK_ARES\t\t\t33\n+#define GCC_LPASS_SWAY_CLK_ARES\t\t\t\t34\n+#define GCC_MDIOM_BCR\t\t\t\t\t35\n+#define GCC_MDIOS_BCR\t\t\t\t\t36\n+#define GCC_NSS_BCR\t\t\t\t\t37\n+#define GCC_NSS_TS_CLK_ARES\t\t\t\t38\n+#define GCC_NSSCC_CLK_ARES\t\t\t\t39\n+#define GCC_NSSCFG_CLK_ARES\t\t\t\t40\n+#define GCC_NSSNOC_ATB_CLK_ARES\t\t\t\t41\n+#define GCC_NSSNOC_NSSCC_CLK_ARES\t\t\t42\n+#define GCC_NSSNOC_QOSGEN_REF_CLK_ARES\t\t\t43\n+#define GCC_NSSNOC_SNOC_1_CLK_ARES\t\t\t44\n+#define GCC_NSSNOC_SNOC_CLK_ARES\t\t\t45\n+#define GCC_NSSNOC_TIMEOUT_REF_CLK_ARES\t\t\t46\n+#define GCC_NSSNOC_XO_DCD_CLK_ARES\t\t\t47\n+#define GCC_PCIE3X1_0_AHB_CLK_ARES\t\t\t48\n+#define GCC_PCIE3X1_0_AUX_CLK_ARES\t\t\t49\n+#define GCC_PCIE3X1_0_AXI_M_CLK_ARES\t\t\t50\n+#define GCC_PCIE3X1_0_AXI_S_BRIDGE_CLK_ARES\t\t51\n+#define GCC_PCIE3X1_0_AXI_S_CLK_ARES\t\t\t52\n+#define GCC_PCIE3X1_0_BCR\t\t\t\t53\n+#define GCC_PCIE3X1_0_LINK_DOWN_BCR\t\t\t54\n+#define GCC_PCIE3X1_0_PHY_BCR\t\t\t\t55\n+#define GCC_PCIE3X1_0_PHY_PHY_BCR\t\t\t56\n+#define GCC_PCIE3X1_1_AHB_CLK_ARES\t\t\t57\n+#define GCC_PCIE3X1_1_AUX_CLK_ARES\t\t\t58\n+#define GCC_PCIE3X1_1_AXI_M_CLK_ARES\t\t\t59\n+#define GCC_PCIE3X1_1_AXI_S_BRIDGE_CLK_ARES\t\t60\n+#define GCC_PCIE3X1_1_AXI_S_CLK_ARES\t\t\t61\n+#define GCC_PCIE3X1_1_BCR\t\t\t\t62\n+#define GCC_PCIE3X1_1_LINK_DOWN_BCR\t\t\t63\n+#define GCC_PCIE3X1_1_PHY_BCR\t\t\t\t64\n+#define GCC_PCIE3X1_1_PHY_PHY_BCR\t\t\t65\n+#define GCC_PCIE3X1_PHY_AHB_CLK_ARES\t\t\t66\n+#define GCC_PCIE3X2_AHB_CLK_ARES\t\t\t67\n+#define GCC_PCIE3X2_AUX_CLK_ARES\t\t\t68\n+#define GCC_PCIE3X2_AXI_M_CLK_ARES\t\t\t69\n+#define GCC_PCIE3X2_AXI_S_BRIDGE_CLK_ARES\t\t70\n+#define GCC_PCIE3X2_AXI_S_CLK_ARES\t\t\t71\n+#define GCC_PCIE3X2_BCR\t\t\t\t\t72\n+#define GCC_PCIE3X2_LINK_DOWN_BCR\t\t\t73\n+#define GCC_PCIE3X2_PHY_AHB_CLK_ARES\t\t\t74\n+#define GCC_PCIE3X2_PHY_BCR\t\t\t\t75\n+#define GCC_PCIE3X2PHY_PHY_BCR\t\t\t\t76\n+#define GCC_PCNOC_BCR\t\t\t\t\t77\n+#define GCC_PCNOC_LPASS_CLK_ARES\t\t\t78\n+#define GCC_PRNG_AHB_CLK_ARES\t\t\t\t79\n+#define GCC_PRNG_BCR\t\t\t\t\t80\n+#define GCC_Q6_AHB_CLK_ARES\t\t\t\t81\n+#define GCC_Q6_AHB_S_CLK_ARES\t\t\t\t82\n+#define GCC_Q6_AXIM_CLK_ARES\t\t\t\t83\n+#define GCC_Q6_AXIS_CLK_ARES\t\t\t\t84\n+#define GCC_Q6_TSCTR_1TO2_CLK_ARES\t\t\t85\n+#define GCC_Q6SS_ATBM_CLK_ARES\t\t\t\t86\n+#define GCC_Q6SS_PCLKDBG_CLK_ARES\t\t\t87\n+#define GCC_Q6SS_TRIG_CLK_ARES\t\t\t\t88\n+#define GCC_QDSS_APB2JTAG_CLK_ARES\t\t\t89\n+#define GCC_QDSS_AT_CLK_ARES\t\t\t\t90\n+#define GCC_QDSS_BCR\t\t\t\t\t91\n+#define GCC_QDSS_CFG_AHB_CLK_ARES\t\t\t92\n+#define GCC_QDSS_DAP_AHB_CLK_ARES\t\t\t93\n+#define GCC_QDSS_DAP_CLK_ARES\t\t\t\t94\n+#define GCC_QDSS_ETR_USB_CLK_ARES\t\t\t95\n+#define GCC_QDSS_EUD_AT_CLK_ARES\t\t\t96\n+#define GCC_QDSS_STM_CLK_ARES\t\t\t\t97\n+#define GCC_QDSS_TRACECLKIN_CLK_ARES\t\t\t98\n+#define GCC_QDSS_TS_CLK_ARES\t\t\t\t99\n+#define GCC_QDSS_TSCTR_DIV16_CLK_ARES\t\t\t100\n+#define GCC_QDSS_TSCTR_DIV2_CLK_ARES\t\t\t101\n+#define GCC_QDSS_TSCTR_DIV3_CLK_ARES\t\t\t102\n+#define GCC_QDSS_TSCTR_DIV4_CLK_ARES\t\t\t103\n+#define GCC_QDSS_TSCTR_DIV8_CLK_ARES\t\t\t104\n+#define GCC_QPIC_AHB_CLK_ARES\t\t\t\t105\n+#define GCC_QPIC_CLK_ARES\t\t\t\t106\n+#define GCC_QPIC_BCR\t\t\t\t\t107\n+#define GCC_QPIC_IO_MACRO_CLK_ARES\t\t\t108\n+#define GCC_QPIC_SLEEP_CLK_ARES\t\t\t\t109\n+#define GCC_QUSB2_0_PHY_BCR\t\t\t\t110\n+#define GCC_SDCC1_AHB_CLK_ARES\t\t\t\t111\n+#define GCC_SDCC1_APPS_CLK_ARES\t\t\t\t112\n+#define GCC_SDCC_BCR\t\t\t\t\t113\n+#define GCC_SNOC_BCR\t\t\t\t\t114\n+#define GCC_SNOC_LPASS_CFG_CLK_ARES\t\t\t115\n+#define GCC_SNOC_NSSNOC_1_CLK_ARES\t\t\t116\n+#define GCC_SNOC_NSSNOC_CLK_ARES\t\t\t117\n+#define GCC_SYS_NOC_QDSS_STM_AXI_CLK_ARES\t\t118\n+#define GCC_SYS_NOC_WCSS_AHB_CLK_ARES\t\t\t119\n+#define GCC_UNIPHY0_AHB_CLK_ARES\t\t\t120\n+#define GCC_UNIPHY0_BCR\t\t\t\t\t121\n+#define GCC_UNIPHY0_SYS_CLK_ARES\t\t\t122\n+#define GCC_UNIPHY1_AHB_CLK_ARES\t\t\t123\n+#define GCC_UNIPHY1_BCR\t\t\t\t\t124\n+#define GCC_UNIPHY1_SYS_CLK_ARES\t\t\t125\n+#define GCC_USB0_AUX_CLK_ARES\t\t\t\t126\n+#define GCC_USB0_EUD_AT_CLK_ARES\t\t\t127\n+#define GCC_USB0_LFPS_CLK_ARES\t\t\t\t128\n+#define GCC_USB0_MASTER_CLK_ARES\t\t\t129\n+#define GCC_USB0_MOCK_UTMI_CLK_ARES\t\t\t130\n+#define GCC_USB0_PHY_BCR\t\t\t\t131\n+#define GCC_USB0_PHY_CFG_AHB_CLK_ARES\t\t\t132\n+#define GCC_USB0_SLEEP_CLK_ARES\t\t\t\t133\n+#define GCC_USB3PHY_0_PHY_BCR\t\t\t\t134\n+#define GCC_USB_BCR\t\t\t\t\t135\n+#define GCC_WCSS_AXIM_CLK_ARES\t\t\t\t136\n+#define GCC_WCSS_AXIS_CLK_ARES\t\t\t\t137\n+#define GCC_WCSS_BCR\t\t\t\t\t138\n+#define GCC_WCSS_DBG_IFC_APB_BDG_CLK_ARES\t\t139\n+#define GCC_WCSS_DBG_IFC_APB_CLK_ARES\t\t\t140\n+#define GCC_WCSS_DBG_IFC_ATB_BDG_CLK_ARES\t\t141\n+#define GCC_WCSS_DBG_IFC_ATB_CLK_ARES\t\t\t142\n+#define GCC_WCSS_DBG_IFC_NTS_BDG_CLK_ARES\t\t143\n+#define GCC_WCSS_DBG_IFC_NTS_CLK_ARES\t\t\t144\n+#define GCC_WCSS_ECAHB_CLK_ARES\t\t\t\t145\n+#define GCC_WCSS_MST_ASYNC_BDG_CLK_ARES\t\t\t146\n+#define GCC_WCSS_Q6_BCR\t\t\t\t\t147\n+#define GCC_WCSS_SLV_ASYNC_BDG_CLK_ARES\t\t\t148\n+#define GCC_XO_CLK_ARES\t\t\t\t\t149\n+#define GCC_XO_DIV4_CLK_ARES\t\t\t\t150\n+#define GCC_Q6SS_DBG_ARES\t\t\t\t151\n+#define GCC_WCSS_DBG_BDG_ARES\t\t\t\t152\n+#define GCC_WCSS_DBG_ARES\t\t\t\t153\n+#define GCC_WCSS_AXI_S_ARES\t\t\t\t154\n+#define GCC_WCSS_AXI_M_ARES\t\t\t\t155\n+#define GCC_WCSSAON_ARES\t\t\t\t156\n+#define GCC_PCIE3X2_PIPE_ARES\t\t\t\t157\n+#define GCC_PCIE3X2_CORE_STICKY_ARES\t\t\t158\n+#define GCC_PCIE3X2_AXI_S_STICKY_ARES\t\t\t159\n+#define GCC_PCIE3X2_AXI_M_STICKY_ARES\t\t\t160\n+#define GCC_PCIE3X1_0_PIPE_ARES\t\t\t\t161\n+#define GCC_PCIE3X1_0_CORE_STICKY_ARES\t\t\t162\n+#define GCC_PCIE3X1_0_AXI_S_STICKY_ARES\t\t\t163\n+#define GCC_PCIE3X1_0_AXI_M_STICKY_ARES\t\t\t164\n+#define GCC_PCIE3X1_1_PIPE_ARES\t\t\t\t165\n+#define GCC_PCIE3X1_1_CORE_STICKY_ARES\t\t\t166\n+#define GCC_PCIE3X1_1_AXI_S_STICKY_ARES\t\t\t167\n+#define GCC_PCIE3X1_1_AXI_M_STICKY_ARES\t\t\t168\n+#define GCC_IM_SLEEP_CLK_ARES\t\t\t\t169\n+#define GCC_NSSNOC_PCNOC_1_CLK_ARES\t\t\t170\n+#define GCC_UNIPHY0_XPCS_ARES\t\t\t\t171\n+#define GCC_UNIPHY1_XPCS_ARES\t\t\t\t172\n+#endif\n", "prefixes": [ "V5", "2/7" ] }