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GET /api/patches/1644802/?format=api
HTTP 200 OK
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{
    "id": 1644802,
    "url": "http://patchwork.ozlabs.org/api/patches/1644802/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20220617104726.158688-12-pan@semihalf.com/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20220617104726.158688-12-pan@semihalf.com>",
    "list_archive_url": null,
    "date": "2022-06-17T10:47:26",
    "name": "[v3,11/11] socfpga: arria10: Allow dcache_enable before relocation",
    "commit_ref": "e26ecebc684bfe74f6c27cca151c3490d1ed5d8f",
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "2065784ceae27c173762dea96c8780b8f6a4e8a1",
    "submitter": {
        "id": 82560,
        "url": "http://patchwork.ozlabs.org/api/people/82560/?format=api",
        "name": "Paweł Anikiel",
        "email": "pan@semihalf.com"
    },
    "delegate": {
        "id": 88515,
        "url": "http://patchwork.ozlabs.org/api/users/88515/?format=api",
        "username": "simongoldschmidt",
        "first_name": "Simon",
        "last_name": "Goldschmidt",
        "email": "simon.k.r.goldschmidt@gmail.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20220617104726.158688-12-pan@semihalf.com/mbox/",
    "series": [
        {
            "id": 305278,
            "url": "http://patchwork.ozlabs.org/api/series/305278/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=305278",
            "date": "2022-06-17T10:47:15",
            "name": "Add Chameleon v3 support",
            "version": 3,
            "mbox": "http://patchwork.ozlabs.org/series/305278/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/1644802/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/1644802/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "=?utf-8?q?Pawe=C5=82_Anikiel?= <pan@semihalf.com>",
        "To": "marex@denx.de, simon.k.r.goldschmidt@gmail.com, tien.fong.chee@intel.com,\n michal.simek@xilinx.com",
        "Cc": "u-boot@lists.denx.de, sjg@chromium.org, festevam@denx.de,\n jagan@amarulasolutions.com, andre.przywara@arm.com, narmstrong@baylibre.com,\n pbrobinson@gmail.com, tharvey@gateworks.com, paul.liu@linaro.org,\n christianshewitt@gmail.com, adrian.fiergolski@fastree3d.com,\n marek.behun@nic.cz, wd@denx.de, elly.siew.chin.lim@intel.com,\n upstream@semihalf.com, amstan@chromium.org,\n =?utf-8?q?Pawe=C5=82_Anikiel?= <pan@semihalf.com>",
        "Subject": "[PATCH v3 11/11] socfpga: arria10: Allow dcache_enable before\n relocation",
        "Date": "Fri, 17 Jun 2022 12:47:26 +0200",
        "Message-Id": "<20220617104726.158688-12-pan@semihalf.com>",
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    "content": "Before relocating to SDRAM, the ECC is initialized by clearing the\nwhole SDRAM. In order to speed this up, dcache_enable is used (see\nsdram_init_ecc_bits).\n\nSince commit 503eea451903 (\"arm: cp15: update DACR value to activate\naccess control\"), this no longer works, because running code in OCRAM\nwith the XN bit set causes a page fault. Override dram_bank_mmu_setup\nto disable XN in the OCRAM and setup DRAM dcache before relocation.\n\nSigned-off-by: Paweł Anikiel <pan@semihalf.com>\nReviewed-by: Simon Glass <sjg@chromium.org>\n---\n arch/arm/mach-socfpga/misc_arria10.c | 26 ++++++++++++++++++++++++++\n 1 file changed, 26 insertions(+)",
    "diff": "diff --git a/arch/arm/mach-socfpga/misc_arria10.c b/arch/arm/mach-socfpga/misc_arria10.c\nindex 0ed2adfd84..7ce888d197 100644\n--- a/arch/arm/mach-socfpga/misc_arria10.c\n+++ b/arch/arm/mach-socfpga/misc_arria10.c\n@@ -246,3 +246,29 @@ int qspi_flash_software_reset(void)\n \treturn 0;\n }\n #endif\n+\n+void dram_bank_mmu_setup(int bank)\n+{\n+\tstruct bd_info *bd = gd->bd;\n+\tu32 start, size;\n+\tint i;\n+\n+\t/* If we're still in OCRAM, don't set the XN bit on it */\n+\tif (!(gd->flags & GD_FLG_RELOC)) {\n+\t\tset_section_dcache(\n+\t\t\tCONFIG_SYS_INIT_RAM_ADDR >> MMU_SECTION_SHIFT,\n+\t\t\tDCACHE_WRITETHROUGH);\n+\t}\n+\n+\t/*\n+\t * The default implementation of this function allows the DRAM dcache\n+\t * to be enabled only after relocation. However, to speed up ECC\n+\t * initialization, we want to be able to enable DRAM dcache before\n+\t * relocation, so we don't check GD_FLG_RELOC (this assumes bd->bi_dram\n+\t * is set first).\n+\t */\n+\tstart = bd->bi_dram[bank].start >> MMU_SECTION_SHIFT;\n+\tsize = bd->bi_dram[bank].size >> MMU_SECTION_SHIFT;\n+\tfor (i = start; i < start + size; i++)\n+\t\tset_section_dcache(i, DCACHE_DEFAULT_OPTION);\n+}\n",
    "prefixes": [
        "v3",
        "11/11"
    ]
}