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GET /api/patches/1644800/?format=api
{ "id": 1644800, "url": "http://patchwork.ozlabs.org/api/patches/1644800/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20220617104726.158688-10-pan@semihalf.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20220617104726.158688-10-pan@semihalf.com>", "list_archive_url": null, "date": "2022-06-17T10:47:24", "name": "[v3,09/11] socfpga: arria10: Improve bitstream loading speed", "commit_ref": "8b1eee3730fc603fcacc5818b71a0e194bc55892", "pull_url": null, "state": "accepted", "archived": false, "hash": "4523693f0218fcfe9e4b11914870ade7a50f6b68", "submitter": { "id": 82560, "url": "http://patchwork.ozlabs.org/api/people/82560/?format=api", "name": "Paweł Anikiel", "email": "pan@semihalf.com" }, "delegate": { "id": 88515, "url": "http://patchwork.ozlabs.org/api/users/88515/?format=api", "username": "simongoldschmidt", "first_name": "Simon", "last_name": "Goldschmidt", "email": "simon.k.r.goldschmidt@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20220617104726.158688-10-pan@semihalf.com/mbox/", "series": [ { "id": 305278, "url": "http://patchwork.ozlabs.org/api/series/305278/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=305278", "date": "2022-06-17T10:47:15", "name": "Add Chameleon v3 support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/305278/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1644800/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1644800/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "bilbo.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=semihalf.com header.i=@semihalf.com header.a=rsa-sha256\n header.s=google header.b=q+y1iJZC;\n\tdkim-atps=neutral", "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=semihalf.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=semihalf.com header.i=@semihalf.com\n header.b=\"q+y1iJZC\";\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=semihalf.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=pan@semihalf.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (2048 bits))\n\t(No client certificate requested)\n\tby bilbo.ozlabs.org (Postfix) with ESMTPS id 4LPbQV3CvHz9s5V\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 17 Jun 2022 20:49:38 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 9434584435;\n\tFri, 17 Jun 2022 12:48:24 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id 2F2E38445A; Fri, 17 Jun 2022 12:48:23 +0200 (CEST)", "from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com\n [IPv6:2a00:1450:4864:20::12e])\n (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id CF3AF8442C\n for <u-boot@lists.denx.de>; Fri, 17 Jun 2022 12:48:20 +0200 (CEST)", "by mail-lf1-x12e.google.com with SMTP id a29so6359120lfk.2\n for <u-boot@lists.denx.de>; Fri, 17 Jun 2022 03:48:20 -0700 (PDT)", "from panikiel.roam.corp.google.com\n (staticline-31-182-204-250.toya.net.pl. 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.5 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Apply some optimizations to speed up bitstream loading\n(both for full and split periph/core bitstreams):\n\n * Change the size of the first fs read, so that all the subsequent\n reads are aligned to a specific value (called MAX_FIRST_LOAD_SIZE).\n This value was chosen so that in subsequent reads the fat fs driver\n doesn't have to allocate a temporary buffer in get_contents\n (assuming 8KiB clusters).\n\n * Change the buffer size to a larger value when reading to ddr\n (but not too large, because large transfers cause a stack overflow\n in the dwmmc driver).\n\nSigned-off-by: Paweł Anikiel <pan@semihalf.com>\nReviewed-by: Simon Glass <sjg@chromium.org>\n---\n drivers/fpga/socfpga_arria10.c | 20 ++++++++++++++++++--\n 1 file changed, 18 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c\nindex 798e3a3f90..07bfe3060e 100644\n--- a/drivers/fpga/socfpga_arria10.c\n+++ b/drivers/fpga/socfpga_arria10.c\n@@ -30,6 +30,14 @@\n #define FPGA_TIMEOUT_MSEC\t1000 /* timeout in ms */\n #define FPGA_TIMEOUT_CNT\t0x1000000\n #define DEFAULT_DDR_LOAD_ADDRESS\t0x400\n+#define DDR_BUFFER_SIZE\t\t0x100000\n+\n+/* When reading bitstream from a filesystem, the size of the first read is\n+ * changed so that the subsequent reads are aligned to this value. This value\n+ * was chosen so that in subsequent reads the fat fs driver doesn't have to\n+ * allocate a temporary buffer in get_contents (assuming 8KiB clusters).\n+ */\n+#define MAX_FIRST_LOAD_SIZE\t0x2000\n \n DECLARE_GLOBAL_DATA_PTR;\n \n@@ -526,7 +534,8 @@ static void get_rbf_image_info(struct rbf_info *rbf, u16 *buffer)\n #ifdef CONFIG_FS_LOADER\n static int first_loading_rbf_to_buffer(struct udevice *dev,\n \t\t\t\tstruct fpga_loadfs_info *fpga_loadfs,\n-\t\t\t\tu32 *buffer, size_t *buffer_bsize)\n+\t\t\t\tu32 *buffer, size_t *buffer_bsize,\n+\t\t\t\tsize_t *buffer_bsize_ori)\n {\n \tu32 *buffer_p = (u32 *)*buffer;\n \tu32 *loadable = buffer_p;\n@@ -674,6 +683,7 @@ static int first_loading_rbf_to_buffer(struct udevice *dev,\n \t\t}\n \n \t\tbuffer_size = rbf_size;\n+\t\t*buffer_bsize_ori = DDR_BUFFER_SIZE;\n \t}\n \n \tdebug(\"FPGA: External data: offset = 0x%x, size = 0x%x.\\n\",\n@@ -686,11 +696,16 @@ static int first_loading_rbf_to_buffer(struct udevice *dev,\n \t * chunk by chunk transfer is required due to smaller buffer size\n \t * compare to bitstream\n \t */\n+\n+\tif (buffer_size > MAX_FIRST_LOAD_SIZE)\n+\t\tbuffer_size = MAX_FIRST_LOAD_SIZE;\n+\n \tif (rbf_size <= buffer_size) {\n \t\t/* Loading whole bitstream into buffer */\n \t\tbuffer_size = rbf_size;\n \t\tfpga_loadfs->remaining = 0;\n \t} else {\n+\t\tbuffer_size -= rbf_offset % buffer_size;\n \t\tfpga_loadfs->remaining -= buffer_size;\n \t}\n \n@@ -806,7 +821,8 @@ int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize,\n \t * function below.\n \t */\n \tret = first_loading_rbf_to_buffer(dev, &fpga_loadfs, &buffer,\n-\t\t\t\t\t &buffer_sizebytes);\n+\t\t\t\t\t &buffer_sizebytes,\n+\t\t\t\t\t &buffer_sizebytes_ori);\n \tif (ret == 1) {\n \t\tprintf(\"FPGA: Skipping configuration ...\\n\");\n \t\treturn 0;\n", "prefixes": [ "v3", "09/11" ] }