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GET /api/patches/1644799/?format=api
{ "id": 1644799, "url": "http://patchwork.ozlabs.org/api/patches/1644799/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20220617104726.158688-9-pan@semihalf.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20220617104726.158688-9-pan@semihalf.com>", "list_archive_url": null, "date": "2022-06-17T10:47:23", "name": "[v3,08/11] socfpga: arria10: Replace delays with busy waiting in cm_full_cfg", "commit_ref": "aea0e80a9feff740a6cb6323c67452bc5a752e4d", "pull_url": null, "state": "accepted", "archived": false, "hash": "cad52c5903cdc74af80bc49620e9c35ff5cfa646", "submitter": { "id": 82560, "url": "http://patchwork.ozlabs.org/api/people/82560/?format=api", "name": "Paweł Anikiel", "email": "pan@semihalf.com" }, "delegate": { "id": 88515, "url": "http://patchwork.ozlabs.org/api/users/88515/?format=api", "username": "simongoldschmidt", "first_name": "Simon", "last_name": "Goldschmidt", "email": "simon.k.r.goldschmidt@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20220617104726.158688-9-pan@semihalf.com/mbox/", "series": [ { "id": 305278, "url": "http://patchwork.ozlabs.org/api/series/305278/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=305278", "date": "2022-06-17T10:47:15", "name": "Add Chameleon v3 support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/305278/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1644799/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1644799/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "bilbo.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=semihalf.com header.i=@semihalf.com header.a=rsa-sha256\n header.s=google header.b=IAXT0mIi;\n\tdkim-atps=neutral", "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=semihalf.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=semihalf.com header.i=@semihalf.com\n header.b=\"IAXT0mIi\";\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=semihalf.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=pan@semihalf.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (2048 bits))\n\t(No client certificate requested)\n\tby bilbo.ozlabs.org (Postfix) with ESMTPS id 4LPbQH5hflz9s5V\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 17 Jun 2022 20:49:27 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 22A4F84442;\n\tFri, 17 Jun 2022 12:48:21 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id 89ECC843DB; Fri, 17 Jun 2022 12:48:18 +0200 (CEST)", "from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com\n [IPv6:2a00:1450:4864:20::22a])\n (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 00A2384435\n for <u-boot@lists.denx.de>; Fri, 17 Jun 2022 12:48:15 +0200 (CEST)", "by mail-lj1-x22a.google.com with SMTP id d18so4321094ljc.4\n for <u-boot@lists.denx.de>; Fri, 17 Jun 2022 03:48:15 -0700 (PDT)", "from panikiel.roam.corp.google.com\n (staticline-31-182-204-250.toya.net.pl. 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Use sdelay and wait_on_value\ninstead (the values used in these functions were found experimentally).\n\nSigned-off-by: Paweł Anikiel <pan@semihalf.com>\n---\n arch/arm/mach-socfpga/clock_manager_arria10.c | 31 +++++++++++++------\n 1 file changed, 22 insertions(+), 9 deletions(-)", "diff": "diff --git a/arch/arm/mach-socfpga/clock_manager_arria10.c b/arch/arm/mach-socfpga/clock_manager_arria10.c\nindex 58d5d3fd8a..b48a2b47bc 100644\n--- a/arch/arm/mach-socfpga/clock_manager_arria10.c\n+++ b/arch/arm/mach-socfpga/clock_manager_arria10.c\n@@ -15,6 +15,10 @@\n \n #ifdef CONFIG_SPL_BUILD\n \n+void sdelay(unsigned long loops);\n+u32 wait_on_value(u32 read_bit_mask, u32 match_value, void *read_addr,\n+\t\t u32 bound);\n+\n static u32 eosc1_hz;\n static u32 cb_intosc_hz;\n static u32 f2s_free_hz;\n@@ -551,13 +555,13 @@ static void cm_pll_ramp_main(struct mainpll_cfg *main_cfg,\n \t\t\tCLKMGR_MAINPLL_VCO1_DENOM_LSB) |\n \t\t\tcm_calc_safe_pll_numer(0, main_cfg, per_cfg, clk_hz),\n \t\t\tsocfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);\n-\t\tmdelay(1);\n+\t\tsdelay(1000000); /* 1ms */\n \t\tcm_wait_for_lock(LOCKED_MASK);\n \t}\n \twritel((main_cfg->vco1_denom << CLKMGR_MAINPLL_VCO1_DENOM_LSB) |\n \t\tmain_cfg->vco1_numer,\n \t\tsocfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO1);\n-\tmdelay(1);\n+\tsdelay(1000000); /* 1ms */\n \tcm_wait_for_lock(LOCKED_MASK);\n }\n \n@@ -585,16 +589,25 @@ static void cm_pll_ramp_periph(struct mainpll_cfg *main_cfg,\n \t\t\t\t\t\t clk_hz),\n \t\t\t socfpga_get_clkmgr_addr() +\n \t\t\t CLKMGR_A10_PERPLL_VCO1);\n-\t\tmdelay(1);\n+\t\tsdelay(1000000); /* 1ms */\n \t\tcm_wait_for_lock(LOCKED_MASK);\n \t}\n \twritel((per_cfg->vco1_denom << CLKMGR_PERPLL_VCO1_DENOM_LSB) |\n \t\t per_cfg->vco1_numer,\n \t\t socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);\n-\tmdelay(1);\n+\tsdelay(1000000); /* 1ms */\n \tcm_wait_for_lock(LOCKED_MASK);\n }\n \n+/* function to poll in the fsm busy bit */\n+static int cm_busy_wait_for_fsm(void)\n+{\n+\tvoid *reg = (void *)(socfpga_get_clkmgr_addr() + CLKMGR_STAT);\n+\n+\t/* 20s timeout */\n+\treturn wait_on_value(CLKMGR_STAT_BUSY, 0, reg, 100000000);\n+}\n+\n /*\n * Setup clocks while making no assumptions of the\n * previous state of the clocks.\n@@ -727,7 +740,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)\n \t\t\tsocfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_VCO1);\n \n \t/* Wait for at least 5 us */\n-\tudelay(5);\n+\tsdelay(5000);\n \n \t/* Now deassert BGPWRDN and PWRDN */\n \tclrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0,\n@@ -738,7 +751,7 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)\n \t\t CLKMGR_PERPLL_VCO0_PWRDN_SET_MSK);\n \n \t/* Wait for at least 7 us */\n-\tudelay(7);\n+\tsdelay(7000);\n \n \t/* enable the VCO and disable the external regulator to PLL */\n \twritel((readl(socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_VCO0) &\n@@ -878,19 +891,19 @@ static int cm_full_cfg(struct mainpll_cfg *main_cfg, struct perpll_cfg *per_cfg)\n \twritel(CLKMGR_MAINPLL_BYPASS_RESET,\n \t socfpga_get_clkmgr_addr() + CLKMGR_A10_MAINPLL_BYPASSR);\n \t/* wait till Clock Manager is not busy */\n-\tcm_wait_for_fsm();\n+\tcm_busy_wait_for_fsm();\n \n \t/* release perpll from bypass */\n \twritel(CLKMGR_PERPLL_BYPASS_RESET,\n \t socfpga_get_clkmgr_addr() + CLKMGR_A10_PERPLL_BYPASSR);\n \t/* wait till Clock Manager is not busy */\n-\tcm_wait_for_fsm();\n+\tcm_busy_wait_for_fsm();\n \n \t/* clear boot mode */\n \tclrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_A10_CTRL,\n \t\t CLKMGR_CLKMGR_CTL_BOOTMOD_SET_MSK);\n \t/* wait till Clock Manager is not busy */\n-\tcm_wait_for_fsm();\n+\tcm_busy_wait_for_fsm();\n \n \t/* At here, we need to ramp to final value if needed */\n \tif (pll_ramp_main_hz != 0)\n", "prefixes": [ "v3", "08/11" ] }