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GET /api/patches/1644796/?format=api
{ "id": 1644796, "url": "http://patchwork.ozlabs.org/api/patches/1644796/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20220617104726.158688-6-pan@semihalf.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20220617104726.158688-6-pan@semihalf.com>", "list_archive_url": null, "date": "2022-06-17T10:47:20", "name": "[v3,05/11] config: Add Chameleonv3 config", "commit_ref": "61298270c56d14f55e26ac17c8b5e110aa13e12c", "pull_url": null, "state": "accepted", "archived": false, "hash": "428a07f3d2b4845667b919c7c34ab3e11f776490", "submitter": { "id": 82560, "url": "http://patchwork.ozlabs.org/api/people/82560/?format=api", "name": "Paweł Anikiel", "email": "pan@semihalf.com" }, "delegate": { "id": 88515, "url": "http://patchwork.ozlabs.org/api/users/88515/?format=api", "username": "simongoldschmidt", "first_name": "Simon", "last_name": "Goldschmidt", "email": "simon.k.r.goldschmidt@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20220617104726.158688-6-pan@semihalf.com/mbox/", "series": [ { "id": 305278, "url": "http://patchwork.ozlabs.org/api/series/305278/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=305278", "date": "2022-06-17T10:47:15", "name": "Add Chameleon v3 support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/305278/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1644796/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1644796/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "bilbo.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=semihalf.com header.i=@semihalf.com header.a=rsa-sha256\n header.s=google header.b=onWK1hUI;\n\tdkim-atps=neutral", "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=semihalf.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=semihalf.com header.i=@semihalf.com\n header.b=\"onWK1hUI\";\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=semihalf.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=pan@semihalf.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (2048 bits))\n\t(No client certificate requested)\n\tby bilbo.ozlabs.org (Postfix) with ESMTPS id 4LPbPf6Hf8z9s5V\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 17 Jun 2022 20:48:54 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 72E16843D3;\n\tFri, 17 Jun 2022 12:48:01 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id 65F4D8443B; Fri, 17 Jun 2022 12:47:56 +0200 (CEST)", "from mail-lj1-x22a.google.com (mail-lj1-x22a.google.com\n [IPv6:2a00:1450:4864:20::22a])\n (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id CA216843E9\n for <u-boot@lists.denx.de>; Fri, 17 Jun 2022 12:47:50 +0200 (CEST)", "by mail-lj1-x22a.google.com with SMTP id w2so962910lji.5\n for <u-boot@lists.denx.de>; Fri, 17 Jun 2022 03:47:50 -0700 (PDT)", "from panikiel.roam.corp.google.com\n (staticline-31-182-204-250.toya.net.pl. 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"X-Virus-Scanned": "clamav-milter 0.103.5 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Add defconfig and Kconfig files for Google Chameleon V3 board\n\nSigned-off-by: Paweł Anikiel <pan@semihalf.com>\nReviewed-by: Simon Glass <sjg@chromium.org>\n---\n arch/arm/mach-socfpga/Kconfig | 7 +++++\n configs/socfpga_chameleonv3_defconfig | 29 ++++++++++++++++++\n include/configs/socfpga_chameleonv3.h | 44 +++++++++++++++++++++++++++\n 3 files changed, 80 insertions(+)\n create mode 100644 configs/socfpga_chameleonv3_defconfig\n create mode 100644 include/configs/socfpga_chameleonv3.h", "diff": "diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig\nindex 78a7549a41..fe851f575e 100644\n--- a/arch/arm/mach-socfpga/Kconfig\n+++ b/arch/arm/mach-socfpga/Kconfig\n@@ -143,6 +143,10 @@ config TARGET_SOCFPGA_ARRIA5_SOCDK\n \tbool \"Altera SOCFPGA SoCDK (Arria V)\"\n \tselect TARGET_SOCFPGA_ARRIA5\n \n+config TARGET_SOCFPGA_CHAMELEONV3\n+\tbool \"Google Chameleon v3 (Arria 10)\"\n+\tselect TARGET_SOCFPGA_ARRIA10\n+\n config TARGET_SOCFPGA_CYCLONE5_SOCDK\n \tbool \"Altera SOCFPGA SoCDK (Cyclone V)\"\n \tselect TARGET_SOCFPGA_CYCLONE5\n@@ -194,6 +198,7 @@ config SYS_BOARD\n \tdefault \"agilex-socdk\" if TARGET_SOCFPGA_AGILEX_SOCDK\n \tdefault \"arria5-socdk\" if TARGET_SOCFPGA_ARRIA5_SOCDK\n \tdefault \"arria10-socdk\" if TARGET_SOCFPGA_ARRIA10_SOCDK\n+\tdefault \"chameleonv3\" if TARGET_SOCFPGA_CHAMELEONV3\n \tdefault \"cyclone5-socdk\" if TARGET_SOCFPGA_CYCLONE5_SOCDK\n \tdefault \"dbm-soc1\" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1\n \tdefault \"de0-nano-soc\" if TARGET_SOCFPGA_TERASIC_DE0_NANO\n@@ -219,6 +224,7 @@ config SYS_VENDOR\n \tdefault \"aries\" if TARGET_SOCFPGA_ARIES_MCVEVK\n \tdefault \"devboards\" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1\n \tdefault \"ebv\" if TARGET_SOCFPGA_EBV_SOCRATES\n+\tdefault \"google\" if TARGET_SOCFPGA_CHAMELEONV3\n \tdefault \"keymile\" if TARGET_SOCFPGA_ARRIA5_SECU1\n \tdefault \"softing\" if TARGET_SOCFPGA_SOFTING_VINING_FPGA\n \tdefault \"terasic\" if TARGET_SOCFPGA_TERASIC_DE0_NANO\n@@ -234,6 +240,7 @@ config SYS_CONFIG_NAME\n \tdefault \"socfpga_arria5_secu1\" if TARGET_SOCFPGA_ARRIA5_SECU1\n \tdefault \"socfpga_arria5_socdk\" if TARGET_SOCFPGA_ARRIA5_SOCDK\n \tdefault \"socfpga_arria10_socdk\" if TARGET_SOCFPGA_ARRIA10_SOCDK\n+\tdefault \"socfpga_chameleonv3\" if TARGET_SOCFPGA_CHAMELEONV3\n \tdefault \"socfpga_cyclone5_socdk\" if TARGET_SOCFPGA_CYCLONE5_SOCDK\n \tdefault \"socfpga_dbm_soc1\" if TARGET_SOCFPGA_DEVBOARDS_DBM_SOC1\n \tdefault \"socfpga_de0_nano_soc\" if TARGET_SOCFPGA_TERASIC_DE0_NANO\ndiff --git a/configs/socfpga_chameleonv3_defconfig b/configs/socfpga_chameleonv3_defconfig\nnew file mode 100644\nindex 0000000000..7870d31b09\n--- /dev/null\n+++ b/configs/socfpga_chameleonv3_defconfig\n@@ -0,0 +1,29 @@\n+CONFIG_ARM=y\n+CONFIG_ARCH_SOCFPGA=y\n+CONFIG_TARGET_SOCFPGA_CHAMELEONV3=y\n+CONFIG_DEFAULT_DEVICE_TREE=\"socfpga_arria10_chameleonv3_480_2\"\n+CONFIG_DISTRO_DEFAULTS=y\n+# CONFIG_USE_SPL_FIT_GENERATOR is not set\n+CONFIG_FIT=y\n+CONFIG_SPL_FIT=y\n+CONFIG_FS_LOADER=y\n+CONFIG_SPL_FS_LOADER=y\n+CONFIG_SPL_FS_FAT=y\n+CONFIG_SPL_FPGA=y\n+CONFIG_SPL_TEXT_BASE=0xFFE00000\n+CONFIG_SPL_ENV_SUPPORT=y\n+CONFIG_SPL_DRIVERS_MISC=y\n+CONFIG_ENV_IS_IN_MMC=y\n+CONFIG_ENV_SIZE=0x10000\n+CONFIG_ENV_OFFSET=0x4400\n+CONFIG_DM_ETH=y\n+CONFIG_ETH_DESIGNWARE=y\n+CONFIG_TIMER=y\n+CONFIG_SPL_TIMER=y\n+CONFIG_DESIGNWARE_APB_TIMER=y\n+CONFIG_MMC_DW=y\n+CONFIG_DM_I2C=y\n+CONFIG_SYS_I2C_DW=y\n+CONFIG_MISC=y\n+CONFIG_MISC_INIT_R=y\n+CONFIG_ATSHA204A=y\ndiff --git a/include/configs/socfpga_chameleonv3.h b/include/configs/socfpga_chameleonv3.h\nnew file mode 100644\nindex 0000000000..891b762946\n--- /dev/null\n+++ b/include/configs/socfpga_chameleonv3.h\n@@ -0,0 +1,44 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright 2022 Google LLC\n+ */\n+#ifndef __SOCFGPA_CHAMELEONV3_H__\n+#define __SOCFGPA_CHAMELEONV3_H__\n+\n+#include <asm/arch/base_addr_a10.h>\n+\n+#define CONFIG_SYS_BOOTM_LEN\t(32 * 1024 * 1024)\n+\n+/*\n+ * U-Boot general configurations\n+ */\n+\n+/* Memory configurations */\n+#define PHYS_SDRAM_1_SIZE\t\t0x40000000\n+\n+/*\n+ * Serial / UART configurations\n+ */\n+#define CONFIG_SYS_NS16550_MEM32\n+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}\n+\n+#define CONFIG_EXTRA_ENV_SETTINGS \\\n+\t\"autoload=no\\0\" \\\n+\t\"bootargs=cma=256M console=ttyS1,115200 root=/dev/mmcblk0p3 rw rootwait\\0\" \\\n+\t\"distro_bootcmd=bridge enable; run bootcmd_mmc\\0\" \\\n+\t\"bootcmd_mmc=load mmc 0:1 ${loadaddr} kernel.itb; bootm\\0\" \\\n+\t\"bootcmd_net=dhcp; tftpboot ${loadaddr} kernel.itb; bootm\\0\"\n+\n+/*\n+ * L4 OSC1 Timer 0\n+ */\n+/* reload value when timer count to zero */\n+#define TIMER_LOAD_VAL\t\t\t0xFFFFFFFF\n+\n+/* SPL memory allocation configuration, this is for FAT implementation */\n+#define CONFIG_SYS_SPL_MALLOC_SIZE\t0x00015000\n+\n+/* The rest of the configuration is shared */\n+#include <configs/socfpga_common.h>\n+\n+#endif\t/* __SOCFGPA_CHAMELEONV3_H__ */\n", "prefixes": [ "v3", "05/11" ] }