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GET /api/patches/1644792/?format=api
{ "id": 1644792, "url": "http://patchwork.ozlabs.org/api/patches/1644792/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20220617104726.158688-3-pan@semihalf.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20220617104726.158688-3-pan@semihalf.com>", "list_archive_url": null, "date": "2022-06-17T10:47:17", "name": "[v3,02/11] arm: dts: Add Chameleonv3 handoff headers", "commit_ref": "882c00edeb994e0e27540f332a7fe7ceb20d0c34", "pull_url": null, "state": "accepted", "archived": false, "hash": "90df30a7cd8702325b0d0c3893218d8f45de09f2", "submitter": { "id": 82560, "url": "http://patchwork.ozlabs.org/api/people/82560/?format=api", "name": "Paweł Anikiel", "email": "pan@semihalf.com" }, "delegate": { "id": 88515, "url": "http://patchwork.ozlabs.org/api/users/88515/?format=api", "username": "simongoldschmidt", "first_name": "Simon", "last_name": "Goldschmidt", "email": "simon.k.r.goldschmidt@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20220617104726.158688-3-pan@semihalf.com/mbox/", "series": [ { "id": 305278, "url": "http://patchwork.ozlabs.org/api/series/305278/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=305278", "date": "2022-06-17T10:47:15", "name": "Add Chameleon v3 support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/305278/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1644792/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1644792/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "bilbo.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=semihalf.com header.i=@semihalf.com header.a=rsa-sha256\n header.s=google header.b=SRXCZ2LE;\n\tdkim-atps=neutral", "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=semihalf.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=semihalf.com header.i=@semihalf.com\n header.b=\"SRXCZ2LE\";\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=none (p=none dis=none) header.from=semihalf.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=pan@semihalf.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (2048 bits))\n\t(No client certificate requested)\n\tby bilbo.ozlabs.org (Postfix) with ESMTPS id 4LPbNv1kWyz9sGH\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 17 Jun 2022 20:48:15 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 21041843CC;\n\tFri, 17 Jun 2022 12:47:54 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id 790CC8440C; Fri, 17 Jun 2022 12:47:50 +0200 (CEST)", "from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com\n [IPv6:2a00:1450:4864:20::12a])\n (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 62B888432F\n for <u-boot@lists.denx.de>; Fri, 17 Jun 2022 12:47:46 +0200 (CEST)", "by mail-lf1-x12a.google.com with SMTP id h36so6311199lfv.9\n for <u-boot@lists.denx.de>; Fri, 17 Jun 2022 03:47:46 -0700 (PDT)", "from panikiel.roam.corp.google.com\n (staticline-31-182-204-250.toya.net.pl. [31.182.204.250])\n by smtp.gmail.com with ESMTPSA id\n a17-20020ac25e71000000b00479342519e5sm592379lfr.210.2022.06.17.03.47.44\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Fri, 17 Jun 2022 03:47:45 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS,\n T_SCC_BODY_TEXT_LINE,UPPERCASE_50_75 autolearn=no autolearn_force=no\n version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf.com;\n s=google;\n h=from:to:cc:subject:date:message-id:in-reply-to:references\n :mime-version:content-transfer-encoding;\n bh=j2vQlgq7qsBUnMhzuxlH/n3i4iIXXZWM0Zt0aan5SNc=;\n b=SRXCZ2LEDjgcVmU7ClbrLb2wa4I4K4LMSnW722MgwTm1vb2phhGdHG2vyE9r/7aiKb\n uaO17jRl18pxj32pxlfTJ1eTkhETkYUIaBvKVjcyrujYx4Oub8T5oFeFxBfTFrPNg2Gr\n 7t3deR3Ew7kCpXbF2YbOeWoV1pv6KswqP5kIGU6r6S5iFmeoca1uU8oe07U8eoowGSkS\n 25MsTvMS0tqcvvNQRopGl4KBr/qX6tWPK8qG22xb+jqk4geILTkRkO1XoHxI/lYBEzao\n mWuuXajdfC/PiIGJ3Ut7JZitef/ofH6IupvnjKXsPgO8OtRPIZ7ZVCafhIlbcIylH74o\n Ckgw==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20210112;\n h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n :references:mime-version:content-transfer-encoding;\n bh=j2vQlgq7qsBUnMhzuxlH/n3i4iIXXZWM0Zt0aan5SNc=;\n b=HHBdduu+qltyrc7zbp0+EhCF+4M1QcSnLwZg/TCzxQijsrBdWobioMqRxbkBPQE5/Q\n /S04MS3H5djlY38mPxaCemYGG8gw7/4guH5TxgnQIDAYEb7HEmk3FQRZ/LO/o+svsa+r\n 6uCymOSsB1m7M0cOwpE2nandyf8jENuuoC72rPtKLEWxEBp8dNLEF/getUNicKtUeU/1\n FnhFS+V7nRf9Z6hYEJp76FKJuR3GWKusvNkzaHdGwhR5zBO469BCi2zIpJFFQ3hFY8AQ\n ZMGzUag/1zUaLryg6xZEc+WWWB4AZCRo2RwNFrgvSxDpLk0x1Mkfoz+bjIXSEg6YF/PH\n /Tyw==", "X-Gm-Message-State": "AJIora+784roilHRJbe7eXR5CnCHrpEKJaoR3XaaGahG5RUo1rwg0/of\n XtCE6J01vKWtCNXE6OZn4OfI0A==", "X-Google-Smtp-Source": "\n AGRyM1tdkzd+xelWrQiIiXdndlySZ7LZfjQkNGF4MJL2pCktG5HrkFMiBdKGDJggqRLgBFjVM5eEvg==", "X-Received": "by 2002:a05:6512:130a:b0:47d:b429:79fb with SMTP id\n x10-20020a056512130a00b0047db42979fbmr5133627lfu.559.1655462865753;\n Fri, 17 Jun 2022 03:47:45 -0700 (PDT)", "From": "=?utf-8?q?Pawe=C5=82_Anikiel?= <pan@semihalf.com>", "To": "marex@denx.de, simon.k.r.goldschmidt@gmail.com, tien.fong.chee@intel.com,\n michal.simek@xilinx.com", "Cc": "u-boot@lists.denx.de, sjg@chromium.org, festevam@denx.de,\n jagan@amarulasolutions.com, andre.przywara@arm.com, narmstrong@baylibre.com,\n pbrobinson@gmail.com, tharvey@gateworks.com, paul.liu@linaro.org,\n christianshewitt@gmail.com, adrian.fiergolski@fastree3d.com,\n marek.behun@nic.cz, wd@denx.de, elly.siew.chin.lim@intel.com,\n upstream@semihalf.com, amstan@chromium.org,\n =?utf-8?q?Pawe=C5=82_Anikiel?= <pan@semihalf.com>", "Subject": "[PATCH v3 02/11] arm: dts: Add Chameleonv3 handoff headers", "Date": "Fri, 17 Jun 2022 12:47:17 +0200", "Message-Id": "<20220617104726.158688-3-pan@semihalf.com>", "X-Mailer": "git-send-email 2.36.1.476.g0c4daa206d-goog", "In-Reply-To": "<20220617104726.158688-1-pan@semihalf.com>", "References": "<20220617104726.158688-1-pan@semihalf.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.5 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Add handoff headers for the Google Chameleonv3 variants: 480-2 and\n270-3. Both files were generated using qts-filter-a10.sh.\n\nSigned-off-by: Paweł Anikiel <pan@semihalf.com>\nReviewed-by: Simon Glass <sjg@chromium.org>\n---\n ...ocfpga_arria10_chameleonv3_270_3_handoff.h | 305 ++++++++++++++++++\n ...ocfpga_arria10_chameleonv3_480_2_handoff.h | 305 ++++++++++++++++++\n 2 files changed, 610 insertions(+)\n create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h\n create mode 100644 arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h", "diff": "diff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h\nnew file mode 100644\nindex 0000000000..9d8f4a0dd3\n--- /dev/null\n+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_270_3_handoff.h\n@@ -0,0 +1,305 @@\n+// SPDX-License-Identifier: BSD-3-Clause\n+/*\n+ * Intel Arria 10 SoCFPGA configuration\n+ */\n+\n+#ifndef __SOCFPGA_ARRIA10_CONFIG_H__\n+#define __SOCFPGA_ARRIA10_CONFIG_H__\n+\n+/* Clocks */\n+#define CB_INTOSC_LS_CLK_HZ 60000000\n+#define EMAC0_CLK_HZ 250000000\n+#define EMAC1_CLK_HZ 250000000\n+#define EMAC2_CLK_HZ 250000000\n+#define EOSC1_CLK_HZ 33330000\n+#define F2H_FREE_CLK_HZ 200000000\n+#define H2F_USER0_CLK_HZ 200000000\n+#define H2F_USER1_CLK_HZ 100000000\n+#define L3_MAIN_FREE_CLK_HZ 200000000\n+#define SDMMC_CLK_HZ 200000000\n+#define TPIU_CLK_HZ 100000000\n+#define MAINPLLGRP_CNTR15CLK_CNT 900\n+#define MAINPLLGRP_CNTR2CLK_CNT 900\n+#define MAINPLLGRP_CNTR3CLK_CNT 900\n+#define MAINPLLGRP_CNTR4CLK_CNT 900\n+#define MAINPLLGRP_CNTR5CLK_CNT 900\n+#define MAINPLLGRP_CNTR6CLK_CNT 7\n+#define MAINPLLGRP_CNTR7CLK_CNT 7\n+#define MAINPLLGRP_CNTR7CLK_SRC 0\n+#define MAINPLLGRP_CNTR8CLK_CNT 15\n+#define MAINPLLGRP_CNTR9CLK_CNT 900\n+#define MAINPLLGRP_CNTR9CLK_SRC 0\n+#define MAINPLLGRP_MPUCLK_CNT 0\n+#define MAINPLLGRP_MPUCLK_SRC 0\n+#define MAINPLLGRP_NOCCLK_CNT 0\n+#define MAINPLLGRP_NOCCLK_SRC 0\n+#define MAINPLLGRP_NOCDIV_CSATCLK 0\n+#define MAINPLLGRP_NOCDIV_CSPDBGCLK 1\n+#define MAINPLLGRP_NOCDIV_CSTRACECLK 0\n+#define MAINPLLGRP_NOCDIV_L4MAINCLK 0\n+#define MAINPLLGRP_NOCDIV_L4MPCLK 1\n+#define MAINPLLGRP_NOCDIV_L4SPCLK 2\n+#define MAINPLLGRP_VCO0_PSRC 0\n+#define MAINPLLGRP_VCO1_DENOM 32\n+#define MAINPLLGRP_VCO1_NUMER 1584\n+#define PERPLLGRP_CNTR2CLK_CNT 5\n+#define PERPLLGRP_CNTR2CLK_SRC 1\n+#define PERPLLGRP_CNTR3CLK_CNT 900\n+#define PERPLLGRP_CNTR3CLK_SRC 1\n+#define PERPLLGRP_CNTR4CLK_CNT 14\n+#define PERPLLGRP_CNTR4CLK_SRC 1\n+#define PERPLLGRP_CNTR5CLK_CNT 374\n+#define PERPLLGRP_CNTR5CLK_SRC 1\n+#define PERPLLGRP_CNTR6CLK_CNT 900\n+#define PERPLLGRP_CNTR6CLK_SRC 0\n+#define PERPLLGRP_CNTR7CLK_CNT 900\n+#define PERPLLGRP_CNTR8CLK_CNT 900\n+#define PERPLLGRP_CNTR8CLK_SRC 0\n+#define PERPLLGRP_CNTR9CLK_CNT 900\n+#define PERPLLGRP_EMACCTL_EMAC0SEL 0\n+#define PERPLLGRP_EMACCTL_EMAC1SEL 0\n+#define PERPLLGRP_EMACCTL_EMAC2SEL 0\n+#define PERPLLGRP_GPIODIV_GPIODBCLK 32000\n+#define PERPLLGRP_VCO0_PSRC 0\n+#define PERPLLGRP_VCO1_DENOM 32\n+#define PERPLLGRP_VCO1_NUMER 1485\n+#define CLKMGR_TESTIOCTRL_DEBUGCLKSEL 16\n+#define CLKMGR_TESTIOCTRL_MAINCLKSEL 8\n+#define CLKMGR_TESTIOCTRL_PERICLKSEL 8\n+#define ALTERAGRP_MPUCLK_MAINCNT 1\n+#define ALTERAGRP_MPUCLK_PERICNT 900\n+#define ALTERAGRP_NOCCLK_MAINCNT 7\n+#define ALTERAGRP_NOCCLK_PERICNT 900\n+#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \\\n+\t(ALTERAGRP_MPUCLK_MAINCNT))\n+#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \\\n+\t(ALTERAGRP_NOCCLK_MAINCNT))\n+\n+/* Pin Mux Configuration */\n+#define CONFIG_IO_10_INPUT_BUF_EN 1\n+#define CONFIG_IO_10_PD_DRV_STRG 10\n+#define CONFIG_IO_10_PD_SLW_RT 1\n+#define CONFIG_IO_10_PU_DRV_STRG 8\n+#define CONFIG_IO_10_PU_SLW_RT 1\n+#define CONFIG_IO_10_RTRIM 1\n+#define CONFIG_IO_10_WK_PU_EN 0\n+#define CONFIG_IO_11_INPUT_BUF_EN 1\n+#define CONFIG_IO_11_PD_DRV_STRG 10\n+#define CONFIG_IO_11_PD_SLW_RT 1\n+#define CONFIG_IO_11_PU_DRV_STRG 8\n+#define CONFIG_IO_11_PU_SLW_RT 1\n+#define CONFIG_IO_11_RTRIM 1\n+#define CONFIG_IO_11_WK_PU_EN 0\n+#define CONFIG_IO_12_INPUT_BUF_EN 0\n+#define CONFIG_IO_12_PD_DRV_STRG 0\n+#define CONFIG_IO_12_PD_SLW_RT 0\n+#define CONFIG_IO_12_PU_DRV_STRG 0\n+#define CONFIG_IO_12_PU_SLW_RT 0\n+#define CONFIG_IO_12_RTRIM 1\n+#define CONFIG_IO_12_WK_PU_EN 1\n+#define CONFIG_IO_13_INPUT_BUF_EN 0\n+#define CONFIG_IO_13_PD_DRV_STRG 0\n+#define CONFIG_IO_13_PD_SLW_RT 0\n+#define CONFIG_IO_13_PU_DRV_STRG 0\n+#define CONFIG_IO_13_PU_SLW_RT 0\n+#define CONFIG_IO_13_RTRIM 1\n+#define CONFIG_IO_13_WK_PU_EN 1\n+#define CONFIG_IO_14_INPUT_BUF_EN 0\n+#define CONFIG_IO_14_PD_DRV_STRG 0\n+#define CONFIG_IO_14_PD_SLW_RT 0\n+#define CONFIG_IO_14_PU_DRV_STRG 0\n+#define CONFIG_IO_14_PU_SLW_RT 0\n+#define CONFIG_IO_14_RTRIM 1\n+#define CONFIG_IO_14_WK_PU_EN 1\n+#define CONFIG_IO_15_INPUT_BUF_EN 0\n+#define CONFIG_IO_15_PD_DRV_STRG 0\n+#define CONFIG_IO_15_PD_SLW_RT 0\n+#define CONFIG_IO_15_PU_DRV_STRG 0\n+#define CONFIG_IO_15_PU_SLW_RT 0\n+#define CONFIG_IO_15_RTRIM 1\n+#define CONFIG_IO_15_WK_PU_EN 1\n+#define CONFIG_IO_16_INPUT_BUF_EN 0\n+#define CONFIG_IO_16_PD_DRV_STRG 10\n+#define CONFIG_IO_16_PD_SLW_RT 1\n+#define CONFIG_IO_16_PU_DRV_STRG 8\n+#define CONFIG_IO_16_PU_SLW_RT 1\n+#define CONFIG_IO_16_RTRIM 1\n+#define CONFIG_IO_16_WK_PU_EN 0\n+#define CONFIG_IO_17_INPUT_BUF_EN 1\n+#define CONFIG_IO_17_PD_DRV_STRG 10\n+#define CONFIG_IO_17_PD_SLW_RT 1\n+#define CONFIG_IO_17_PU_DRV_STRG 8\n+#define CONFIG_IO_17_PU_SLW_RT 1\n+#define CONFIG_IO_17_RTRIM 1\n+#define CONFIG_IO_17_WK_PU_EN 0\n+#define CONFIG_IO_1_INPUT_BUF_EN 1\n+#define CONFIG_IO_1_PD_DRV_STRG 10\n+#define CONFIG_IO_1_PD_SLW_RT 0\n+#define CONFIG_IO_1_PU_DRV_STRG 8\n+#define CONFIG_IO_1_PU_SLW_RT 0\n+#define CONFIG_IO_1_RTRIM 1\n+#define CONFIG_IO_1_WK_PU_EN 1\n+#define CONFIG_IO_2_INPUT_BUF_EN 1\n+#define CONFIG_IO_2_PD_DRV_STRG 10\n+#define CONFIG_IO_2_PD_SLW_RT 0\n+#define CONFIG_IO_2_PU_DRV_STRG 8\n+#define CONFIG_IO_2_PU_SLW_RT 0\n+#define CONFIG_IO_2_RTRIM 1\n+#define CONFIG_IO_2_WK_PU_EN 1\n+#define CONFIG_IO_3_INPUT_BUF_EN 1\n+#define CONFIG_IO_3_PD_DRV_STRG 10\n+#define CONFIG_IO_3_PD_SLW_RT 0\n+#define CONFIG_IO_3_PU_DRV_STRG 8\n+#define CONFIG_IO_3_PU_SLW_RT 0\n+#define CONFIG_IO_3_RTRIM 1\n+#define CONFIG_IO_3_WK_PU_EN 1\n+#define CONFIG_IO_4_INPUT_BUF_EN 1\n+#define CONFIG_IO_4_PD_DRV_STRG 10\n+#define CONFIG_IO_4_PD_SLW_RT 1\n+#define CONFIG_IO_4_PU_DRV_STRG 8\n+#define CONFIG_IO_4_PU_SLW_RT 1\n+#define CONFIG_IO_4_RTRIM 1\n+#define CONFIG_IO_4_WK_PU_EN 0\n+#define CONFIG_IO_5_INPUT_BUF_EN 1\n+#define CONFIG_IO_5_PD_DRV_STRG 10\n+#define CONFIG_IO_5_PD_SLW_RT 1\n+#define CONFIG_IO_5_PU_DRV_STRG 8\n+#define CONFIG_IO_5_PU_SLW_RT 1\n+#define CONFIG_IO_5_RTRIM 1\n+#define CONFIG_IO_5_WK_PU_EN 0\n+#define CONFIG_IO_6_INPUT_BUF_EN 0\n+#define CONFIG_IO_6_PD_DRV_STRG 10\n+#define CONFIG_IO_6_PD_SLW_RT 1\n+#define CONFIG_IO_6_PU_DRV_STRG 8\n+#define CONFIG_IO_6_PU_SLW_RT 1\n+#define CONFIG_IO_6_RTRIM 1\n+#define CONFIG_IO_6_WK_PU_EN 0\n+#define CONFIG_IO_7_INPUT_BUF_EN 1\n+#define CONFIG_IO_7_PD_DRV_STRG 10\n+#define CONFIG_IO_7_PD_SLW_RT 1\n+#define CONFIG_IO_7_PU_DRV_STRG 8\n+#define CONFIG_IO_7_PU_SLW_RT 1\n+#define CONFIG_IO_7_RTRIM 1\n+#define CONFIG_IO_7_WK_PU_EN 0\n+#define CONFIG_IO_8_INPUT_BUF_EN 1\n+#define CONFIG_IO_8_PD_DRV_STRG 10\n+#define CONFIG_IO_8_PD_SLW_RT 1\n+#define CONFIG_IO_8_PU_DRV_STRG 8\n+#define CONFIG_IO_8_PU_SLW_RT 1\n+#define CONFIG_IO_8_RTRIM 1\n+#define CONFIG_IO_8_WK_PU_EN 0\n+#define CONFIG_IO_9_INPUT_BUF_EN 1\n+#define CONFIG_IO_9_PD_DRV_STRG 10\n+#define CONFIG_IO_9_PD_SLW_RT 1\n+#define CONFIG_IO_9_PU_DRV_STRG 8\n+#define CONFIG_IO_9_PU_SLW_RT 1\n+#define CONFIG_IO_9_RTRIM 1\n+#define CONFIG_IO_9_WK_PU_EN 0\n+#define CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO 1\n+#define CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO 1\n+#define PINMUX_DEDICATED_IO_10_SEL 15\n+#define PINMUX_DEDICATED_IO_11_SEL 15\n+#define PINMUX_DEDICATED_IO_12_SEL 1\n+#define PINMUX_DEDICATED_IO_13_SEL 1\n+#define PINMUX_DEDICATED_IO_14_SEL 10\n+#define PINMUX_DEDICATED_IO_15_SEL 10\n+#define PINMUX_DEDICATED_IO_16_SEL 13\n+#define PINMUX_DEDICATED_IO_17_SEL 13\n+#define PINMUX_DEDICATED_IO_4_SEL 8\n+#define PINMUX_DEDICATED_IO_5_SEL 8\n+#define PINMUX_DEDICATED_IO_6_SEL 8\n+#define PINMUX_DEDICATED_IO_7_SEL 8\n+#define PINMUX_DEDICATED_IO_8_SEL 8\n+#define PINMUX_DEDICATED_IO_9_SEL 8\n+#define PINMUX_I2C0_USEFPGA_SEL 1\n+#define PINMUX_I2C1_USEFPGA_SEL 0\n+#define PINMUX_I2CEMAC0_USEFPGA_SEL 0\n+#define PINMUX_I2CEMAC1_USEFPGA_SEL 0\n+#define PINMUX_I2CEMAC2_USEFPGA_SEL 0\n+#define PINMUX_NAND_USEFPGA_SEL 0\n+#define PINMUX_PLL_CLOCK_OUT_USEFPGA_SEL 0\n+#define PINMUX_QSPI_USEFPGA_SEL 0\n+#define PINMUX_RGMII0_USEFPGA_SEL 0\n+#define PINMUX_RGMII1_USEFPGA_SEL 0\n+#define PINMUX_RGMII2_USEFPGA_SEL 0\n+#define PINMUX_SDMMC_USEFPGA_SEL 0\n+#define PINMUX_SHARED_IO_Q1_10_SEL 8\n+#define PINMUX_SHARED_IO_Q1_11_SEL 8\n+#define PINMUX_SHARED_IO_Q1_12_SEL 8\n+#define PINMUX_SHARED_IO_Q1_1_SEL 8\n+#define PINMUX_SHARED_IO_Q1_2_SEL 8\n+#define PINMUX_SHARED_IO_Q1_3_SEL 8\n+#define PINMUX_SHARED_IO_Q1_4_SEL 8\n+#define PINMUX_SHARED_IO_Q1_5_SEL 8\n+#define PINMUX_SHARED_IO_Q1_6_SEL 8\n+#define PINMUX_SHARED_IO_Q1_7_SEL 8\n+#define PINMUX_SHARED_IO_Q1_8_SEL 8\n+#define PINMUX_SHARED_IO_Q1_9_SEL 8\n+#define PINMUX_SHARED_IO_Q2_10_SEL 4\n+#define PINMUX_SHARED_IO_Q2_11_SEL 4\n+#define PINMUX_SHARED_IO_Q2_12_SEL 4\n+#define PINMUX_SHARED_IO_Q2_1_SEL 4\n+#define PINMUX_SHARED_IO_Q2_2_SEL 4\n+#define PINMUX_SHARED_IO_Q2_3_SEL 4\n+#define PINMUX_SHARED_IO_Q2_4_SEL 4\n+#define PINMUX_SHARED_IO_Q2_5_SEL 4\n+#define PINMUX_SHARED_IO_Q2_6_SEL 4\n+#define PINMUX_SHARED_IO_Q2_7_SEL 4\n+#define PINMUX_SHARED_IO_Q2_8_SEL 4\n+#define PINMUX_SHARED_IO_Q2_9_SEL 4\n+#define PINMUX_SHARED_IO_Q3_10_SEL 15\n+#define PINMUX_SHARED_IO_Q3_11_SEL 1\n+#define PINMUX_SHARED_IO_Q3_12_SEL 1\n+#define PINMUX_SHARED_IO_Q3_1_SEL 15\n+#define PINMUX_SHARED_IO_Q3_2_SEL 15\n+#define PINMUX_SHARED_IO_Q3_3_SEL 15\n+#define PINMUX_SHARED_IO_Q3_4_SEL 15\n+#define PINMUX_SHARED_IO_Q3_5_SEL 15\n+#define PINMUX_SHARED_IO_Q3_6_SEL 15\n+#define PINMUX_SHARED_IO_Q3_7_SEL 0\n+#define PINMUX_SHARED_IO_Q3_8_SEL 0\n+#define PINMUX_SHARED_IO_Q3_9_SEL 15\n+#define PINMUX_SHARED_IO_Q4_10_SEL 10\n+#define PINMUX_SHARED_IO_Q4_11_SEL 10\n+#define PINMUX_SHARED_IO_Q4_12_SEL 10\n+#define PINMUX_SHARED_IO_Q4_1_SEL 10\n+#define PINMUX_SHARED_IO_Q4_2_SEL 10\n+#define PINMUX_SHARED_IO_Q4_3_SEL 10\n+#define PINMUX_SHARED_IO_Q4_4_SEL 10\n+#define PINMUX_SHARED_IO_Q4_5_SEL 10\n+#define PINMUX_SHARED_IO_Q4_6_SEL 10\n+#define PINMUX_SHARED_IO_Q4_7_SEL 10\n+#define PINMUX_SHARED_IO_Q4_8_SEL 10\n+#define PINMUX_SHARED_IO_Q4_9_SEL 10\n+#define PINMUX_SPIM0_USEFPGA_SEL 0\n+#define PINMUX_SPIM1_USEFPGA_SEL 0\n+#define PINMUX_SPIS0_USEFPGA_SEL 0\n+#define PINMUX_SPIS1_USEFPGA_SEL 0\n+#define PINMUX_UART0_USEFPGA_SEL 1\n+#define PINMUX_UART1_USEFPGA_SEL 0\n+#define PINMUX_USB0_USEFPGA_SEL 0\n+#define PINMUX_USB1_USEFPGA_SEL 0\n+\n+/* Bridge Configuration */\n+#define F2H_AXI_SLAVE 1\n+#define F2SDRAM0_AXI_SLAVE 1\n+#define F2SDRAM1_AXI_SLAVE 1\n+#define F2SDRAM2_AXI_SLAVE 1\n+#define H2F_AXI_MASTER 1\n+#define LWH2F_AXI_MASTER 1\n+\n+/* Voltage Select for Config IO */\n+#define CONFIG_IO_BANK_VSEL \\\n+\t(((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \\\n+\t(CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))\n+\n+/* Macro for Config IO bit mapping */\n+#define CONFIG_IO_MACRO(NAME) (((NAME ## _RTRIM & 0xff) << 19) | \\\n+\t((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \\\n+\t((NAME ## _WK_PU_EN & 0x1) << 16) | \\\n+\t((NAME ## _PU_SLW_RT & 0x1) << 13) | \\\n+\t((NAME ## _PU_DRV_STRG & 0xf) << 8) | \\\n+\t((NAME ## _PD_SLW_RT & 0x1) << 5) | \\\n+\t(NAME ## _PD_DRV_STRG & 0x1f))\n+\n+#endif /* __SOCFPGA_ARRIA10_CONFIG_H__ */\ndiff --git a/arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h\nnew file mode 100644\nindex 0000000000..caaff604eb\n--- /dev/null\n+++ b/arch/arm/dts/socfpga_arria10_chameleonv3_480_2_handoff.h\n@@ -0,0 +1,305 @@\n+// SPDX-License-Identifier: BSD-3-Clause\n+/*\n+ * Intel Arria 10 SoCFPGA configuration\n+ */\n+\n+#ifndef __SOCFPGA_ARRIA10_CONFIG_H__\n+#define __SOCFPGA_ARRIA10_CONFIG_H__\n+\n+/* Clocks */\n+#define CB_INTOSC_LS_CLK_HZ 60000000\n+#define EMAC0_CLK_HZ 250000000\n+#define EMAC1_CLK_HZ 250000000\n+#define EMAC2_CLK_HZ 250000000\n+#define EOSC1_CLK_HZ 33330000\n+#define F2H_FREE_CLK_HZ 200000000\n+#define H2F_USER0_CLK_HZ 200000000\n+#define H2F_USER1_CLK_HZ 100000000\n+#define L3_MAIN_FREE_CLK_HZ 200000000\n+#define SDMMC_CLK_HZ 200000000\n+#define TPIU_CLK_HZ 100000000\n+#define MAINPLLGRP_CNTR15CLK_CNT 900\n+#define MAINPLLGRP_CNTR2CLK_CNT 900\n+#define MAINPLLGRP_CNTR3CLK_CNT 900\n+#define MAINPLLGRP_CNTR4CLK_CNT 900\n+#define MAINPLLGRP_CNTR5CLK_CNT 900\n+#define MAINPLLGRP_CNTR6CLK_CNT 9\n+#define MAINPLLGRP_CNTR7CLK_CNT 9\n+#define MAINPLLGRP_CNTR7CLK_SRC 0\n+#define MAINPLLGRP_CNTR8CLK_CNT 19\n+#define MAINPLLGRP_CNTR9CLK_CNT 900\n+#define MAINPLLGRP_CNTR9CLK_SRC 0\n+#define MAINPLLGRP_MPUCLK_CNT 0\n+#define MAINPLLGRP_MPUCLK_SRC 0\n+#define MAINPLLGRP_NOCCLK_CNT 0\n+#define MAINPLLGRP_NOCCLK_SRC 0\n+#define MAINPLLGRP_NOCDIV_CSATCLK 0\n+#define MAINPLLGRP_NOCDIV_CSPDBGCLK 1\n+#define MAINPLLGRP_NOCDIV_CSTRACECLK 0\n+#define MAINPLLGRP_NOCDIV_L4MAINCLK 0\n+#define MAINPLLGRP_NOCDIV_L4MPCLK 1\n+#define MAINPLLGRP_NOCDIV_L4SPCLK 2\n+#define MAINPLLGRP_VCO0_PSRC 0\n+#define MAINPLLGRP_VCO1_DENOM 32\n+#define MAINPLLGRP_VCO1_NUMER 1980\n+#define PERPLLGRP_CNTR2CLK_CNT 7\n+#define PERPLLGRP_CNTR2CLK_SRC 1\n+#define PERPLLGRP_CNTR3CLK_CNT 900\n+#define PERPLLGRP_CNTR3CLK_SRC 1\n+#define PERPLLGRP_CNTR4CLK_CNT 19\n+#define PERPLLGRP_CNTR4CLK_SRC 1\n+#define PERPLLGRP_CNTR5CLK_CNT 499\n+#define PERPLLGRP_CNTR5CLK_SRC 1\n+#define PERPLLGRP_CNTR6CLK_CNT 900\n+#define PERPLLGRP_CNTR6CLK_SRC 0\n+#define PERPLLGRP_CNTR7CLK_CNT 900\n+#define PERPLLGRP_CNTR8CLK_CNT 900\n+#define PERPLLGRP_CNTR8CLK_SRC 0\n+#define PERPLLGRP_CNTR9CLK_CNT 900\n+#define PERPLLGRP_EMACCTL_EMAC0SEL 0\n+#define PERPLLGRP_EMACCTL_EMAC1SEL 0\n+#define PERPLLGRP_EMACCTL_EMAC2SEL 0\n+#define PERPLLGRP_GPIODIV_GPIODBCLK 32000\n+#define PERPLLGRP_VCO0_PSRC 0\n+#define PERPLLGRP_VCO1_DENOM 32\n+#define PERPLLGRP_VCO1_NUMER 1980\n+#define CLKMGR_TESTIOCTRL_DEBUGCLKSEL 16\n+#define CLKMGR_TESTIOCTRL_MAINCLKSEL 8\n+#define CLKMGR_TESTIOCTRL_PERICLKSEL 8\n+#define ALTERAGRP_MPUCLK_MAINCNT 1\n+#define ALTERAGRP_MPUCLK_PERICNT 900\n+#define ALTERAGRP_NOCCLK_MAINCNT 9\n+#define ALTERAGRP_NOCCLK_PERICNT 900\n+#define ALTERAGRP_MPUCLK ((ALTERAGRP_MPUCLK_PERICNT << 16) | \\\n+\t(ALTERAGRP_MPUCLK_MAINCNT))\n+#define ALTERAGRP_NOCCLK ((ALTERAGRP_NOCCLK_PERICNT << 16) | \\\n+\t(ALTERAGRP_NOCCLK_MAINCNT))\n+\n+/* Pin Mux Configuration */\n+#define CONFIG_IO_10_INPUT_BUF_EN 1\n+#define CONFIG_IO_10_PD_DRV_STRG 10\n+#define CONFIG_IO_10_PD_SLW_RT 1\n+#define CONFIG_IO_10_PU_DRV_STRG 8\n+#define CONFIG_IO_10_PU_SLW_RT 1\n+#define CONFIG_IO_10_RTRIM 1\n+#define CONFIG_IO_10_WK_PU_EN 0\n+#define CONFIG_IO_11_INPUT_BUF_EN 1\n+#define CONFIG_IO_11_PD_DRV_STRG 10\n+#define CONFIG_IO_11_PD_SLW_RT 1\n+#define CONFIG_IO_11_PU_DRV_STRG 8\n+#define CONFIG_IO_11_PU_SLW_RT 1\n+#define CONFIG_IO_11_RTRIM 1\n+#define CONFIG_IO_11_WK_PU_EN 0\n+#define CONFIG_IO_12_INPUT_BUF_EN 0\n+#define CONFIG_IO_12_PD_DRV_STRG 0\n+#define CONFIG_IO_12_PD_SLW_RT 0\n+#define CONFIG_IO_12_PU_DRV_STRG 0\n+#define CONFIG_IO_12_PU_SLW_RT 0\n+#define CONFIG_IO_12_RTRIM 1\n+#define CONFIG_IO_12_WK_PU_EN 1\n+#define CONFIG_IO_13_INPUT_BUF_EN 0\n+#define CONFIG_IO_13_PD_DRV_STRG 0\n+#define CONFIG_IO_13_PD_SLW_RT 0\n+#define CONFIG_IO_13_PU_DRV_STRG 0\n+#define CONFIG_IO_13_PU_SLW_RT 0\n+#define CONFIG_IO_13_RTRIM 1\n+#define CONFIG_IO_13_WK_PU_EN 1\n+#define CONFIG_IO_14_INPUT_BUF_EN 0\n+#define CONFIG_IO_14_PD_DRV_STRG 0\n+#define CONFIG_IO_14_PD_SLW_RT 0\n+#define CONFIG_IO_14_PU_DRV_STRG 0\n+#define CONFIG_IO_14_PU_SLW_RT 0\n+#define CONFIG_IO_14_RTRIM 1\n+#define CONFIG_IO_14_WK_PU_EN 1\n+#define CONFIG_IO_15_INPUT_BUF_EN 0\n+#define CONFIG_IO_15_PD_DRV_STRG 0\n+#define CONFIG_IO_15_PD_SLW_RT 0\n+#define CONFIG_IO_15_PU_DRV_STRG 0\n+#define CONFIG_IO_15_PU_SLW_RT 0\n+#define CONFIG_IO_15_RTRIM 1\n+#define CONFIG_IO_15_WK_PU_EN 1\n+#define CONFIG_IO_16_INPUT_BUF_EN 0\n+#define CONFIG_IO_16_PD_DRV_STRG 10\n+#define CONFIG_IO_16_PD_SLW_RT 1\n+#define CONFIG_IO_16_PU_DRV_STRG 8\n+#define CONFIG_IO_16_PU_SLW_RT 1\n+#define CONFIG_IO_16_RTRIM 1\n+#define CONFIG_IO_16_WK_PU_EN 0\n+#define CONFIG_IO_17_INPUT_BUF_EN 1\n+#define CONFIG_IO_17_PD_DRV_STRG 10\n+#define CONFIG_IO_17_PD_SLW_RT 1\n+#define CONFIG_IO_17_PU_DRV_STRG 8\n+#define CONFIG_IO_17_PU_SLW_RT 1\n+#define CONFIG_IO_17_RTRIM 1\n+#define CONFIG_IO_17_WK_PU_EN 0\n+#define CONFIG_IO_1_INPUT_BUF_EN 1\n+#define CONFIG_IO_1_PD_DRV_STRG 10\n+#define CONFIG_IO_1_PD_SLW_RT 0\n+#define CONFIG_IO_1_PU_DRV_STRG 8\n+#define CONFIG_IO_1_PU_SLW_RT 0\n+#define CONFIG_IO_1_RTRIM 1\n+#define CONFIG_IO_1_WK_PU_EN 1\n+#define CONFIG_IO_2_INPUT_BUF_EN 1\n+#define CONFIG_IO_2_PD_DRV_STRG 10\n+#define CONFIG_IO_2_PD_SLW_RT 0\n+#define CONFIG_IO_2_PU_DRV_STRG 8\n+#define CONFIG_IO_2_PU_SLW_RT 0\n+#define CONFIG_IO_2_RTRIM 1\n+#define CONFIG_IO_2_WK_PU_EN 1\n+#define CONFIG_IO_3_INPUT_BUF_EN 1\n+#define CONFIG_IO_3_PD_DRV_STRG 10\n+#define CONFIG_IO_3_PD_SLW_RT 0\n+#define CONFIG_IO_3_PU_DRV_STRG 8\n+#define CONFIG_IO_3_PU_SLW_RT 0\n+#define CONFIG_IO_3_RTRIM 1\n+#define CONFIG_IO_3_WK_PU_EN 1\n+#define CONFIG_IO_4_INPUT_BUF_EN 1\n+#define CONFIG_IO_4_PD_DRV_STRG 10\n+#define CONFIG_IO_4_PD_SLW_RT 1\n+#define CONFIG_IO_4_PU_DRV_STRG 8\n+#define CONFIG_IO_4_PU_SLW_RT 1\n+#define CONFIG_IO_4_RTRIM 1\n+#define CONFIG_IO_4_WK_PU_EN 0\n+#define CONFIG_IO_5_INPUT_BUF_EN 1\n+#define CONFIG_IO_5_PD_DRV_STRG 10\n+#define CONFIG_IO_5_PD_SLW_RT 1\n+#define CONFIG_IO_5_PU_DRV_STRG 8\n+#define CONFIG_IO_5_PU_SLW_RT 1\n+#define CONFIG_IO_5_RTRIM 1\n+#define CONFIG_IO_5_WK_PU_EN 0\n+#define CONFIG_IO_6_INPUT_BUF_EN 0\n+#define CONFIG_IO_6_PD_DRV_STRG 10\n+#define CONFIG_IO_6_PD_SLW_RT 1\n+#define CONFIG_IO_6_PU_DRV_STRG 8\n+#define CONFIG_IO_6_PU_SLW_RT 1\n+#define CONFIG_IO_6_RTRIM 1\n+#define CONFIG_IO_6_WK_PU_EN 0\n+#define CONFIG_IO_7_INPUT_BUF_EN 1\n+#define CONFIG_IO_7_PD_DRV_STRG 10\n+#define CONFIG_IO_7_PD_SLW_RT 1\n+#define CONFIG_IO_7_PU_DRV_STRG 8\n+#define CONFIG_IO_7_PU_SLW_RT 1\n+#define CONFIG_IO_7_RTRIM 1\n+#define CONFIG_IO_7_WK_PU_EN 0\n+#define CONFIG_IO_8_INPUT_BUF_EN 1\n+#define CONFIG_IO_8_PD_DRV_STRG 10\n+#define CONFIG_IO_8_PD_SLW_RT 1\n+#define CONFIG_IO_8_PU_DRV_STRG 8\n+#define CONFIG_IO_8_PU_SLW_RT 1\n+#define CONFIG_IO_8_RTRIM 1\n+#define CONFIG_IO_8_WK_PU_EN 0\n+#define CONFIG_IO_9_INPUT_BUF_EN 1\n+#define CONFIG_IO_9_PD_DRV_STRG 10\n+#define CONFIG_IO_9_PD_SLW_RT 1\n+#define CONFIG_IO_9_PU_DRV_STRG 8\n+#define CONFIG_IO_9_PU_SLW_RT 1\n+#define CONFIG_IO_9_RTRIM 1\n+#define CONFIG_IO_9_WK_PU_EN 0\n+#define CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO 1\n+#define CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO 1\n+#define PINMUX_DEDICATED_IO_10_SEL 15\n+#define PINMUX_DEDICATED_IO_11_SEL 15\n+#define PINMUX_DEDICATED_IO_12_SEL 1\n+#define PINMUX_DEDICATED_IO_13_SEL 1\n+#define PINMUX_DEDICATED_IO_14_SEL 10\n+#define PINMUX_DEDICATED_IO_15_SEL 10\n+#define PINMUX_DEDICATED_IO_16_SEL 13\n+#define PINMUX_DEDICATED_IO_17_SEL 13\n+#define PINMUX_DEDICATED_IO_4_SEL 8\n+#define PINMUX_DEDICATED_IO_5_SEL 8\n+#define PINMUX_DEDICATED_IO_6_SEL 8\n+#define PINMUX_DEDICATED_IO_7_SEL 8\n+#define PINMUX_DEDICATED_IO_8_SEL 8\n+#define PINMUX_DEDICATED_IO_9_SEL 8\n+#define PINMUX_I2C0_USEFPGA_SEL 1\n+#define PINMUX_I2C1_USEFPGA_SEL 0\n+#define PINMUX_I2CEMAC0_USEFPGA_SEL 0\n+#define PINMUX_I2CEMAC1_USEFPGA_SEL 0\n+#define PINMUX_I2CEMAC2_USEFPGA_SEL 0\n+#define PINMUX_NAND_USEFPGA_SEL 0\n+#define PINMUX_PLL_CLOCK_OUT_USEFPGA_SEL 0\n+#define PINMUX_QSPI_USEFPGA_SEL 0\n+#define PINMUX_RGMII0_USEFPGA_SEL 0\n+#define PINMUX_RGMII1_USEFPGA_SEL 0\n+#define PINMUX_RGMII2_USEFPGA_SEL 0\n+#define PINMUX_SDMMC_USEFPGA_SEL 0\n+#define PINMUX_SHARED_IO_Q1_10_SEL 8\n+#define PINMUX_SHARED_IO_Q1_11_SEL 8\n+#define PINMUX_SHARED_IO_Q1_12_SEL 8\n+#define PINMUX_SHARED_IO_Q1_1_SEL 8\n+#define PINMUX_SHARED_IO_Q1_2_SEL 8\n+#define PINMUX_SHARED_IO_Q1_3_SEL 8\n+#define PINMUX_SHARED_IO_Q1_4_SEL 8\n+#define PINMUX_SHARED_IO_Q1_5_SEL 8\n+#define PINMUX_SHARED_IO_Q1_6_SEL 8\n+#define PINMUX_SHARED_IO_Q1_7_SEL 8\n+#define PINMUX_SHARED_IO_Q1_8_SEL 8\n+#define PINMUX_SHARED_IO_Q1_9_SEL 8\n+#define PINMUX_SHARED_IO_Q2_10_SEL 4\n+#define PINMUX_SHARED_IO_Q2_11_SEL 4\n+#define PINMUX_SHARED_IO_Q2_12_SEL 4\n+#define PINMUX_SHARED_IO_Q2_1_SEL 4\n+#define PINMUX_SHARED_IO_Q2_2_SEL 4\n+#define PINMUX_SHARED_IO_Q2_3_SEL 4\n+#define PINMUX_SHARED_IO_Q2_4_SEL 4\n+#define PINMUX_SHARED_IO_Q2_5_SEL 4\n+#define PINMUX_SHARED_IO_Q2_6_SEL 4\n+#define PINMUX_SHARED_IO_Q2_7_SEL 4\n+#define PINMUX_SHARED_IO_Q2_8_SEL 4\n+#define PINMUX_SHARED_IO_Q2_9_SEL 4\n+#define PINMUX_SHARED_IO_Q3_10_SEL 15\n+#define PINMUX_SHARED_IO_Q3_11_SEL 1\n+#define PINMUX_SHARED_IO_Q3_12_SEL 1\n+#define PINMUX_SHARED_IO_Q3_1_SEL 15\n+#define PINMUX_SHARED_IO_Q3_2_SEL 15\n+#define PINMUX_SHARED_IO_Q3_3_SEL 15\n+#define PINMUX_SHARED_IO_Q3_4_SEL 15\n+#define PINMUX_SHARED_IO_Q3_5_SEL 15\n+#define PINMUX_SHARED_IO_Q3_6_SEL 15\n+#define PINMUX_SHARED_IO_Q3_7_SEL 0\n+#define PINMUX_SHARED_IO_Q3_8_SEL 0\n+#define PINMUX_SHARED_IO_Q3_9_SEL 15\n+#define PINMUX_SHARED_IO_Q4_10_SEL 10\n+#define PINMUX_SHARED_IO_Q4_11_SEL 10\n+#define PINMUX_SHARED_IO_Q4_12_SEL 10\n+#define PINMUX_SHARED_IO_Q4_1_SEL 10\n+#define PINMUX_SHARED_IO_Q4_2_SEL 10\n+#define PINMUX_SHARED_IO_Q4_3_SEL 10\n+#define PINMUX_SHARED_IO_Q4_4_SEL 10\n+#define PINMUX_SHARED_IO_Q4_5_SEL 10\n+#define PINMUX_SHARED_IO_Q4_6_SEL 10\n+#define PINMUX_SHARED_IO_Q4_7_SEL 10\n+#define PINMUX_SHARED_IO_Q4_8_SEL 10\n+#define PINMUX_SHARED_IO_Q4_9_SEL 10\n+#define PINMUX_SPIM0_USEFPGA_SEL 0\n+#define PINMUX_SPIM1_USEFPGA_SEL 0\n+#define PINMUX_SPIS0_USEFPGA_SEL 0\n+#define PINMUX_SPIS1_USEFPGA_SEL 0\n+#define PINMUX_UART0_USEFPGA_SEL 1\n+#define PINMUX_UART1_USEFPGA_SEL 0\n+#define PINMUX_USB0_USEFPGA_SEL 0\n+#define PINMUX_USB1_USEFPGA_SEL 0\n+\n+/* Bridge Configuration */\n+#define F2H_AXI_SLAVE 1\n+#define F2SDRAM0_AXI_SLAVE 1\n+#define F2SDRAM1_AXI_SLAVE 1\n+#define F2SDRAM2_AXI_SLAVE 1\n+#define H2F_AXI_MASTER 1\n+#define LWH2F_AXI_MASTER 1\n+\n+/* Voltage Select for Config IO */\n+#define CONFIG_IO_BANK_VSEL \\\n+\t(((CONFIG_IO_BANK_VOLTAGE_SEL_CLKRST_IO & 0x3) << 8) | \\\n+\t(CONFIG_IO_BANK_VOLTAGE_SEL_PERI_IO & 0x3))\n+\n+/* Macro for Config IO bit mapping */\n+#define CONFIG_IO_MACRO(NAME) (((NAME ## _RTRIM & 0xff) << 19) | \\\n+\t((NAME ## _INPUT_BUF_EN & 0x3) << 17) | \\\n+\t((NAME ## _WK_PU_EN & 0x1) << 16) | \\\n+\t((NAME ## _PU_SLW_RT & 0x1) << 13) | \\\n+\t((NAME ## _PU_DRV_STRG & 0xf) << 8) | \\\n+\t((NAME ## _PD_SLW_RT & 0x1) << 5) | \\\n+\t(NAME ## _PD_DRV_STRG & 0x1f))\n+\n+#endif /* __SOCFPGA_ARRIA10_CONFIG_H__ */\n", "prefixes": [ "v3", "02/11" ] }