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GET /api/patches/1641675/?format=api
{ "id": 1641675, "url": "http://patchwork.ozlabs.org/api/patches/1641675/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-ide/patch/20220610081801.11854-20-Sergey.Semin@baikalelectronics.ru/", "project": { "id": 13, "url": "http://patchwork.ozlabs.org/api/projects/13/?format=api", "name": "Linux IDE development", "link_name": "linux-ide", "list_id": "linux-ide.vger.kernel.org", "list_email": "linux-ide@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20220610081801.11854-20-Sergey.Semin@baikalelectronics.ru>", "list_archive_url": null, "date": "2022-06-10T08:17:57", "name": "[v4,19/23] ata: ahci: Add DWC AHCI SATA controller support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "165732ca0363a488c47c44851bf9aa1cffe2cf2f", "submitter": { "id": 78624, "url": "http://patchwork.ozlabs.org/api/people/78624/?format=api", "name": "Serge Semin", "email": "Sergey.Semin@baikalelectronics.ru" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-ide/patch/20220610081801.11854-20-Sergey.Semin@baikalelectronics.ru/mbox/", "series": [ { "id": 304159, "url": "http://patchwork.ozlabs.org/api/series/304159/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-ide/list/?series=304159", "date": "2022-06-10T08:17:42", "name": "ata: ahci: Add DWC/Baikal-T1 AHCI SATA support", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/304159/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1641675/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1641675/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-ide-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "bilbo.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=baikalelectronics.ru header.i=@baikalelectronics.ru\n header.a=rsa-sha256 header.s=mail header.b=UhjNqkdT;\n\tdkim-atps=neutral", "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2620:137:e000::1:20; helo=out1.vger.email;\n envelope-from=linux-ide-owner@vger.kernel.org; receiver=<UNKNOWN>)" ], "Received": [ "from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20])\n\tby bilbo.ozlabs.org (Postfix) with ESMTP id 4LKDQ030Gvz9s5V\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 10 Jun 2022 18:19:04 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n id S1347483AbiFJITB (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n Fri, 10 Jun 2022 04:19:01 -0400", "from lindbergh.monkeyblade.net ([23.128.96.19]:35934 \"EHLO\n lindbergh.monkeyblade.net\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n with ESMTP id S1347295AbiFJISm (ORCPT\n <rfc822;linux-ide@vger.kernel.org>); Fri, 10 Jun 2022 04:18:42 -0400", "from mail.baikalelectronics.com (mail.baikalelectronics.com\n [87.245.175.230])\n by lindbergh.monkeyblade.net (Postfix) with ESMTP id DCBD024C0B9;\n Fri, 10 Jun 2022 01:18:38 -0700 (PDT)", "from mail (mail.baikal.int [192.168.51.25])\n by mail.baikalelectronics.com (Postfix) with ESMTP id 476A316A7;\n Fri, 10 Jun 2022 11:19:11 +0300 (MSK)", "from localhost (192.168.53.207) by mail (192.168.51.25) with\n Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 10 Jun 2022 11:18:19 +0300" ], "DKIM-Filter": "OpenDKIM Filter v2.11.0 mail.baikalelectronics.com 476A316A7", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=baikalelectronics.ru; s=mail; t=1654849151;\n bh=M81wYYsdKNXa+ZZwg4pFUnZGLhl3d4svGtT5zJ/TRRI=;\n h=From:To:CC:Subject:Date:In-Reply-To:References:From;\n b=UhjNqkdTDrSWR64key91iTxh7JIM5PEXiKQdsheBV67ohOcq1PwRfaeOMmTZTIOny\n nV8wltiHacxhLNCkjrmZNjQt3a9JjLTeIG5buHn/aZJNUcWHz/75a5S8WsYp9FP/wT\n lo1rpLY1qHuyUNv0YlHmGrL3NYJqgMfHjOZ1WrfU=", "From": "Serge Semin <Sergey.Semin@baikalelectronics.ru>", "To": "Damien Le Moal <damien.lemoal@opensource.wdc.com>,\n Hans de Goede <hdegoede@redhat.com>,\n Jens Axboe <axboe@kernel.dk>, Hannes Reinecke <hare@suse.de>,\n Serge Semin <fancer.lancer@gmail.com>", "CC": "Serge Semin <Sergey.Semin@baikalelectronics.ru>,\n Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,\n Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>,\n Rob Herring <robh+dt@kernel.org>, <linux-ide@vger.kernel.org>,\n <linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>", "Subject": "[PATCH v4 19/23] ata: ahci: Add DWC AHCI SATA controller support", "Date": "Fri, 10 Jun 2022 11:17:57 +0300", "Message-ID": "<20220610081801.11854-20-Sergey.Semin@baikalelectronics.ru>", "In-Reply-To": "<20220610081801.11854-1-Sergey.Semin@baikalelectronics.ru>", "References": "<20220610081801.11854-1-Sergey.Semin@baikalelectronics.ru>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25)", "X-Spam-Status": "No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS,\n T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no\n version=3.4.6", "X-Spam-Checker-Version": "SpamAssassin 3.4.6 (2021-04-09) on\n lindbergh.monkeyblade.net", "Precedence": "bulk", "List-ID": "<linux-ide.vger.kernel.org>", "X-Mailing-List": "linux-ide@vger.kernel.org" }, "content": "Synopsys AHCI SATA controller can work pretty under with the generic\nAHCI-platform driver control. But there are vendor-specific peculiarities\nwhich can tune the device performance up and which may need to be fixed up\nfor proper device functioning. In addition some DWC AHCI-based controllers\nmay require small platform-specific fixups, so adding them in the generic\nAHCI driver would have ruined the code simplicity. Shortly speaking in\norder to keep the generic AHCI-platform code clean and have DWC AHCI\nSATA-specific features supported we suggest to add a dedicated DWC AHCI\nSATA device driver. Aside with the standard AHCI-platform resources\ngetting, enabling/disabling and the controller registration the new driver\nperforms the next actions.\n\nFirst of all there is a way to verify whether the HBA/ports capabilities\nactivated in OF are correct. Almost all features availability is reflected\nin the vendor-specific parameters registers. So the DWC AHCI driver does\nthe capabilities sanity check based on the corresponding fields state.\n\nSecondly if either the Command Completion Coalescing or the Device Sleep\nfeature is enabled the DWC AHCI-specific internal 1ms timer must be fixed\nin accordance with the application clock signal frequency. In particular\nthe timer value must be set to be Fapp * 1000. Normally the SoC designers\npre-configure the TIMER1MS register to contain a correct value by default.\nBut the platforms can support the application clock rate change. If that\nhappens the 1ms timer value must be accordingly updated otherwise the\ndependent features won't work as expected. In the DWC AHCI driver we\nsuggest to rely on the \"aclk\" reference clock rate to set the timer\ninterval up. That clock source is supposed to be the AHCI SATA application\nclock in accordance with the DT bindings.\n\nFinally DWC AHCI SATA controller AXI/AHB bus DMA-engine can be tuned up to\ntransfer up to 1024 * FIFO words at a time by setting the Tx/Rx\ntransaction size in the DMA control register. The maximum value depends on\nthe DMA data bus and AXI/AHB bus maximum burst length. In most of the\ncases it's better to set the maximum possible value to reach the best AHCI\nSATA controller performance. But sometimes in order to improve the system\ninterconnect responsiveness, transferring in smaller data chunks may be\nmore preferable. For such cases and for the case when the default value\ndoesn't provide the best DMA bus performance we suggest to use the new\nHBA-port specific DT-properties \"snps,{tx,rx}-ts-max\" to tune the DMA\ntransactions size up.\n\nAfter all the settings denoted above are handled the DWC AHCI SATA driver\nproceeds further with the standard AHCI-platform host initializations.\n\nNote since DWC AHCI controller is now have a dedicated driver we can\ndiscard the corresponding compatible string from the ahci-platform.c\nmodule. The same concerns \"snps,spear-ahci\" compatible string, which is\nalso based on the DWC AHCI IP-core.\n\nSigned-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>\nReviewed-by: Hannes Reinecke <hare@suse.de>\n\n---\n\nNote there are three more AHCI SATA drivers which have been created for\nthe devices based on the DWC AHCI SATA IP-core. It's AHCI SunXi, St and\niMX drivers. Mostly they don't support the features implemented in this\ndriver. So hopefully sometime in future they can be converted to be based\non the generic DWC AHCI SATA driver and just perform some\nsubvendor-specific setups in their own LLDD (glue) driver code. But for\nnow let's leave the generic DWC AHCI SATA code as is. Hopefully the new\nDWC AHCI-based device drivers will try at least to re-use a part of the\nDWC AHCI driver methods if not being able to be integrated in the generic\nDWC driver code.\n\nChangelog v2:\n- Change the local objects prefix from 'dwc_ahci_' to 'ahci_dwc_'.\n (@Damien)\n\nChangelog v4:\n- Replace GPLv2 with just GPL license which are the same in the framework\n of the MODULE_LICENSE() macro.\n---\n drivers/ata/Kconfig | 10 +\n drivers/ata/Makefile | 1 +\n drivers/ata/ahci_dwc.c | 395 ++++++++++++++++++++++++++++++++++++\n drivers/ata/ahci_platform.c | 2 -\n 4 files changed, 406 insertions(+), 2 deletions(-)\n create mode 100644 drivers/ata/ahci_dwc.c", "diff": "diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig\nindex bb45a9c00514..95e0e022b5bb 100644\n--- a/drivers/ata/Kconfig\n+++ b/drivers/ata/Kconfig\n@@ -176,6 +176,16 @@ config AHCI_DM816\n \n \t If unsure, say N.\n \n+config AHCI_DWC\n+\ttristate \"Synopsys DWC AHCI SATA support\"\n+\tselect SATA_HOST\n+\tdefault SATA_AHCI_PLATFORM\n+\thelp\n+\t This option enables support for the Synopsys DWC AHCI SATA\n+\t controller implementation.\n+\n+\t If unsure, say N.\n+\n config AHCI_ST\n \ttristate \"ST AHCI SATA support\"\n \tdepends on ARCH_STI\ndiff --git a/drivers/ata/Makefile b/drivers/ata/Makefile\nindex b8aebfb14e82..34623365d9a6 100644\n--- a/drivers/ata/Makefile\n+++ b/drivers/ata/Makefile\n@@ -17,6 +17,7 @@ obj-$(CONFIG_AHCI_BRCM)\t\t+= ahci_brcm.o libahci.o libahci_platform.o\n obj-$(CONFIG_AHCI_CEVA)\t\t+= ahci_ceva.o libahci.o libahci_platform.o\n obj-$(CONFIG_AHCI_DA850)\t+= ahci_da850.o libahci.o libahci_platform.o\n obj-$(CONFIG_AHCI_DM816)\t+= ahci_dm816.o libahci.o libahci_platform.o\n+obj-$(CONFIG_AHCI_DWC)\t\t+= ahci_dwc.o libahci.o libahci_platform.o\n obj-$(CONFIG_AHCI_IMX)\t\t+= ahci_imx.o libahci.o libahci_platform.o\n obj-$(CONFIG_AHCI_MTK)\t\t+= ahci_mtk.o libahci.o libahci_platform.o\n obj-$(CONFIG_AHCI_MVEBU)\t+= ahci_mvebu.o libahci.o libahci_platform.o\ndiff --git a/drivers/ata/ahci_dwc.c b/drivers/ata/ahci_dwc.c\nnew file mode 100644\nindex 000000000000..8c2510933a31\n--- /dev/null\n+++ b/drivers/ata/ahci_dwc.c\n@@ -0,0 +1,395 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+/*\n+ * DWC AHCI SATA Platform driver\n+ *\n+ * Copyright (C) 2021 BAIKAL ELECTRONICS, JSC\n+ */\n+\n+#include <linux/ahci_platform.h>\n+#include <linux/bitfield.h>\n+#include <linux/bits.h>\n+#include <linux/clk.h>\n+#include <linux/device.h>\n+#include <linux/kernel.h>\n+#include <linux/libata.h>\n+#include <linux/log2.h>\n+#include <linux/module.h>\n+#include <linux/of_device.h>\n+#include <linux/platform_device.h>\n+#include <linux/pm.h>\n+\n+#include \"ahci.h\"\n+\n+#define DRV_NAME \"ahci-dwc\"\n+\n+#define AHCI_DWC_FBS_PMPN_MAX\t\t15\n+\n+/* DWC AHCI SATA controller specific registers */\n+#define AHCI_DWC_HOST_OOBR\t\t0xbc\n+#define AHCI_DWC_HOST_OOB_WE\t\tBIT(31)\n+#define AHCI_DWC_HOST_CWMIN_MASK\tGENMASK(30, 24)\n+#define AHCI_DWC_HOST_CWMAX_MASK\tGENMASK(23, 16)\n+#define AHCI_DWC_HOST_CIMIN_MASK\tGENMASK(15, 8)\n+#define AHCI_DWC_HOST_CIMAX_MASK\tGENMASK(7, 0)\n+\n+#define AHCI_DWC_HOST_GPCR\t\t0xd0\n+#define AHCI_DWC_HOST_GPSR\t\t0xd4\n+\n+#define AHCI_DWC_HOST_TIMER1MS\t\t0xe0\n+#define AHCI_DWC_HOST_TIMV_MASK\t\tGENMASK(19, 0)\n+\n+#define AHCI_DWC_HOST_GPARAM1R\t\t0xe8\n+#define AHCI_DWC_HOST_ALIGN_M\t\tBIT(31)\n+#define AHCI_DWC_HOST_RX_BUFFER\t\tBIT(30)\n+#define AHCI_DWC_HOST_PHY_DATA_MASK\tGENMASK(29, 28)\n+#define AHCI_DWC_HOST_PHY_RST\t\tBIT(27)\n+#define AHCI_DWC_HOST_PHY_CTRL_MASK\tGENMASK(26, 21)\n+#define AHCI_DWC_HOST_PHY_STAT_MASK\tGENMASK(20, 15)\n+#define AHCI_DWC_HOST_LATCH_M\t\tBIT(14)\n+#define AHCI_DWC_HOST_PHY_TYPE_MASK\tGENMASK(13, 11)\n+#define AHCI_DWC_HOST_RET_ERR\t\tBIT(10)\n+#define AHCI_DWC_HOST_AHB_ENDIAN_MASK\tGENMASK(9, 8)\n+#define AHCI_DWC_HOST_S_HADDR\t\tBIT(7)\n+#define AHCI_DWC_HOST_M_HADDR\t\tBIT(6)\n+#define AHCI_DWC_HOST_S_HDATA_MASK\tGENMASK(5, 3)\n+#define AHCI_DWC_HOST_M_HDATA_MASK\tGENMASK(2, 0)\n+\n+#define AHCI_DWC_HOST_GPARAM2R\t\t0xec\n+#define AHCI_DWC_HOST_FBS_MEM_S\t\tBIT(19)\n+#define AHCI_DWC_HOST_FBS_PMPN_MASK\tGENMASK(17, 16)\n+#define AHCI_DWC_HOST_FBS_SUP\t\tBIT(15)\n+#define AHCI_DWC_HOST_DEV_CP\t\tBIT(14)\n+#define AHCI_DWC_HOST_DEV_MP\t\tBIT(13)\n+#define AHCI_DWC_HOST_ENCODE_M\t\tBIT(12)\n+#define AHCI_DWC_HOST_RXOOB_CLK_M\tBIT(11)\n+#define AHCI_DWC_HOST_RXOOB_M\t\tBIT(10)\n+#define AHCI_DWC_HOST_TXOOB_M\t\tBIT(9)\n+#define AHCI_DWC_HOST_RXOOB_M\t\tBIT(10)\n+#define AHCI_DWC_HOST_RXOOB_CLK_MASK\tGENMASK(8, 0)\n+\n+#define AHCI_DWC_HOST_PPARAMR\t\t0xf0\n+#define AHCI_DWC_HOST_TX_MEM_M\t\tBIT(11)\n+#define AHCI_DWC_HOST_TX_MEM_S\t\tBIT(10)\n+#define AHCI_DWC_HOST_RX_MEM_M\t\tBIT(9)\n+#define AHCI_DWC_HOST_RX_MEM_S\t\tBIT(8)\n+#define AHCI_DWC_HOST_TXFIFO_DEPTH\tGENMASK(7, 4)\n+#define AHCI_DWC_HOST_RXFIFO_DEPTH\tGENMASK(3, 0)\n+\n+#define AHCI_DWC_HOST_TESTR\t\t0xf4\n+#define AHCI_DWC_HOST_PSEL_MASK\t\tGENMASK(18, 16)\n+#define AHCI_DWC_HOST_TEST_IF\t\tBIT(0)\n+\n+#define AHCI_DWC_HOST_VERSIONR\t\t0xf8\n+#define AHCI_DWC_HOST_IDR\t\t0xfc\n+\n+#define AHCI_DWC_PORT_DMACR\t\t0x70\n+#define AHCI_DWC_PORT_RXABL_MASK\tGENMASK(15, 12)\n+#define AHCI_DWC_PORT_TXABL_MASK\tGENMASK(11, 8)\n+#define AHCI_DWC_PORT_RXTS_MASK\t\tGENMASK(7, 4)\n+#define AHCI_DWC_PORT_TXTS_MASK\t\tGENMASK(3, 0)\n+#define AHCI_DWC_PORT_PHYCR\t\t0x74\n+#define AHCI_DWC_PORT_PHYSR\t\t0x78\n+\n+struct ahci_dwc_host_priv {\n+\tstruct platform_device *pdev;\n+\n+\tu32 timv;\n+\tu32 dmacr[AHCI_MAX_PORTS];\n+};\n+\n+static struct ahci_host_priv *ahci_dwc_get_resources(struct platform_device *pdev)\n+{\n+\tstruct ahci_dwc_host_priv *dpriv;\n+\tstruct ahci_host_priv *hpriv;\n+\n+\tdpriv = devm_kzalloc(&pdev->dev, sizeof(*dpriv), GFP_KERNEL);\n+\tif (!dpriv)\n+\t\treturn ERR_PTR(-ENOMEM);\n+\n+\tdpriv->pdev = pdev;\n+\n+\thpriv = ahci_platform_get_resources(pdev, AHCI_PLATFORM_GET_RESETS);\n+\tif (IS_ERR(hpriv))\n+\t\treturn hpriv;\n+\n+\thpriv->plat_data = (void *)dpriv;\n+\n+\treturn hpriv;\n+}\n+\n+static void ahci_dwc_check_cap(struct ahci_host_priv *hpriv)\n+{\n+\tunsigned long port_map = hpriv->saved_port_map | hpriv->mask_port_map;\n+\tstruct ahci_dwc_host_priv *dpriv = hpriv->plat_data;\n+\tbool dev_mp, dev_cp, fbs_sup;\n+\tunsigned int fbs_pmp;\n+\tu32 param;\n+\tint i;\n+\n+\tparam = readl(hpriv->mmio + AHCI_DWC_HOST_GPARAM2R);\n+\tdev_mp = !!(param & AHCI_DWC_HOST_DEV_MP);\n+\tdev_cp = !!(param & AHCI_DWC_HOST_DEV_CP);\n+\tfbs_sup = !!(param & AHCI_DWC_HOST_FBS_SUP);\n+\tfbs_pmp = 5 * FIELD_GET(AHCI_DWC_HOST_FBS_PMPN_MASK, param);\n+\n+\tif (!dev_mp && hpriv->saved_cap & HOST_CAP_MPS) {\n+\t\tdev_warn(&dpriv->pdev->dev, \"MPS is unsupported\\n\");\n+\t\thpriv->saved_cap &= ~HOST_CAP_MPS;\n+\t}\n+\n+\n+\tif (fbs_sup && fbs_pmp < AHCI_DWC_FBS_PMPN_MAX) {\n+\t\tdev_warn(&dpriv->pdev->dev, \"PMPn is limited up to %u ports\\n\",\n+\t\t\t fbs_pmp);\n+\t}\n+\n+\tfor_each_set_bit(i, &port_map, AHCI_MAX_PORTS) {\n+\t\tif (!dev_mp && hpriv->saved_port_cap[i] & PORT_CMD_MPSP) {\n+\t\t\tdev_warn(&dpriv->pdev->dev, \"MPS incapable port %d\\n\", i);\n+\t\t\thpriv->saved_port_cap[i] &= ~PORT_CMD_MPSP;\n+\t\t}\n+\n+\t\tif (!dev_cp && hpriv->saved_port_cap[i] & PORT_CMD_CPD) {\n+\t\t\tdev_warn(&dpriv->pdev->dev, \"CPD incapable port %d\\n\", i);\n+\t\t\thpriv->saved_port_cap[i] &= ~PORT_CMD_CPD;\n+\t\t}\n+\n+\t\tif (!fbs_sup && hpriv->saved_port_cap[i] & PORT_CMD_FBSCP) {\n+\t\t\tdev_warn(&dpriv->pdev->dev, \"FBS incapable port %d\\n\", i);\n+\t\t\thpriv->saved_port_cap[i] &= ~PORT_CMD_FBSCP;\n+\t\t}\n+\t}\n+}\n+\n+static void ahci_dwc_init_timer(struct ahci_host_priv *hpriv)\n+{\n+\tstruct ahci_dwc_host_priv *dpriv = hpriv->plat_data;\n+\tunsigned long rate;\n+\tstruct clk *aclk;\n+\tu32 cap, cap2;\n+\n+\t/* 1ms tick is generated only for the CCC or DevSleep features */\n+\tcap = readl(hpriv->mmio + HOST_CAP);\n+\tcap2 = readl(hpriv->mmio + HOST_CAP2);\n+\tif (!(cap & HOST_CAP_CCC) && !(cap2 & HOST_CAP2_SDS))\n+\t\treturn;\n+\n+\t/*\n+\t * Tick is generated based on the AXI/AHB application clocks signal\n+\t * so we need to be sure in the clock we are going to use.\n+\t */\n+\taclk = ahci_platform_find_clk(hpriv, \"aclk\");\n+\tif (!aclk)\n+\t\treturn;\n+\n+\t/* 1ms timer interval is set as TIMV = AMBA_FREQ[MHZ] * 1000 */\n+\tdpriv->timv = readl(hpriv->mmio + AHCI_DWC_HOST_TIMER1MS);\n+\tdpriv->timv = FIELD_GET(AHCI_DWC_HOST_TIMV_MASK, dpriv->timv);\n+\trate = clk_get_rate(aclk) / 1000UL;\n+\tif (rate == dpriv->timv)\n+\t\treturn;\n+\n+\tdev_info(&dpriv->pdev->dev, \"Update CCC/DevSlp timer for Fapp %lu MHz\\n\",\n+\t\t rate / 1000UL);\n+\tdpriv->timv = FIELD_PREP(AHCI_DWC_HOST_TIMV_MASK, rate);\n+\twritel(dpriv->timv, hpriv->mmio + AHCI_DWC_HOST_TIMER1MS);\n+}\n+\n+static int ahci_dwc_init_dmacr(struct ahci_host_priv *hpriv)\n+{\n+\tstruct ahci_dwc_host_priv *dpriv = hpriv->plat_data;\n+\tstruct device_node *child;\n+\tvoid __iomem *port_mmio;\n+\tu32 port, dmacr, ts;\n+\n+\t/*\n+\t * Update the DMA Tx/Rx transaction sizes in accordance with the\n+\t * platform setup. Note values exceeding maximal or minimal limits will\n+\t * be automatically clamped. Also note the register isn't affected by\n+\t * the HBA global reset so we can freely initialize it once until the\n+\t * next system reset.\n+\t */\n+\tfor_each_child_of_node(dpriv->pdev->dev.of_node, child) {\n+\t\tif (!of_device_is_available(child))\n+\t\t\tcontinue;\n+\n+\t\tif (of_property_read_u32(child, \"reg\", &port)) {\n+\t\t\tof_node_put(child);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\n+\t\tport_mmio = __ahci_port_base(hpriv, port);\n+\t\tdmacr = readl(port_mmio + AHCI_DWC_PORT_DMACR);\n+\n+\t\tif (!of_property_read_u32(child, \"snps,tx-ts-max\", &ts)) {\n+\t\t\tts = ilog2(ts);\n+\t\t\tdmacr &= ~AHCI_DWC_PORT_TXTS_MASK;\n+\t\t\tdmacr |= FIELD_PREP(AHCI_DWC_PORT_TXTS_MASK, ts);\n+\t\t}\n+\n+\t\tif (!of_property_read_u32(child, \"snps,rx-ts-max\", &ts)) {\n+\t\t\tts = ilog2(ts);\n+\t\t\tdmacr &= ~AHCI_DWC_PORT_RXTS_MASK;\n+\t\t\tdmacr |= FIELD_PREP(AHCI_DWC_PORT_RXTS_MASK, ts);\n+\t\t}\n+\n+\t\twritel(dmacr, port_mmio + AHCI_DWC_PORT_DMACR);\n+\t\tdpriv->dmacr[port] = dmacr;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int ahci_dwc_init_host(struct ahci_host_priv *hpriv)\n+{\n+\tint rc;\n+\n+\trc = ahci_platform_enable_resources(hpriv);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tahci_dwc_check_cap(hpriv);\n+\n+\tahci_dwc_init_timer(hpriv);\n+\n+\trc = ahci_dwc_init_dmacr(hpriv);\n+\tif (rc)\n+\t\tgoto err_disable_resources;\n+\n+\treturn 0;\n+\n+err_disable_resources:\n+\tahci_platform_disable_resources(hpriv);\n+\n+\treturn rc;\n+}\n+\n+static int ahci_dwc_reinit_host(struct ahci_host_priv *hpriv)\n+{\n+\tstruct ahci_dwc_host_priv *dpriv = hpriv->plat_data;\n+\tunsigned long port_map = hpriv->port_map;\n+\tvoid __iomem *port_mmio;\n+\tint i, rc;\n+\n+\trc = ahci_platform_enable_resources(hpriv);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\twritel(dpriv->timv, hpriv->mmio + AHCI_DWC_HOST_TIMER1MS);\n+\n+\tfor_each_set_bit(i, &port_map, AHCI_MAX_PORTS) {\n+\t\tport_mmio = __ahci_port_base(hpriv, i);\n+\t\twritel(dpriv->dmacr[i], port_mmio + AHCI_DWC_PORT_DMACR);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void ahci_dwc_clear_host(struct ahci_host_priv *hpriv)\n+{\n+\tahci_platform_disable_resources(hpriv);\n+}\n+\n+static void ahci_dwc_stop_host(struct ata_host *host)\n+{\n+\tstruct ahci_host_priv *hpriv = host->private_data;\n+\n+\tahci_dwc_clear_host(hpriv);\n+}\n+\n+static struct ata_port_operations ahci_dwc_port_ops = {\n+\t.inherits\t= &ahci_platform_ops,\n+\t.host_stop\t= ahci_dwc_stop_host,\n+};\n+\n+static const struct ata_port_info ahci_dwc_port_info = {\n+\t.flags\t\t= AHCI_FLAG_COMMON,\n+\t.pio_mask\t= ATA_PIO4,\n+\t.udma_mask\t= ATA_UDMA6,\n+\t.port_ops\t= &ahci_dwc_port_ops,\n+};\n+\n+static struct scsi_host_template ahci_dwc_scsi_info = {\n+\tAHCI_SHT(DRV_NAME),\n+};\n+\n+static int ahci_dwc_probe(struct platform_device *pdev)\n+{\n+\tstruct ahci_host_priv *hpriv;\n+\tint rc;\n+\n+\thpriv = ahci_dwc_get_resources(pdev);\n+\tif (IS_ERR(hpriv))\n+\t\treturn PTR_ERR(hpriv);\n+\n+\trc = ahci_dwc_init_host(hpriv);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\trc = ahci_platform_init_host(pdev, hpriv, &ahci_dwc_port_info,\n+\t\t\t\t &ahci_dwc_scsi_info);\n+\tif (rc)\n+\t\tgoto err_clear_host;\n+\n+\treturn 0;\n+\n+err_clear_host:\n+\tahci_dwc_clear_host(hpriv);\n+\n+\treturn rc;\n+}\n+\n+#ifdef CONFIG_PM_SLEEP\n+static int ahci_dwc_suspend(struct device *dev)\n+{\n+\tstruct ata_host *host = dev_get_drvdata(dev);\n+\tstruct ahci_host_priv *hpriv = host->private_data;\n+\tint rc;\n+\n+\trc = ahci_platform_suspend_host(dev);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\tahci_dwc_clear_host(hpriv);\n+\n+\treturn 0;\n+}\n+\n+static int ahci_dwc_resume(struct device *dev)\n+{\n+\tstruct ata_host *host = dev_get_drvdata(dev);\n+\tstruct ahci_host_priv *hpriv = host->private_data;\n+\tint rc;\n+\n+\trc = ahci_dwc_reinit_host(hpriv);\n+\tif (rc)\n+\t\treturn rc;\n+\n+\treturn ahci_platform_resume_host(dev);\n+}\n+#endif\n+\n+static SIMPLE_DEV_PM_OPS(ahci_dwc_pm_ops, ahci_dwc_suspend, ahci_dwc_resume);\n+\n+static const struct of_device_id ahci_dwc_of_match[] = {\n+\t{ .compatible = \"snps,dwc-ahci\", },\n+\t{ .compatible = \"snps,spear-ahci\", },\n+\t{},\n+};\n+MODULE_DEVICE_TABLE(of, ahci_dwc_of_match);\n+\n+static struct platform_driver ahci_dwc_driver = {\n+\t.probe = ahci_dwc_probe,\n+\t.remove = ata_platform_remove_one,\n+\t.shutdown = ahci_platform_shutdown,\n+\t.driver = {\n+\t\t.name = DRV_NAME,\n+\t\t.of_match_table = ahci_dwc_of_match,\n+\t\t.pm = &ahci_dwc_pm_ops,\n+\t},\n+};\n+module_platform_driver(ahci_dwc_driver);\n+\n+MODULE_DESCRIPTION(\"DWC AHCI SATA platform driver\");\n+MODULE_AUTHOR(\"Serge Semin <Sergey.Semin@baikalelectronics.ru>\");\n+MODULE_LICENSE(\"GPL\");\ndiff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c\nindex 9b56490ecbc3..8f5572a9f8f1 100644\n--- a/drivers/ata/ahci_platform.c\n+++ b/drivers/ata/ahci_platform.c\n@@ -80,9 +80,7 @@ static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_platform_suspend,\n static const struct of_device_id ahci_of_match[] = {\n \t{ .compatible = \"generic-ahci\", },\n \t/* Keep the following compatibles for device tree compatibility */\n-\t{ .compatible = \"snps,spear-ahci\", },\n \t{ .compatible = \"ibm,476gtr-ahci\", },\n-\t{ .compatible = \"snps,dwc-ahci\", },\n \t{ .compatible = \"hisilicon,hisi-ahci\", },\n \t{ .compatible = \"cavium,octeon-7130-ahci\", },\n \t{ /* sentinel */ }\n", "prefixes": [ "v4", "19/23" ] }