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GET /api/patches/1641671/?format=api
{ "id": 1641671, "url": "http://patchwork.ozlabs.org/api/patches/1641671/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-ide/patch/20220610081801.11854-18-Sergey.Semin@baikalelectronics.ru/", "project": { "id": 13, "url": "http://patchwork.ozlabs.org/api/projects/13/?format=api", "name": "Linux IDE development", "link_name": "linux-ide", "list_id": "linux-ide.vger.kernel.org", "list_email": "linux-ide@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20220610081801.11854-18-Sergey.Semin@baikalelectronics.ru>", "list_archive_url": null, "date": "2022-06-10T08:17:55", "name": "[v4,17/23] dt-bindings: ata: ahci: Add DWC AHCI SATA controller DT schema", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3720227ce537ee1dc636022a8f2fdb72810897fa", "submitter": { "id": 78624, "url": "http://patchwork.ozlabs.org/api/people/78624/?format=api", "name": "Serge Semin", "email": "Sergey.Semin@baikalelectronics.ru" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-ide/patch/20220610081801.11854-18-Sergey.Semin@baikalelectronics.ru/mbox/", "series": [ { "id": 304159, "url": "http://patchwork.ozlabs.org/api/series/304159/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-ide/list/?series=304159", "date": "2022-06-10T08:17:42", "name": "ata: ahci: Add DWC/Baikal-T1 AHCI SATA support", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/304159/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1641671/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1641671/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-ide-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "bilbo.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=baikalelectronics.ru header.i=@baikalelectronics.ru\n header.a=rsa-sha256 header.s=mail header.b=hhE4Bplx;\n\tdkim-atps=neutral", "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2620:137:e000::1:20; helo=out1.vger.email;\n envelope-from=linux-ide-owner@vger.kernel.org; receiver=<UNKNOWN>)" ], "Received": [ "from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20])\n\tby bilbo.ozlabs.org (Postfix) with ESMTP id 4LKDPw05Ztz9s5V\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 10 Jun 2022 18:19:00 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n id S1347459AbiFJIS4 (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n Fri, 10 Jun 2022 04:18:56 -0400", "from lindbergh.monkeyblade.net ([23.128.96.19]:35878 \"EHLO\n lindbergh.monkeyblade.net\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n with ESMTP id S1347286AbiFJISm (ORCPT\n <rfc822;linux-ide@vger.kernel.org>); Fri, 10 Jun 2022 04:18:42 -0400", "from mail.baikalelectronics.com (mail.baikalelectronics.com\n [87.245.175.230])\n by lindbergh.monkeyblade.net (Postfix) with ESMTP id 848BD249327;\n Fri, 10 Jun 2022 01:18:31 -0700 (PDT)", "from mail (mail.baikal.int [192.168.51.25])\n by mail.baikalelectronics.com (Postfix) with ESMTP id 68B8C16A5;\n Fri, 10 Jun 2022 11:19:09 +0300 (MSK)", "from localhost (192.168.53.207) by mail (192.168.51.25) with\n Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 10 Jun 2022 11:18:17 +0300" ], "DKIM-Filter": "OpenDKIM Filter v2.11.0 mail.baikalelectronics.com 68B8C16A5", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=baikalelectronics.ru; s=mail; t=1654849149;\n bh=v9quJBEP04SYeGrjAbGmSbaRO29Vk1LoKwuBZscMaIY=;\n h=From:To:CC:Subject:Date:In-Reply-To:References:From;\n b=hhE4Bplx74gn4LzKcuy6bTaG/PgmrGU2o6YfQ0tzSrfEhA8Ow5KBR32zz8T80lXX+\n CwmDAj0vqNtifD8NtoM+SpURe9rN5zQy85aLUsio4Ft3sBRWAZxeUZVzU4veJ+XIV9\n HqZwrxcxGzVg4uU3eo61sqicyHsFx+4ovC7paudo=", "From": "Serge Semin <Sergey.Semin@baikalelectronics.ru>", "To": "Damien Le Moal <damien.lemoal@opensource.wdc.com>,\n Hans de Goede <hdegoede@redhat.com>,\n Jens Axboe <axboe@kernel.dk>, Hannes Reinecke <hare@suse.de>,\n Rob Herring <robh+dt@kernel.org>,\n Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,\n Serge Semin <fancer.lancer@gmail.com>", "CC": "Serge Semin <Sergey.Semin@baikalelectronics.ru>,\n Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,\n Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>,\n <linux-ide@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n <devicetree@vger.kernel.org>", "Subject": "[PATCH v4 17/23] dt-bindings: ata: ahci: Add DWC AHCI SATA controller\n DT schema", "Date": "Fri, 10 Jun 2022 11:17:55 +0300", "Message-ID": "<20220610081801.11854-18-Sergey.Semin@baikalelectronics.ru>", "In-Reply-To": "<20220610081801.11854-1-Sergey.Semin@baikalelectronics.ru>", "References": "<20220610081801.11854-1-Sergey.Semin@baikalelectronics.ru>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25)", "X-Spam-Status": "No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS,\n T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no\n version=3.4.6", "X-Spam-Checker-Version": "SpamAssassin 3.4.6 (2021-04-09) on\n lindbergh.monkeyblade.net", "Precedence": "bulk", "List-ID": "<linux-ide.vger.kernel.org>", "X-Mailing-List": "linux-ide@vger.kernel.org" }, "content": "Synopsys AHCI SATA controller is mainly compatible with the generic AHCI\nSATA controller except a few peculiarities and the platform environment\nrequirements. In particular it can have one or two reference clocks to\nfeed up its AXI/AHB interface and SATA PHYs domain and at least one reset\ncontrol for the application clock domain. In addition to that the DMA\ninterface of each port can be tuned up to work with the predefined maximum\ndata chunk size. Note unlike generic AHCI controller DWC AHCI can't have\nmore than 8 ports. All of that is reflected in the new DWC AHCI SATA\ndevice DT binding.\n\nNote the DWC AHCI SATA controller DT-schema has been created in a way so\nto be reused for the vendor-specific DT-schemas (see for example the\n\"snps,dwc-ahci\" compatible string binding). One of which we are about to\nintroduce.\n\nSigned-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>\n\n---\n\nChangelog v2:\n- Replace min/max constraints of the snps,{tx,rx}-ts-max property with\n enum [ 1, 2, 4, ..., 1024 ]. (@Rob)\n\nChangelog v4:\n- Decrease the \"additionalProperties\" property identation otherwise it's\n percieved as the node property instead of the key one. (@Rob)\n- Use the ahci-port properties definition from the AHCI common schema\n in order to extend it with DWC AHCI SATA port properties. (@Rob)\n- Remove the Hannes' rb tag since the patch content has changed.\n---\n .../bindings/ata/ahci-platform.yaml | 8 --\n .../bindings/ata/snps,dwc-ahci.yaml | 129 ++++++++++++++++++\n 2 files changed, 129 insertions(+), 8 deletions(-)\n create mode 100644 Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml", "diff": "diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.yaml b/Documentation/devicetree/bindings/ata/ahci-platform.yaml\nindex e19cf9828e68..7dc2a2e8f598 100644\n--- a/Documentation/devicetree/bindings/ata/ahci-platform.yaml\n+++ b/Documentation/devicetree/bindings/ata/ahci-platform.yaml\n@@ -30,8 +30,6 @@ select:\n - marvell,armada-3700-ahci\n - marvell,armada-8k-ahci\n - marvell,berlin2q-ahci\n- - snps,dwc-ahci\n- - snps,spear-ahci\n required:\n - compatible\n \n@@ -48,17 +46,11 @@ properties:\n - marvell,berlin2-ahci\n - marvell,berlin2q-ahci\n - const: generic-ahci\n- - items:\n- - enum:\n- - rockchip,rk3568-dwc-ahci\n- - const: snps,dwc-ahci\n - enum:\n - cavium,octeon-7130-ahci\n - hisilicon,hisi-ahci\n - ibm,476gtr-ahci\n - marvell,armada-3700-ahci\n- - snps,dwc-ahci\n- - snps,spear-ahci\n \n reg:\n minItems: 1\ndiff --git a/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml b/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml\nnew file mode 100644\nindex 000000000000..af78f6c9b857\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml\n@@ -0,0 +1,129 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Synopsys DWC AHCI SATA controller\n+\n+maintainers:\n+ - Serge Semin <fancer.lancer@gmail.com>\n+\n+description:\n+ This document defines device tree bindings for the Synopsys DWC\n+ implementation of the AHCI SATA controller.\n+\n+allOf:\n+ - $ref: ahci-common.yaml#\n+\n+properties:\n+ compatible:\n+ oneOf:\n+ - description: Synopsys AHCI SATA-compatible devices\n+ contains:\n+ const: snps,dwc-ahci\n+ - description: SPEAr1340 AHCI SATA device\n+ const: snps,spear-ahci\n+ - description: Rockhip RK3568 ahci controller\n+ const: rockchip,rk3568-dwc-ahci\n+\n+ reg:\n+ maxItems: 1\n+\n+ interrupts:\n+ maxItems: 1\n+\n+ clocks:\n+ description:\n+ Basic DWC AHCI SATA clock sources like application AXI/AHB BIU clock\n+ and embedded PHYs reference clock together with vendor-specific set\n+ of clocks.\n+ minItems: 1\n+ maxItems: 4\n+\n+ clock-names:\n+ contains:\n+ anyOf:\n+ - description: Application AXI/AHB BIU clock source\n+ enum:\n+ - aclk\n+ - sata\n+ - description: SATA Ports reference clock\n+ enum:\n+ - ref\n+ - sata_ref\n+\n+ resets:\n+ description:\n+ At least basic core and application clock domains reset is normally\n+ supported by the DWC AHCI SATA controller. Some platform specific\n+ clocks can be also specified though.\n+\n+ reset-names:\n+ contains:\n+ description: Core and application clock domains reset control\n+ const: arst\n+\n+patternProperties:\n+ \"^sata-port@[0-9a-e]$\":\n+ $ref: '#/$defs/dwc-ahci-port'\n+\n+ unevaluatedProperties: false\n+\n+required:\n+ - compatible\n+ - reg\n+ - interrupts\n+\n+unevaluatedProperties: false\n+\n+$defs:\n+ dwc-ahci-port:\n+ $ref: /schemas/ata/ahci-common.yaml#/$defs/ahci-port\n+\n+ properties:\n+ reg:\n+ minimum: 0\n+ maximum: 7\n+\n+ snps,tx-ts-max:\n+ $ref: /schemas/types.yaml#/definitions/uint32\n+ description: Maximal size of Tx DMA transactions in FIFO words\n+ enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 ]\n+\n+ snps,rx-ts-max:\n+ $ref: /schemas/types.yaml#/definitions/uint32\n+ description: Maximal size of Rx DMA transactions in FIFO words\n+ enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 ]\n+\n+examples:\n+ - |\n+ #include <dt-bindings/interrupt-controller/arm-gic.h>\n+ #include <dt-bindings/ata/ahci.h>\n+\n+ sata@122f0000 {\n+ compatible = \"snps,dwc-ahci\";\n+ reg = <0x122F0000 0x1ff>;\n+ #address-cells = <1>;\n+ #size-cells = <0>;\n+\n+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;\n+\n+ clocks = <&clock1>, <&clock2>;\n+ clock-names = \"aclk\", \"ref\";\n+\n+ phys = <&sata_phy>;\n+ phy-names = \"sata-phy\";\n+\n+ ports-implemented = <0x1>;\n+\n+ sata-port@0 {\n+ reg = <0>;\n+\n+ hba-port-cap = <HBA_PORT_FBSCP>;\n+\n+ snps,tx-ts-max = <512>;\n+ snps,rx-ts-max = <512>;\n+ };\n+ };\n+...\n", "prefixes": [ "v4", "17/23" ] }