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GET /api/patches/1641665/?format=api
{ "id": 1641665, "url": "http://patchwork.ozlabs.org/api/patches/1641665/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-ide/patch/20220610081801.11854-3-Sergey.Semin@baikalelectronics.ru/", "project": { "id": 13, "url": "http://patchwork.ozlabs.org/api/projects/13/?format=api", "name": "Linux IDE development", "link_name": "linux-ide", "list_id": "linux-ide.vger.kernel.org", "list_email": "linux-ide@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20220610081801.11854-3-Sergey.Semin@baikalelectronics.ru>", "list_archive_url": null, "date": "2022-06-10T08:17:40", "name": "[v4,02/23] dt-bindings: ata: ahci-platform: Detach common AHCI bindings", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "872ecca4e0b931ecdc3d6ed8316e429553e8810c", "submitter": { "id": 78624, "url": "http://patchwork.ozlabs.org/api/people/78624/?format=api", "name": "Serge Semin", "email": "Sergey.Semin@baikalelectronics.ru" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-ide/patch/20220610081801.11854-3-Sergey.Semin@baikalelectronics.ru/mbox/", "series": [ { "id": 304159, "url": "http://patchwork.ozlabs.org/api/series/304159/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-ide/list/?series=304159", "date": "2022-06-10T08:17:42", "name": "ata: ahci: Add DWC/Baikal-T1 AHCI SATA support", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/304159/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1641665/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1641665/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linux-ide-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "bilbo.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=baikalelectronics.ru header.i=@baikalelectronics.ru\n header.a=rsa-sha256 header.s=mail header.b=j9QBmc0b;\n\tdkim-atps=neutral", "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2620:137:e000::1:20; helo=out1.vger.email;\n envelope-from=linux-ide-owner@vger.kernel.org; receiver=<UNKNOWN>)" ], "Received": [ "from out1.vger.email (out1.vger.email [IPv6:2620:137:e000::1:20])\n\tby bilbo.ozlabs.org (Postfix) with ESMTP id 4LKDPm5THKz9s09\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 10 Jun 2022 18:18:52 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n id S1347393AbiFJISu (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n Fri, 10 Jun 2022 04:18:50 -0400", "from lindbergh.monkeyblade.net ([23.128.96.19]:34298 \"EHLO\n lindbergh.monkeyblade.net\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n with ESMTP id S1347364AbiFJISL (ORCPT\n <rfc822;linux-ide@vger.kernel.org>); Fri, 10 Jun 2022 04:18:11 -0400", "from mail.baikalelectronics.com (mail.baikalelectronics.com\n [87.245.175.230])\n by lindbergh.monkeyblade.net (Postfix) with ESMTP id 69615233561;\n Fri, 10 Jun 2022 01:18:09 -0700 (PDT)", "from mail (mail.baikal.int [192.168.51.25])\n by mail.baikalelectronics.com (Postfix) with ESMTP id 92B9116A3;\n Fri, 10 Jun 2022 11:18:57 +0300 (MSK)", "from localhost (192.168.53.207) by mail (192.168.51.25) with\n Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 10 Jun 2022 11:18:05 +0300" ], "DKIM-Filter": "OpenDKIM Filter v2.11.0 mail.baikalelectronics.com 92B9116A3", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=baikalelectronics.ru; s=mail; t=1654849137;\n bh=tREhIctPbG6TtUn0LROFIgA2rsy12HWrOrKl/nPL4HE=;\n h=From:To:CC:Subject:Date:In-Reply-To:References:From;\n b=j9QBmc0bJC63Cnmvz3kFxCp4SCCxBJ8yKYg9YgN+jrYc0qVdy1jFJAANt1+fCprGy\n xIro6DXa/GvPcKXBKc6PHwOmM/MNZrrNWA2mqRYRxdLTrXRsmhjQ8sZmfBvY5TrD7x\n qxhGN3Q3EGsF050bz7OJNDyMYsMap0sTvTnWVuxU=", "From": "Serge Semin <Sergey.Semin@baikalelectronics.ru>", "To": "Damien Le Moal <damien.lemoal@opensource.wdc.com>,\n Hans de Goede <hdegoede@redhat.com>,\n Jens Axboe <axboe@kernel.dk>, Hannes Reinecke <hare@suse.de>,\n Rob Herring <robh+dt@kernel.org>,\n Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,\n Linus Walleij <linus.walleij@linaro.org>", "CC": "Serge Semin <Sergey.Semin@baikalelectronics.ru>,\n Serge Semin <fancer.lancer@gmail.com>,\n Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>,\n Pavel Parkhomenko <Pavel.Parkhomenko@baikalelectronics.ru>,\n <linux-ide@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n <devicetree@vger.kernel.org>", "Subject": "[PATCH v4 02/23] dt-bindings: ata: ahci-platform: Detach common AHCI\n bindings", "Date": "Fri, 10 Jun 2022 11:17:40 +0300", "Message-ID": "<20220610081801.11854-3-Sergey.Semin@baikalelectronics.ru>", "In-Reply-To": "<20220610081801.11854-1-Sergey.Semin@baikalelectronics.ru>", "References": "<20220610081801.11854-1-Sergey.Semin@baikalelectronics.ru>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "MAIL.baikal.int (192.168.51.25) To mail (192.168.51.25)", "X-Spam-Status": "No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_PASS,SPF_PASS,\n T_SCC_BODY_TEXT_LINE,URIBL_BLOCKED autolearn=ham autolearn_force=no\n version=3.4.6", "X-Spam-Checker-Version": "SpamAssassin 3.4.6 (2021-04-09) on\n lindbergh.monkeyblade.net", "Precedence": "bulk", "List-ID": "<linux-ide.vger.kernel.org>", "X-Mailing-List": "linux-ide@vger.kernel.org" }, "content": "In order to create a more sophisticated AHCI controller DT bindings let's\ndivide the already available generic AHCI platform YAML schema into the\nplatform part and a set of the common AHCI properties. The former part\nwill be used to evaluate the AHCI DT nodes mainly compatible with the\ngeneric AHCI controller while the later schema will be used for more\nthorough AHCI DT nodes description. For instance such YAML schemas design\nwill be useful for our DW AHCI SATA controller derivative with four clock\nsources, two reset lines, one system controller reference and specific\nmax Rx/Tx DMA xfers size constraints.\n\nNote the phys and target-supply property requirement is preserved in the\ngeneric AHCI platform bindings because some platforms can lack of the\nexplicitly specified PHYs or target device power regulators.\n\nAlso note the SATA/AHCI ports properties have been moved to the\n$defs-paragraph of the schemas. It's done in order to create the\nextendable properties hierarchy such that particular AHCI-controller\ncould add vendor-specific port properties.\n\nSigned-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>\n\n---\n\nFolks, I don't really see why the phys/target-supply requirement has been\nadded to the generic AHCI DT schema in the first place. Probably just to\nimply some meaning for the sub-nodes definition. Anyway in one of the\nfurther patches I am adding the DW AHCI SATA controller DT bindings which\nwon't require having these properties specified in the sub-nodes, but will\ndescribe additional port-specific properties. That's why I get to keep the\nconstraints in the ahci-platform.yaml schema instead of moving them to the\ncommon schema.\n\nChangelog v2:\n- This is a new patch created after rebasing v1 onto the 5.18-rc3 kernel.\n\nChangelog v3:\n- Replace Jens's email address with Damien's one in the list of the\n schema maintainers. (@Damien)\n\nChangelog v4:\n- Drop clocks, clock-names, resets, reset-names and power-domains\n properties from the common schema. (@Rob)\n- Create sata/ahci-port properties definition hierarchy so the sub-schemas\n would inherit and extend the ports properties of the super-schema. (@Rob)\n---\n .../devicetree/bindings/ata/ahci-common.yaml | 100 ++++++++++++++++++\n .../bindings/ata/ahci-platform.yaml | 72 ++-----------\n .../devicetree/bindings/ata/sata-common.yaml | 8 +-\n 3 files changed, 115 insertions(+), 65 deletions(-)\n create mode 100644 Documentation/devicetree/bindings/ata/ahci-common.yaml", "diff": "diff --git a/Documentation/devicetree/bindings/ata/ahci-common.yaml b/Documentation/devicetree/bindings/ata/ahci-common.yaml\nnew file mode 100644\nindex 000000000000..e89bda3b62cc\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/ata/ahci-common.yaml\n@@ -0,0 +1,100 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/ata/ahci-common.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Common Properties for Serial ATA AHCI controllers\n+\n+maintainers:\n+ - Hans de Goede <hdegoede@redhat.com>\n+ - Damien Le Moal <damien.lemoal@opensource.wdc.com>\n+\n+description:\n+ This document defines device tree properties for a common AHCI SATA\n+ controller implementation. It's hardware interface is supposed to\n+ conform to the technical standard defined by Intel (see Serial ATA\n+ Advanced Host Controller Interface specification for details). The\n+ document doesn't constitute a DT-node binding by itself but merely\n+ defines a set of common properties for the AHCI-compatible devices.\n+\n+select: false\n+\n+allOf:\n+ - $ref: sata-common.yaml#\n+\n+properties:\n+ reg:\n+ description:\n+ Generic AHCI registers space conforming to the Serial ATA AHCI\n+ specification.\n+\n+ reg-names:\n+ description: CSR space IDs\n+\n+ interrupts:\n+ description:\n+ Generic AHCI state change interrupt. Can be implemented either as a\n+ single line attached to the controller or as a set of the signals\n+ indicating the particular port events.\n+\n+ ahci-supply:\n+ description: Power regulator for AHCI controller\n+\n+ target-supply:\n+ description: Power regulator for SATA target device\n+\n+ phy-supply:\n+ description: Power regulator for SATA PHY\n+\n+ phys:\n+ description: Reference to the SATA PHY node\n+ maxItems: 1\n+\n+ phy-names:\n+ maxItems: 1\n+\n+ ports-implemented:\n+ $ref: '/schemas/types.yaml#/definitions/uint32'\n+ description:\n+ Mask that indicates which ports the HBA supports. Useful if PI is not\n+ programmed by the BIOS, which is true for some embedded SoC's.\n+ maximum: 0x1f\n+\n+patternProperties:\n+ \"^sata-port@[0-9a-f]+$\":\n+ $ref: '#/$defs/ahci-port'\n+ description:\n+ It is optionally possible to describe the ports as sub-nodes so\n+ to enable each port independently when dealing with multiple PHYs.\n+\n+required:\n+ - reg\n+ - interrupts\n+\n+additionalProperties: true\n+\n+$defs:\n+ ahci-port:\n+ $ref: /schemas/ata/sata-common.yaml#/$defs/sata-port\n+\n+ properties:\n+ reg:\n+ description: AHCI SATA port identifier\n+ maxItems: 1\n+\n+ phys:\n+ description: Individual AHCI SATA port PHY\n+ maxItems: 1\n+\n+ phy-names:\n+ description: AHCI SATA port PHY ID\n+ maxItems: 1\n+\n+ target-supply:\n+ description: Power regulator for SATA port target device\n+\n+ required:\n+ - reg\n+\n+...\ndiff --git a/Documentation/devicetree/bindings/ata/ahci-platform.yaml b/Documentation/devicetree/bindings/ata/ahci-platform.yaml\nindex 9304e4731965..15be98e0385b 100644\n--- a/Documentation/devicetree/bindings/ata/ahci-platform.yaml\n+++ b/Documentation/devicetree/bindings/ata/ahci-platform.yaml\n@@ -36,8 +36,7 @@ select:\n - compatible\n \n allOf:\n- - $ref: \"sata-common.yaml#\"\n-\n+ - $ref: \"ahci-common.yaml#\"\n \n properties:\n compatible:\n@@ -69,90 +68,37 @@ properties:\n maxItems: 1\n \n clocks:\n- description:\n- Clock IDs array as required by the controller.\n minItems: 1\n maxItems: 3\n \n clock-names:\n- description:\n- Names of clocks corresponding to IDs in the clock property.\n minItems: 1\n maxItems: 3\n \n interrupts:\n maxItems: 1\n \n- ahci-supply:\n- description:\n- regulator for AHCI controller\n-\n- phy-supply:\n- description:\n- regulator for PHY power\n-\n- phys:\n- description:\n- List of all PHYs on this controller\n- maxItems: 1\n-\n- phy-names:\n- description:\n- Name specifier for the PHYs\n- maxItems: 1\n-\n- ports-implemented:\n- $ref: '/schemas/types.yaml#/definitions/uint32'\n- description: |\n- Mask that indicates which ports that the HBA supports\n- are available for software to use. Useful if PORTS_IMPL\n- is not programmed by the BIOS, which is true with\n- some embedded SoCs.\n- maximum: 0x1f\n-\n power-domains:\n maxItems: 1\n \n resets:\n maxItems: 1\n \n- target-supply:\n- description:\n- regulator for SATA target power\n-\n-required:\n- - compatible\n- - reg\n- - interrupts\n-\n patternProperties:\n \"^sata-port@[0-9a-f]+$\":\n- type: object\n- additionalProperties: false\n- description:\n- Subnode with configuration of the Ports.\n-\n- properties:\n- reg:\n- maxItems: 1\n-\n- phys:\n- maxItems: 1\n-\n- phy-names:\n- maxItems: 1\n-\n- target-supply:\n- description:\n- regulator for SATA target power\n-\n- required:\n- - reg\n+ $ref: /schemas/ata/ahci-common.yaml#/$defs/ahci-port\n \n anyOf:\n - required: [ phys ]\n - required: [ target-supply ]\n \n+ unevaluatedProperties: false\n+\n+required:\n+ - compatible\n+ - reg\n+ - interrupts\n+\n unevaluatedProperties: false\n \n examples:\ndiff --git a/Documentation/devicetree/bindings/ata/sata-common.yaml b/Documentation/devicetree/bindings/ata/sata-common.yaml\nindex cb88d3e25e73..5a31a902618d 100644\n--- a/Documentation/devicetree/bindings/ata/sata-common.yaml\n+++ b/Documentation/devicetree/bindings/ata/sata-common.yaml\n@@ -35,9 +35,15 @@ properties:\n \n patternProperties:\n \"^sata-port@[0-9a-e]$\":\n+ $ref: '#/$defs/sata-port'\n description: |\n DT nodes for ports connected on the SATA host. The SATA port\n nodes will be named \"sata-port\".\n+\n+additionalProperties: true\n+\n+$defs:\n+ sata-port:\n type: object\n \n properties:\n@@ -49,6 +55,4 @@ patternProperties:\n multiplier making it possible to connect up to 15 disks to a single\n SATA port.\n \n-additionalProperties: true\n-\n ...\n", "prefixes": [ "v4", "02/23" ] }