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GET /api/patches/1635774/?format=api
{ "id": 1635774, "url": "http://patchwork.ozlabs.org/api/patches/1635774/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20220526085227.1862-1-pali@kernel.org/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20220526085227.1862-1-pali@kernel.org>", "list_archive_url": null, "date": "2022-05-26T08:52:27", "name": "[v3] board: freescale: p1_p2_rdb_pc: Move boot reset macros to p1_p2_bootsrc.h", "commit_ref": "676f682bad2ed93a20fcf35dd5af5163d11c126f", "pull_url": null, "state": "accepted", "archived": false, "hash": "259dcb5d29b3c08f662751e8b7aafb88766a03cb", "submitter": { "id": 78810, "url": "http://patchwork.ozlabs.org/api/people/78810/?format=api", "name": "Pali Rohár", "email": "pali@kernel.org" }, "delegate": { "id": 55230, "url": "http://patchwork.ozlabs.org/api/users/55230/?format=api", "username": "freenix", "first_name": "Peng", "last_name": "Fan", "email": "van.freenix@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20220526085227.1862-1-pali@kernel.org/mbox/", "series": [ { "id": 302101, "url": "http://patchwork.ozlabs.org/api/series/302101/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=302101", "date": "2022-05-26T08:52:27", "name": "[v3] board: freescale: p1_p2_rdb_pc: Move boot reset macros to p1_p2_bootsrc.h", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/302101/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1635774/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1635774/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "bilbo.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=UY2SX780;\n\tdkim-atps=neutral", "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=kernel.org", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.b=\"UY2SX780\";\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=kernel.org", "phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest\n SHA256)\n\t(No client certificate requested)\n\tby bilbo.ozlabs.org (Postfix) with ESMTPS id 4L81tY0P5sz9s75\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 26 May 2022 18:53:23 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 6B53483E68;\n\tThu, 26 May 2022 10:53:15 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id 1CB66842C4; Thu, 26 May 2022 10:53:14 +0200 (CEST)", "from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n bits)) (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 1144F830E5\n for <u-boot@lists.denx.de>; Thu, 26 May 2022 10:53:11 +0200 (CEST)", "from smtp.kernel.org (relay.kernel.org [52.25.139.140])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n (No client certificate requested)\n by dfw.source.kernel.org (Postfix) with ESMTPS id CA7AD61B30;\n Thu, 26 May 2022 08:53:08 +0000 (UTC)", "by smtp.kernel.org (Postfix) with ESMTPSA id B1606C385A9;\n Thu, 26 May 2022 08:53:07 +0000 (UTC)", "by pali.im (Postfix)\n id 073C04F8; Thu, 26 May 2022 10:53:05 +0200 (CEST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.8 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,\n DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,\n SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no\n version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n s=k20201202; t=1653555188;\n bh=qlSRKG5sCL1UuyJhMZ8elowoDTUA4vyjUbcMAwOFthE=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=UY2SX78042BQqV5xs7HE7TNTulV/C+5Zf+/QWiZC4QGr2+XhznNbBp9uXiooNYtCm\n E5wC4bOLRGixo3mOXrxeKs9LvGjqkc7mOy32PJRzhr4Lv6k84IfU5BKQaDV0Ewev2s\n tJMEjHdsg9gNiEXlAnG14fhfMdwVboY/Yf1oJpin6lnjrctDpeHpnbC+tL1O830eo7\n xSAL/1fR9UytoSWGE2VLxWB/B4uITDE74hTA2Tv6uHn8U6oxqRDndUkkZRFsK8sMTd\n oDDrytaWQPeL0cUFzA4KMD/kN9X/9eDfOia+i7v6p19wAnpAmDMnTZj4Up92FA3qX4\n LN7tMP4G1ALEQ==", "From": "=?utf-8?q?Pali_Roh=C3=A1r?= <pali@kernel.org>", "To": "\"Priyanka Jain (OSS)\" <priyanka.jain@oss.nxp.com>", "Cc": "Qiang Zhao <qiang.zhao@nxp.com>, Shengzhou Liu <shengzhou.liu@nxp.com>,\n Sinan Akman <sinan@writeme.com>,\n \"u-boot@lists.denx.de\" <u-boot@lists.denx.de>", "Subject": "[PATCH v3] board: freescale: p1_p2_rdb_pc: Move boot reset macros to\n p1_p2_bootsrc.h", "Date": "Thu, 26 May 2022 10:52:27 +0200", "Message-Id": "<20220526085227.1862-1-pali@kernel.org>", "X-Mailer": "git-send-email 2.20.1", "In-Reply-To": "<20220526083206.wdl4gxorlpwbuk5m@pali>", "References": "<20220526083206.wdl4gxorlpwbuk5m@pali>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.5 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Code for changing boot source is platform generic and can be used by any\nP1* and P2* compatible RDB board. Not only by boards which use config\nheader file p1_p2_rdb_pc.h.\n\nSo move this code from p1_p2_rdb_pc.h to p1_p2_bootsrc.h and cleanup macros\nfor generating boot source env variables in CONFIG_EXTRA_ENV_SETTINGS.\n\nThis allows to use code for resetting board and rebooting to other boot\nsource also by other boards in future.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\n---\nChanges in v3:\n* Fix copyright header\nChanges in v2:\n* Fix commit message\n* Move macros to file p1_p2_bootsrc.h\n* Rewrite macros even more to be more generic and use them without custom\n macros in p1_p2_rdb_pc.h\n---\n include/configs/p1_p2_bootsrc.h | 59 +++++++++++++++++++++++++++++++++\n include/configs/p1_p2_rdb_pc.h | 41 +++++------------------\n 2 files changed, 68 insertions(+), 32 deletions(-)\n create mode 100644 include/configs/p1_p2_bootsrc.h", "diff": "diff --git a/include/configs/p1_p2_bootsrc.h b/include/configs/p1_p2_bootsrc.h\nnew file mode 100644\nindex 000000000000..13e4fdb4fdf6\n--- /dev/null\n+++ b/include/configs/p1_p2_bootsrc.h\n@@ -0,0 +1,59 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * Copyright 2010-2011 Freescale Semiconductor, Inc.\n+ * Copyright 2020 NXP\n+ * Copyright 2022 Pali Rohár <pali@kernel.org>\n+ */\n+\n+#include <linux/stringify.h>\n+\n+#if !defined(CONFIG_SYS_SPD_BUS_NUM) || !defined(CONFIG_SYS_I2C_PCA9557_ADDR)\n+#error \"CONFIG_SYS_SPD_BUS_NUM and CONFIG_SYS_I2C_PCA9557_ADDR are required\"\n+#endif\n+\n+#define __BOOTSRC_CMD(src, msk) i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 src 1; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 msk 1\n+\n+#define __VAR_CMD(var, cmd) __stringify(var=cmd\\0)\n+#define __VAR_CMD_RST(var, cmd) __VAR_CMD(var, cmd; reset)\n+\n+#ifdef __SW_NOR_BANK_LO\n+#define MAP_NOR_LO_CMD(var, ...) __VAR_CMD(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_NOR_BANK_LO, __SW_NOR_BANK_MASK))\n+#else\n+#define MAP_NOR_LO_CMD(var, ...) \"\"\n+#endif\n+\n+#ifdef __SW_NOR_BANK_UP\n+#define MAP_NOR_UP_CMD(var, ...) __VAR_CMD(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_NOR_BANK_UP, __SW_NOR_BANK_MASK))\n+#else\n+#define MAP_NOR_UP_CMD(var, ...) \"\"\n+#endif\n+\n+#ifdef __SW_BOOT_NOR\n+#define RST_NOR_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NOR, __SW_BOOT_MASK))\n+#else\n+#define RST_NOR_CMD(var, ...) \"\"\n+#endif\n+\n+#ifdef __SW_BOOT_SPI\n+#define RST_SPI_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_SPI, __SW_BOOT_MASK))\n+#else\n+#define RST_SPI_CMD(var, ...) \"\"\n+#endif\n+\n+#ifdef __SW_BOOT_SD\n+#define RST_SD_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_SD, __SW_BOOT_MASK))\n+#else\n+#define RST_SD_CMD(var, ...) \"\"\n+#endif\n+\n+#ifdef __SW_BOOT_NAND\n+#define RST_NAND_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_NAND, __SW_BOOT_MASK))\n+#else\n+#define RST_NAND_CMD(var, ...) \"\"\n+#endif\n+\n+#ifdef __SW_BOOT_PCIE\n+#define RST_PCIE_CMD(var, ...) __VAR_CMD_RST(var, __VA_ARGS__ __BOOTSRC_CMD(__SW_BOOT_PCIE, __SW_BOOT_MASK))\n+#else\n+#define RST_PCIE_CMD(var, ...) \"\"\n+#endif\ndiff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h\nindex f6ecf2a7a8b8..0d655818a924 100644\n--- a/include/configs/p1_p2_rdb_pc.h\n+++ b/include/configs/p1_p2_rdb_pc.h\n@@ -542,31 +542,7 @@\n #define CONFIG_ROOTPATH\t\t\"/opt/nfsroot\"\n #define CONFIG_UBOOTPATH\tu-boot.bin /* U-Boot image on TFTP server */\n \n-#ifdef __SW_BOOT_NOR\n-#define __NOR_RST_CMD\t\\\n-norboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NOR 1; \\\n-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset\n-#endif\n-#ifdef __SW_BOOT_SPI\n-#define __SPI_RST_CMD\t\\\n-spiboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SPI 1; \\\n-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset\n-#endif\n-#ifdef __SW_BOOT_SD\n-#define __SD_RST_CMD\t\\\n-sdboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SD 1; \\\n-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset\n-#endif\n-#ifdef __SW_BOOT_NAND\n-#define __NAND_RST_CMD\t\\\n-nandboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NAND 1; \\\n-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset\n-#endif\n-#ifdef __SW_BOOT_PCIE\n-#define __PCIE_RST_CMD\t\\\n-pciboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_PCIE 1; \\\n-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset\n-#endif\n+#include \"p1_p2_bootsrc.h\"\n \n #define\tCONFIG_EXTRA_ENV_SETTINGS\t\\\n \"netdev=eth0\\0\"\t\\\n@@ -593,13 +569,14 @@ i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset\n \"nandfdtaddr=80000\\0\"\t\t\\\n \"ramdisk_size=120000\\0\"\t\\\n __VSCFW_ADDR\t\\\n-\"map_lowernorbank=i2c dev \"__stringify(CONFIG_SYS_SPD_BUS_NUM)\"; i2c mw \"__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)\" 1 \"__stringify(__SW_NOR_BANK_LO)\" 1; i2c mw \"__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)\" 3 \"__stringify(__SW_NOR_BANK_MASK)\" 1\\0\" \\\n-\"map_uppernorbank=i2c dev \"__stringify(CONFIG_SYS_SPD_BUS_NUM)\"; i2c mw \"__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)\" 1 \"__stringify(__SW_NOR_BANK_UP)\" 1; i2c mw \"__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)\" 3 \"__stringify(__SW_NOR_BANK_MASK)\" 1\\0\" \\\n-__stringify(__NOR_RST_CMD)\"\\0\" \\\n-__stringify(__SPI_RST_CMD)\"\\0\" \\\n-__stringify(__SD_RST_CMD)\"\\0\" \\\n-__stringify(__NAND_RST_CMD)\"\\0\" \\\n-__stringify(__PCIE_RST_CMD)\"\\0\"\n+MAP_NOR_LO_CMD(map_lowernorbank) \\\n+MAP_NOR_UP_CMD(map_uppernorbank) \\\n+RST_NOR_CMD(norboot) \\\n+RST_SPI_CMD(spiboot) \\\n+RST_SD_CMD(sdboot) \\\n+RST_NAND_CMD(nandboot) \\\n+RST_PCIE_CMD(pciboot) \\\n+\"\"\n \n #define CONFIG_USB_FAT_BOOT\t\\\n \"setenv bootargs root=/dev/ram rw \"\t\\\n", "prefixes": [ "v3" ] }