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GET /api/patches/1629719/?format=api
{ "id": 1629719, "url": "http://patchwork.ozlabs.org/api/patches/1629719/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20220511185731.3000-1-pali@kernel.org/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20220511185731.3000-1-pali@kernel.org>", "list_archive_url": null, "date": "2022-05-11T18:57:31", "name": "[v2] powerpc: mpc85xx: Add support for generating QorIQ pre-PBL eSDHC boot sector", "commit_ref": "786d9f1a82eaf09f13e6b4348b555f95360a7721", "pull_url": null, "state": "accepted", "archived": false, "hash": "b3dce7311aa148a49e23b2b1eb453d44895a9494", "submitter": { "id": 78810, "url": "http://patchwork.ozlabs.org/api/people/78810/?format=api", "name": "Pali Rohár", "email": "pali@kernel.org" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20220511185731.3000-1-pali@kernel.org/mbox/", "series": [ { "id": 299698, "url": "http://patchwork.ozlabs.org/api/series/299698/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=299698", "date": "2022-05-11T18:57:31", "name": "[v2] powerpc: mpc85xx: Add support for generating QorIQ pre-PBL eSDHC boot sector", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/299698/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1629719/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1629719/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "bilbo.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=aoQU/9lq;\n\tdkim-atps=neutral", "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=kernel.org", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.b=\"aoQU/9lq\";\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=kernel.org", "phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (2048 bits))\n\t(No client certificate requested)\n\tby bilbo.ozlabs.org (Postfix) with ESMTPS id 4Kz51Q27VRz9sFk\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 12 May 2022 05:43:22 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id DEB3A8435E;\n\tWed, 11 May 2022 21:43:16 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id E2F1080029; Wed, 11 May 2022 21:43:14 +0200 (CEST)", "from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n bits)) (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id F38BE8393F\n for <u-boot@lists.denx.de>; Wed, 11 May 2022 21:43:10 +0200 (CEST)", "from smtp.kernel.org (relay.kernel.org [52.25.139.140])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n (No client certificate requested)\n by dfw.source.kernel.org (Postfix) with ESMTPS id 948CC60F78;\n Wed, 11 May 2022 18:58:13 +0000 (UTC)", "by smtp.kernel.org (Postfix) with ESMTPSA id AB240C340EE;\n Wed, 11 May 2022 18:58:12 +0000 (UTC)", "by pali.im (Postfix)\n id 0F79921A6; Wed, 11 May 2022 20:58:10 +0200 (CEST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,\n DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,\n SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no\n version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n s=k20201202; t=1652295493;\n bh=nN7tpEwSLiVeBVog6SqeJmWb8EPcOVbcafo7Y5o5bwM=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=aoQU/9lqndU+qgop2DUCp/dy5cQQyUZI410/onC9fRWPOBOb6MucnYg9rSo+j2Iq/\n QzYwDftsnUeyIQ8QqQqzCsrR+k9V2KABZb16+Co2zL3rkmi6NzgzG838j8fTwf2u/w\n BtL506TZJSdyVz9n1g6tf0NIGiI+60d9vBHOWXvyuaYdNoxlLtgavclRtGFdZHAqd6\n TNq23pZELFSaFZ7JS9v5Jk4o2pZp6SxMFUxx0boLzGmgVVRmeSyDuxCFP9nn5SHuVL\n JtGpp5o1dUgtDLkaLcY4AUtB+yOWbTzw6DACnP9Xd7uK5eQ0S+EdyaJw5/9h0Fj7h8\n CY/QhuofSxUKA==", "From": "=?utf-8?q?Pali_Roh=C3=A1r?= <pali@kernel.org>", "To": "Priyanka Jain <priyanka.jain@nxp.com>, Bin Meng <bmeng.cn@gmail.com>,\n Wolfgang Denk <wd@denx.de>, Sinan Akman <sinan@writeme.com>", "Cc": "u-boot@lists.denx.de", "Subject": "[PATCH v2] powerpc: mpc85xx: Add support for generating QorIQ pre-PBL\n eSDHC boot sector", "Date": "Wed, 11 May 2022 20:57:31 +0200", "Message-Id": "<20220511185731.3000-1-pali@kernel.org>", "X-Mailer": "git-send-email 2.20.1", "In-Reply-To": "<20220405134032.704-2-pali@kernel.org>", "References": "<20220405134032.704-2-pali@kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.5 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "QorIQ U-Boot binary for SD card booting compiled during build process\n(either u-boot.bin or u-boot-with-spl.bin) cannot be directly loaded by\nQorIQ pre-PBL BootROM. Compiled U-Boot binary first needs to be processed\nby Freescale boot_format tool as described in doc/README.mpc85xx-sd-spi-boot\n\nBootROM requires that image on SD card must contain special boot sector.\nImplement support for generating this special boot sector directly in\nU-Boot start code. Boot sector needs to be at the beginning of the image,\nso when compiling only proper U-Boot without SPL then it needs to be in\nproper U-Boot. When compiling SPL with proper U-Boot then it needs to be\nonly in SPL.\n\nSupport can be enabled by a new config option FSL_PREPBL_ESDHC_BOOT_SECTOR.\nVia other two additional options FSL_PREPBL_ESDHC_BOOT_SECTOR_START and\nFSL_PREPBL_ESDHC_BOOT_SECTOR_DATA it is possible to tune how final U-Boot\nimage could be stored on the SD card.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\n\n---\nChanges in v2:\n* Replace addresses in start.S by named constants\n* Move bootsect from .text section to separate data section .bootsect which\n would be before TEXT_BASE. This boot sector is not used by the U-Boot nor\n SPL and it even is not loaded by BootROM into larget area, so it does not\n have to occupe data in TEXT_BASE. With this change U-Boot and SPL stay on\n the same addresses as before this change.\n---\n arch/powerpc/cpu/mpc85xx/Kconfig | 53 ++++++++++++++\n arch/powerpc/cpu/mpc85xx/start.S | 94 +++++++++++++++++++++++++\n arch/powerpc/cpu/mpc85xx/u-boot-spl.lds | 8 +++\n arch/powerpc/cpu/mpc85xx/u-boot.lds | 8 +++\n 4 files changed, 163 insertions(+)", "diff": "diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig\nindex c308447d493a..6f8b7593d250 100644\n--- a/arch/powerpc/cpu/mpc85xx/Kconfig\n+++ b/arch/powerpc/cpu/mpc85xx/Kconfig\n@@ -12,6 +12,59 @@ config CMD_ERRATA\n \t This enables the 'errata' command which displays a list of errata\n \t work-arounds which are enabled for the current board.\n \n+config FSL_PREPBL_ESDHC_BOOT_SECTOR\n+\tbool \"Generate QorIQ pre-PBL eSDHC boot sector\"\n+\tdepends on MPC85xx\n+\tdepends on SYS_EXTRA_OPTIONS = SDCARD\n+\thelp\n+\t With this option final image would have prepended QorIQ pre-PBL eSDHC\n+\t boot sector suitable for SD card images. This boot sector instruct\n+\t BootROM to configure L2 SRAM and eSDHC then load image from SD card\n+\t into L2 SRAM and finally jump to image entry point.\n+\n+\t This is alternative to Freescale boot_format tool, but works only for\n+\t SD card images and only for L2 SRAM booting. U-Boot images generated\n+\t with this option should not passed to boot_format tool.\n+\n+\t For other configuration like booting from eSPI or configuring SDRAM\n+\t please use Freescale boot_format tool without this option. See file\n+\t doc/README.mpc85xx-sd-spi-boot\n+\n+config FSL_PREPBL_ESDHC_BOOT_SECTOR_START\n+\tint \"QorIQ pre-PBL eSDHC boot sector start offset\"\n+\tdepends on FSL_PREPBL_ESDHC_BOOT_SECTOR\n+\trange 0 23\n+\tdefault 0\n+\thelp\n+\t QorIQ pre-PBL eSDHC boot sector may be located on one of the first\n+\t 24 SD card sectors. Select SD card sector on which final U-Boot\n+\t image (with this boot sector) would be installed.\n+\n+\t By default first SD card sector (0) is used. But this may be changed\n+\t to allow installing U-Boot image on some partition (with fixed start\n+\t sector).\n+\n+\t Please note that any sector on SD card prior this boot sector must\n+\t not contain ASCII \"BOOT\" bytes at sector offset 0x40.\n+\n+config FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA\n+\tint \"Relative data sector for QorIQ pre-PBL eSDHC boot sector\"\n+\tdepends on FSL_PREPBL_ESDHC_BOOT_SECTOR\n+\tdefault 1\n+\trange 1 8388607\n+\thelp\n+\t Select data sector from the beginning of QorIQ pre-PBL eSDHC boot\n+\t sector on which would be stored raw U-Boot image.\n+\n+\t By default is it second sector (1) which is the first available free\n+\t sector (on the first sector is stored boot sector). It can be any\n+\t sector number which offset in bytes can be expressed by 32-bit number.\n+\n+\t In case this final U-Boot image (with this boot sector) is put on\n+\t the FAT32 partition into reserved boot area, this data sector needs\n+\t to be at least 2 (third sector) because FAT32 use second sector for\n+\t its data.\n+\n choice\n \tprompt \"Target select\"\n \toptional\ndiff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S\nindex 796a58b929ec..3006d569b387 100644\n--- a/arch/powerpc/cpu/mpc85xx/start.S\n+++ b/arch/powerpc/cpu/mpc85xx/start.S\n@@ -56,6 +56,100 @@\n \tGOT_ENTRY(__bss_start)\n \tEND_GOT\n \n+#ifdef CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR\n+#if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)\n+\n+/* Maximal size of the image */\n+#ifdef CONFIG_SPL_BUILD\n+#define MAX_IMAGE_SIZE (CONFIG_SPL_MAX_SIZE - (CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512))\n+#else\n+#define MAX_IMAGE_SIZE CONFIG_SYS_L2_SIZE\n+#endif\n+\n+#if defined(CONFIG_SPL_BUILD) && CONFIG_SPL_MAX_SIZE < CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512\n+#error \"CONFIG_SPL_MAX_SIZE is too small for CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA\"\n+#endif\n+\n+#if MAX_IMAGE_SIZE > CONFIG_SYS_L2_SIZE\n+#error \"Image is too big\"\n+#endif\n+\n+#define DIV_ROUND_UP(a, b) (((a) + (b) - 1) / (b))\n+#define ALIGN(x, a) (DIV_ROUND_UP(x, a) * (a))\n+\n+/* Definitions from C header file asm/immap_85xx.h */\n+\n+#define CONFIG_SYS_MPC85xx_L2_OFFSET\t\t0x20000\n+\n+#define MPC85xx_L2CTL\t\t\t\t0x000\n+#define MPC85xx_L2CTL_L2E\t\t\t0x80000000\n+#define MPC85xx_L2CTL_L2SRAM_ENTIRE\t\t0x00010000\n+\n+#define MPC85xx_L2SRBAR0\t\t\t0x100\n+\n+#define MPC85xx_L2ERRDIS\t\t\t0xe44\n+#define MPC85xx_L2ERRDIS_MBECC\t\t\t0x00000008\n+#define MPC85xx_L2ERRDIS_SBECC\t\t\t0x00000004\n+\n+/* Definitions from C header file fsl_esdhc.h */\n+\n+#define ESDHCCTL\t\t\t\t0x0002e40c\n+#define ESDHCCTL_SNOOP\t\t\t\t0x00000040\n+\n+/*\n+ * QorIQ pre-PBL eSDHC boot sector:\n+ * Instruct BootROM to configure L2 SRAM and eSDHC then load image\n+ * from SD card into L2 SRAM and finally jump to image entry point.\n+ */\n+\t.section .bootsect, \"a\"\n+\t.globl bootsect\n+\n+bootsect:\n+\t.org 0x40 /* BOOT signature */\n+\t.ascii \"BOOT\"\n+\n+\t.org 0x48 /* Number of bytes to be copied, must be multiple of block size (512) */\n+\t.long ALIGN(MAX_IMAGE_SIZE, 512)\n+\n+\t.org 0x50 /* Source address from the beginning of boot sector in byte address format, must be multiple of block size (512) */\n+\t.long (CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_START + CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA) * 512\n+\n+\t.org 0x58 /* Target address in the system's local memory address space */\n+\t.long CONFIG_SYS_MONITOR_BASE\n+\n+\t.org 0x60 /* Execution starting address */\n+\t.long _start\n+\n+\t.org 0x68 /* Number of configuration data pairs */\n+\t.long DIV_ROUND_UP(.Lconf_pair_end - .Lconf_pair_start, 8)\n+\n+\t.org 0x80 /* Start of configuration */\n+\t.Lconf_pair_start:\n+\n+\t.long CONFIG_SYS_CCSRBAR_DEFAULT + CONFIG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2SRBAR0 /* Address: L2 memory-mapped SRAM base addr 0 */\n+\t.long CONFIG_SYS_INIT_L2_ADDR\n+\n+\t.long CONFIG_SYS_CCSRBAR_DEFAULT + CONFIG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2ERRDIS /* Address: L2 cache error disable */\n+\t.long MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC\n+\n+\t.long CONFIG_SYS_CCSRBAR_DEFAULT + CONFIG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2CTL /* Address: L2 configuration 0 */\n+\t.long MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE\n+\n+\t.long CONFIG_SYS_CCSRBAR_DEFAULT + ESDHCCTL /* Address: eSDHC DMA control */\n+\t.long ESDHCCTL_SNOOP\n+\n+\t.long 0x40000001 /* Command: Delay in 8 CCB clocks */\n+\t.long 256\n+\n+\t.long 0x80000001 /* End of configuration */\n+\t.Lconf_pair_end:\n+\n+\t.org 0x1b8 /* Reserved for MBR/DBR */\n+\t.org 0x200 /* End of boot sector */\n+\n+#endif\n+#endif\n+\n /*\n * e500 Startup -- after reset only the last 4KB of the effective\n * address space is mapped in the MMU L2 TLB1 Entry0. The .bootpg\ndiff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds\nindex 6fd0da9f39b1..6b3c84a8d5c4 100644\n--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds\n+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds\n@@ -12,6 +12,14 @@ OUTPUT_ARCH(powerpc)\n \n SECTIONS\n {\n+/* Optional boot sector */\n+#if defined(CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR)\n+\t.bootsect IMAGE_TEXT_BASE - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512 : {\n+\t\tKEEP(*(.bootsect))\n+\t\t. = CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512;\n+\t}\n+#endif\n+\n \t. = IMAGE_TEXT_BASE;\n \t.text : {\n /* For ifc, elbc, esdhc, espi, all need the SPL without section .resetvec */\ndiff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds\nindex 9f422810bb5d..cb32aeefdc79 100644\n--- a/arch/powerpc/cpu/mpc85xx/u-boot.lds\n+++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds\n@@ -16,6 +16,14 @@ ENTRY(_start)\n \n SECTIONS\n {\n+ /* Optional boot sector */\n+#if defined(CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR) && !defined(CONFIG_SPL)\n+ .bootsect CONFIG_SYS_TEXT_BASE - CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512 : {\n+ KEEP(arch/powerpc/cpu/mpc85xx/start.o (.bootsect))\n+ . = CONFIG_FSL_PREPBL_ESDHC_BOOT_SECTOR_DATA * 512;\n+ }\n+#endif\n+\n /* Read-only sections, merged into text segment: */\n .text :\n {\n", "prefixes": [ "v2" ] }