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GET /api/patches/1627241/?format=api
{ "id": 1627241, "url": "http://patchwork.ozlabs.org/api/patches/1627241/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20220505184938.351866-31-danielhb413@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20220505184938.351866-31-danielhb413@gmail.com>", "list_archive_url": null, "date": "2022-05-05T18:49:38", "name": "[PULL,30/30] target/ppc: Change MSR_* to follow POWER ISA numbering convention", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "1f5d3258f66274fec6f57e54e0ccf9542df61728", "submitter": { "id": 74265, "url": "http://patchwork.ozlabs.org/api/people/74265/?format=api", "name": "Daniel Henrique Barboza", "email": "danielhb413@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20220505184938.351866-31-danielhb413@gmail.com/mbox/", "series": [ { "id": 298671, "url": "http://patchwork.ozlabs.org/api/series/298671/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=298671", "date": "2022-05-05T18:49:09", "name": "[PULL,01/30] target/ppc: initialize 'val' union in kvm_get_one_spr()", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/298671/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1627241/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1627241/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ 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"Thu, 5 May 2022 15:49:38 -0300", "Message-Id": "<20220505184938.351866-31-danielhb413@gmail.com>", "X-Mailer": "git-send-email 2.32.0", "In-Reply-To": "<20220505184938.351866-1-danielhb413@gmail.com>", "References": "<20220505184938.351866-1-danielhb413@gmail.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::c29;\n envelope-from=danielhb413@gmail.com; helo=mail-oo1-xc29.google.com", "X-Spam_score_int": "-18", "X-Spam_score": "-1.9", "X-Spam_bar": "-", "X-Spam_report": "(-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001,\n T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Víctor Colombo <victor.colombo@eldorado.org.br>\n\nToday we have the issue where MSR_* values are the 'inverted order'\nbit numbers from what the ISA specifies. e.g. MSR_LE is bit 63 but\nis defined as 0 in QEMU.\n\nAdd a macro to be used to convert from QEMU order to ISA order.\n\nThis solution requires less changes than to use the already defined\nPPC_BIT macro, which would turn MSR_* in masks instead of the numbers\nitself.\n\nSigned-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>\nAcked-by: Richard Henderson <richard.henderson@linaro.org>\nMessage-Id: <20220504210541.115256-23-victor.colombo@eldorado.org.br>\nSigned-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>\n---\n target/ppc/cpu.h | 87 ++++++++++++++++++++++++------------------------\n 1 file changed, 44 insertions(+), 43 deletions(-)", "diff": "diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h\nindex 4577cfcc23..48596cfb25 100644\n--- a/target/ppc/cpu.h\n+++ b/target/ppc/cpu.h\n@@ -38,6 +38,7 @@\n #define PPC_ELF_MACHINE EM_PPC\n #endif\n \n+#define PPC_BIT_NR(bit) (63 - (bit))\n #define PPC_BIT(bit) (0x8000000000000000ULL >> (bit))\n #define PPC_BIT32(bit) (0x80000000 >> (bit))\n #define PPC_BIT8(bit) (0x80 >> (bit))\n@@ -310,49 +311,49 @@ typedef enum {\n \n /*****************************************************************************/\n /* Machine state register bits definition */\n-#define MSR_SF 63 /* Sixty-four-bit mode hflags */\n-#define MSR_TAG 62 /* Tag-active mode (POWERx ?) */\n-#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */\n-#define MSR_HV 60 /* hypervisor state hflags */\n-#define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */\n-#define MSR_TS1 33\n-#define MSR_TM 32 /* Transactional Memory Available (Book3s) */\n-#define MSR_CM 31 /* Computation mode for BookE hflags */\n-#define MSR_ICM 30 /* Interrupt computation mode for BookE */\n-#define MSR_GS 28 /* guest state for BookE */\n-#define MSR_UCLE 26 /* User-mode cache lock enable for BookE */\n-#define MSR_VR 25 /* altivec available x hflags */\n-#define MSR_SPE 25 /* SPE enable for BookE x hflags */\n-#define MSR_VSX 23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */\n-#define MSR_S 22 /* Secure state */\n-#define MSR_KEY 19 /* key bit on 603e */\n-#define MSR_POW 18 /* Power management */\n-#define MSR_WE 18 /* Wait State Enable on 405 */\n-#define MSR_TGPR 17 /* TGPR usage on 602/603 x */\n-#define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */\n-#define MSR_ILE 16 /* Interrupt little-endian mode */\n-#define MSR_EE 15 /* External interrupt enable */\n-#define MSR_PR 14 /* Problem state hflags */\n-#define MSR_FP 13 /* Floating point available hflags */\n-#define MSR_ME 12 /* Machine check interrupt enable */\n-#define MSR_FE0 11 /* Floating point exception mode 0 */\n-#define MSR_SE 10 /* Single-step trace enable x hflags */\n-#define MSR_DWE 10 /* Debug wait enable on 405 x */\n-#define MSR_UBLE 10 /* User BTB lock enable on e500 x */\n-#define MSR_BE 9 /* Branch trace enable x hflags */\n-#define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */\n-#define MSR_FE1 8 /* Floating point exception mode 1 */\n-#define MSR_AL 7 /* AL bit on POWER */\n-#define MSR_EP 6 /* Exception prefix on 601 */\n-#define MSR_IR 5 /* Instruction relocate */\n-#define MSR_DR 4 /* Data relocate */\n-#define MSR_IS 5 /* Instruction address space (BookE) */\n-#define MSR_DS 4 /* Data address space (BookE) */\n-#define MSR_PE 3 /* Protection enable on 403 */\n-#define MSR_PX 2 /* Protection exclusive on 403 x */\n-#define MSR_PMM 2 /* Performance monitor mark on POWER x */\n-#define MSR_RI 1 /* Recoverable interrupt 1 */\n-#define MSR_LE 0 /* Little-endian mode 1 hflags */\n+#define MSR_SF PPC_BIT_NR(0) /* Sixty-four-bit mode hflags */\n+#define MSR_TAG PPC_BIT_NR(1) /* Tag-active mode (POWERx ?) */\n+#define MSR_ISF PPC_BIT_NR(2) /* Sixty-four-bit interrupt mode on 630 */\n+#define MSR_HV PPC_BIT_NR(3) /* hypervisor state hflags */\n+#define MSR_TS0 PPC_BIT_NR(29) /* Transactional state, 2 bits (Book3s) */\n+#define MSR_TS1 PPC_BIT_NR(30)\n+#define MSR_TM PPC_BIT_NR(31) /* Transactional Memory Available (Book3s) */\n+#define MSR_CM PPC_BIT_NR(32) /* Computation mode for BookE hflags */\n+#define MSR_ICM PPC_BIT_NR(33) /* Interrupt computation mode for BookE */\n+#define MSR_GS PPC_BIT_NR(35) /* guest state for BookE */\n+#define MSR_UCLE PPC_BIT_NR(37) /* User-mode cache lock enable for BookE */\n+#define MSR_VR PPC_BIT_NR(38) /* altivec available x hflags */\n+#define MSR_SPE PPC_BIT_NR(38) /* SPE enable for BookE x hflags */\n+#define MSR_VSX PPC_BIT_NR(40) /* Vector Scalar Extension (>= 2.06)x hflags */\n+#define MSR_S PPC_BIT_NR(41) /* Secure state */\n+#define MSR_KEY PPC_BIT_NR(44) /* key bit on 603e */\n+#define MSR_POW PPC_BIT_NR(45) /* Power management */\n+#define MSR_WE PPC_BIT_NR(45) /* Wait State Enable on 405 */\n+#define MSR_TGPR PPC_BIT_NR(46) /* TGPR usage on 602/603 x */\n+#define MSR_CE PPC_BIT_NR(46) /* Critical int. enable on embedded PPC x */\n+#define MSR_ILE PPC_BIT_NR(47) /* Interrupt little-endian mode */\n+#define MSR_EE PPC_BIT_NR(48) /* External interrupt enable */\n+#define MSR_PR PPC_BIT_NR(49) /* Problem state hflags */\n+#define MSR_FP PPC_BIT_NR(50) /* Floating point available hflags */\n+#define MSR_ME PPC_BIT_NR(51) /* Machine check interrupt enable */\n+#define MSR_FE0 PPC_BIT_NR(52) /* Floating point exception mode 0 */\n+#define MSR_SE PPC_BIT_NR(53) /* Single-step trace enable x hflags */\n+#define MSR_DWE PPC_BIT_NR(53) /* Debug wait enable on 405 x */\n+#define MSR_UBLE PPC_BIT_NR(53) /* User BTB lock enable on e500 x */\n+#define MSR_BE PPC_BIT_NR(54) /* Branch trace enable x hflags */\n+#define MSR_DE PPC_BIT_NR(54) /* Debug int. enable on embedded PPC x */\n+#define MSR_FE1 PPC_BIT_NR(55) /* Floating point exception mode 1 */\n+#define MSR_AL PPC_BIT_NR(56) /* AL bit on POWER */\n+#define MSR_EP PPC_BIT_NR(57) /* Exception prefix on 601 */\n+#define MSR_IR PPC_BIT_NR(58) /* Instruction relocate */\n+#define MSR_IS PPC_BIT_NR(58) /* Instruction address space (BookE) */\n+#define MSR_DR PPC_BIT_NR(59) /* Data relocate */\n+#define MSR_DS PPC_BIT_NR(59) /* Data address space (BookE) */\n+#define MSR_PE PPC_BIT_NR(60) /* Protection enable on 403 */\n+#define MSR_PX PPC_BIT_NR(61) /* Protection exclusive on 403 x */\n+#define MSR_PMM PPC_BIT_NR(61) /* Performance monitor mark on POWER x */\n+#define MSR_RI PPC_BIT_NR(62) /* Recoverable interrupt 1 */\n+#define MSR_LE PPC_BIT_NR(63) /* Little-endian mode 1 hflags */\n \n FIELD(MSR, SF, MSR_SF, 1)\n FIELD(MSR, TAG, MSR_TAG, 1)\n", "prefixes": [ "PULL", "30/30" ] }