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GET /api/patches/1627225/?format=api
HTTP 200 OK
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{
    "id": 1627225,
    "url": "http://patchwork.ozlabs.org/api/patches/1627225/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20220505184938.351866-26-danielhb413@gmail.com/",
    "project": {
        "id": 14,
        "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api",
        "name": "QEMU Development",
        "link_name": "qemu-devel",
        "list_id": "qemu-devel.nongnu.org",
        "list_email": "qemu-devel@nongnu.org",
        "web_url": "",
        "scm_url": "",
        "webscm_url": "",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20220505184938.351866-26-danielhb413@gmail.com>",
    "list_archive_url": null,
    "date": "2022-05-05T18:49:33",
    "name": "[PULL,25/30] target/ppc: Remove msr_fe0 and msr_fe1 macros",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "151299915a088c9f7d229fa83600a85c8a744265",
    "submitter": {
        "id": 74265,
        "url": "http://patchwork.ozlabs.org/api/people/74265/?format=api",
        "name": "Daniel Henrique Barboza",
        "email": "danielhb413@gmail.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20220505184938.351866-26-danielhb413@gmail.com/mbox/",
    "series": [
        {
            "id": 298671,
            "url": "http://patchwork.ozlabs.org/api/series/298671/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=298671",
            "date": "2022-05-05T18:49:09",
            "name": "[PULL,01/30] target/ppc: initialize 'val' union in kvm_get_one_spr()",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/298671/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/1627225/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/1627225/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Daniel Henrique Barboza <danielhb413@gmail.com>",
        "To": "qemu-devel@nongnu.org",
        "Cc": "qemu-ppc@nongnu.org, danielhb413@gmail.com, peter.maydell@linaro.org,\n richard.henderson@linaro.org,\n =?utf-8?q?V=C3=ADctor_Colombo?= <victor.colombo@eldorado.org.br>",
        "Subject": "[PULL 25/30] target/ppc: Remove msr_fe0 and msr_fe1 macros",
        "Date": "Thu,  5 May 2022 15:49:33 -0300",
        "Message-Id": "<20220505184938.351866-26-danielhb413@gmail.com>",
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        "In-Reply-To": "<20220505184938.351866-1-danielhb413@gmail.com>",
        "References": "<20220505184938.351866-1-danielhb413@gmail.com>",
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    },
    "content": "From: Víctor Colombo <victor.colombo@eldorado.org.br>\n\nmsr_fe0 and msr_fe1 macros hide the usage of env->msr, which is a bad\nbehavior. Substitute it with FIELD_EX64 calls that explicitly use\nenv->msr as a parameter.\n\nSuggested-by: Richard Henderson <richard.henderson@linaro.org>\nSigned-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nMessage-Id: <20220504210541.115256-18-victor.colombo@eldorado.org.br>\nSigned-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>\n---\n target/ppc/cpu.h         | 11 +++++++++--\n target/ppc/excp_helper.c | 18 ++++++------------\n 2 files changed, 15 insertions(+), 14 deletions(-)",
    "diff": "diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h\nindex 5e804f0373..74a3c01f99 100644\n--- a/target/ppc/cpu.h\n+++ b/target/ppc/cpu.h\n@@ -363,12 +363,21 @@ FIELD(MSR, EE, MSR_EE, 1)\n FIELD(MSR, PR, MSR_PR, 1)\n FIELD(MSR, FP, MSR_FP, 1)\n FIELD(MSR, ME, MSR_ME, 1)\n+FIELD(MSR, FE0, MSR_FE0, 1)\n+FIELD(MSR, FE1, MSR_FE1, 1)\n FIELD(MSR, EP, MSR_EP, 1)\n FIELD(MSR, IR, MSR_IR, 1)\n FIELD(MSR, DR, MSR_DR, 1)\n FIELD(MSR, DS, MSR_DS, 1)\n FIELD(MSR, LE, MSR_LE, 1)\n \n+/*\n+ * FE0 and FE1 bits are not side-by-side\n+ * so we can't combine them using FIELD()\n+ */\n+#define FIELD_EX64_FE(msr) \\\n+    ((FIELD_EX64(msr, MSR, FE0) << 1) | FIELD_EX64(msr, MSR, FE1))\n+\n /* PMU bits */\n #define MMCR0_FC     PPC_BIT(32)         /* Freeze Counters  */\n #define MMCR0_PMAO   PPC_BIT(56)         /* Perf Monitor Alert Ocurred */\n@@ -484,9 +493,7 @@ FIELD(MSR, LE, MSR_LE, 1)\n #else\n #define msr_hv   (0)\n #endif\n-#define msr_fe0  ((env->msr >> MSR_FE0)  & 1)\n #define msr_de   ((env->msr >> MSR_DE)   & 1)\n-#define msr_fe1  ((env->msr >> MSR_FE1)  & 1)\n #define msr_ts   ((env->msr >> MSR_TS1)  & 3)\n \n #define DBCR0_ICMP (1 << 27)\ndiff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c\nindex 30baad0489..aa201c63c6 100644\n--- a/target/ppc/excp_helper.c\n+++ b/target/ppc/excp_helper.c\n@@ -478,8 +478,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)\n     case POWERPC_EXCP_PROGRAM:   /* Program exception                        */\n         switch (env->error_code & ~0xF) {\n         case POWERPC_EXCP_FP:\n-            if ((msr_fe0 == 0 && msr_fe1 == 0) ||\n-                !FIELD_EX64(env->msr, MSR, FP)) {\n+            if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) {\n                 trace_ppc_excp_fp_ignore();\n                 powerpc_reset_excp_state(cpu);\n                 return;\n@@ -616,8 +615,7 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)\n     case POWERPC_EXCP_PROGRAM:   /* Program exception                        */\n         switch (env->error_code & ~0xF) {\n         case POWERPC_EXCP_FP:\n-            if ((msr_fe0 == 0 && msr_fe1 == 0) ||\n-                !FIELD_EX64(env->msr, MSR, FP)) {\n+            if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) {\n                 trace_ppc_excp_fp_ignore();\n                 powerpc_reset_excp_state(cpu);\n                 return;\n@@ -790,8 +788,7 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)\n     case POWERPC_EXCP_PROGRAM:   /* Program exception                        */\n         switch (env->error_code & ~0xF) {\n         case POWERPC_EXCP_FP:\n-            if ((msr_fe0 == 0 && msr_fe1 == 0) ||\n-                !FIELD_EX64(env->msr, MSR, FP)) {\n+            if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) {\n                 trace_ppc_excp_fp_ignore();\n                 powerpc_reset_excp_state(cpu);\n                 return;\n@@ -976,8 +973,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)\n     case POWERPC_EXCP_PROGRAM:   /* Program exception                        */\n         switch (env->error_code & ~0xF) {\n         case POWERPC_EXCP_FP:\n-            if ((msr_fe0 == 0 && msr_fe1 == 0) ||\n-                !FIELD_EX64(env->msr, MSR, FP)) {\n+            if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) {\n                 trace_ppc_excp_fp_ignore();\n                 powerpc_reset_excp_state(cpu);\n                 return;\n@@ -1175,8 +1171,7 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)\n     case POWERPC_EXCP_PROGRAM:   /* Program exception                        */\n         switch (env->error_code & ~0xF) {\n         case POWERPC_EXCP_FP:\n-            if ((msr_fe0 == 0 && msr_fe1 == 0) ||\n-                !FIELD_EX64(env->msr, MSR, FP)) {\n+            if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) {\n                 trace_ppc_excp_fp_ignore();\n                 powerpc_reset_excp_state(cpu);\n                 return;\n@@ -1439,8 +1434,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)\n     case POWERPC_EXCP_PROGRAM:   /* Program exception                        */\n         switch (env->error_code & ~0xF) {\n         case POWERPC_EXCP_FP:\n-            if ((msr_fe0 == 0 && msr_fe1 == 0) ||\n-                !FIELD_EX64(env->msr, MSR, FP)) {\n+            if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) {\n                 trace_ppc_excp_fp_ignore();\n                 powerpc_reset_excp_state(cpu);\n                 return;\n",
    "prefixes": [
        "PULL",
        "25/30"
    ]
}