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GET /api/patches/1627191/?format=api
{ "id": 1627191, "url": "http://patchwork.ozlabs.org/api/patches/1627191/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20220505184938.351866-12-danielhb413@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20220505184938.351866-12-danielhb413@gmail.com>", "list_archive_url": null, "date": "2022-05-05T18:49:19", "name": "[PULL,11/30] target/ppc: Remove msr_pr macro", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "089060eaa2c7d535bb4af1e3db1fc994141232e8", "submitter": { "id": 74265, "url": "http://patchwork.ozlabs.org/api/people/74265/?format=api", "name": "Daniel Henrique Barboza", "email": "danielhb413@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20220505184938.351866-12-danielhb413@gmail.com/mbox/", "series": [ { "id": 298671, "url": "http://patchwork.ozlabs.org/api/series/298671/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=298671", "date": "2022-05-05T18:49:09", "name": "[PULL,01/30] target/ppc: initialize 'val' union in kvm_get_one_spr()", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/298671/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1627191/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1627191/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "bilbo.ozlabs.org;\n\tdkim=pass (2048-bit key;\n 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"X-Mailer": "git-send-email 2.32.0", "In-Reply-To": "<20220505184938.351866-1-danielhb413@gmail.com>", "References": "<20220505184938.351866-1-danielhb413@gmail.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::22c;\n envelope-from=danielhb413@gmail.com; helo=mail-oi1-x22c.google.com", "X-Spam_score_int": "-18", "X-Spam_score": "-1.9", "X-Spam_bar": "-", "X-Spam_report": "(-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001,\n T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Víctor Colombo <victor.colombo@eldorado.org.br>\n\nmsr_pr macro hides the usage of env->msr, which is a bad behavior\nSubstitute it with FIELD_EX64 calls that explicitly use env->msr\nas a parameter.\n\nSuggested-by: Richard Henderson <richard.henderson@linaro.org>\nSigned-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nMessage-Id: <20220504210541.115256-4-victor.colombo@eldorado.org.br>\nSigned-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>\n---\n hw/ppc/pegasos2.c | 2 +-\n hw/ppc/spapr.c | 2 +-\n target/ppc/cpu.h | 4 +++-\n target/ppc/cpu_init.c | 4 ++--\n target/ppc/excp_helper.c | 8 +++++---\n target/ppc/mem_helper.c | 5 +++--\n target/ppc/mmu-radix64.c | 5 +++--\n target/ppc/mmu_common.c | 23 ++++++++++++-----------\n 8 files changed, 30 insertions(+), 23 deletions(-)", "diff": "diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c\nindex 56bf203dfd..9411ca6b16 100644\n--- a/hw/ppc/pegasos2.c\n+++ b/hw/ppc/pegasos2.c\n@@ -461,7 +461,7 @@ static void pegasos2_hypercall(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu)\n /* The TCG path should also be holding the BQL at this point */\n g_assert(qemu_mutex_iothread_locked());\n \n- if (msr_pr) {\n+ if (FIELD_EX64(env->msr, MSR, PR)) {\n qemu_log_mask(LOG_GUEST_ERROR, \"Hypercall made with MSR[PR]=1\\n\");\n env->gpr[3] = H_PRIVILEGE;\n } else if (env->gpr[3] == KVMPPC_H_RTAS) {\ndiff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c\nindex 22569305d2..fe9937e811 100644\n--- a/hw/ppc/spapr.c\n+++ b/hw/ppc/spapr.c\n@@ -1269,7 +1269,7 @@ static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,\n \n g_assert(!vhyp_cpu_in_nested(cpu));\n \n- if (msr_pr) {\n+ if (FIELD_EX64(env->msr, MSR, PR)) {\n hcall_dprintf(\"Hypercall made with MSR[PR]=1\\n\");\n env->gpr[3] = H_PRIVILEGE;\n } else {\ndiff --git a/target/ppc/cpu.h b/target/ppc/cpu.h\nindex 112b456220..8f1dc4cb15 100644\n--- a/target/ppc/cpu.h\n+++ b/target/ppc/cpu.h\n@@ -25,6 +25,7 @@\n #include \"exec/cpu-defs.h\"\n #include \"cpu-qom.h\"\n #include \"qom/object.h\"\n+#include \"hw/registerfields.h\"\n \n #define TCG_GUEST_DEFAULT_MO 0\n \n@@ -353,6 +354,8 @@ typedef enum {\n #define MSR_RI 1 /* Recoverable interrupt 1 */\n #define MSR_LE 0 /* Little-endian mode 1 hflags */\n \n+FIELD(MSR, PR, MSR_PR, 1)\n+\n /* PMU bits */\n #define MMCR0_FC PPC_BIT(32) /* Freeze Counters */\n #define MMCR0_PMAO PPC_BIT(56) /* Perf Monitor Alert Ocurred */\n@@ -474,7 +477,6 @@ typedef enum {\n #define msr_ce ((env->msr >> MSR_CE) & 1)\n #define msr_ile ((env->msr >> MSR_ILE) & 1)\n #define msr_ee ((env->msr >> MSR_EE) & 1)\n-#define msr_pr ((env->msr >> MSR_PR) & 1)\n #define msr_fp ((env->msr >> MSR_FP) & 1)\n #define msr_me ((env->msr >> MSR_ME) & 1)\n #define msr_fe0 ((env->msr >> MSR_FE0) & 1)\ndiff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c\nindex d42e2ba8e0..ac16a64846 100644\n--- a/target/ppc/cpu_init.c\n+++ b/target/ppc/cpu_init.c\n@@ -6303,7 +6303,7 @@ static bool cpu_has_work_POWER9(CPUState *cs)\n if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&\n (env->spr[SPR_LPCR] & LPCR_EEE)) {\n bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);\n- if (heic == 0 || !msr_hv || msr_pr) {\n+ if (!heic || !msr_hv || FIELD_EX64(env->msr, MSR, PR)) {\n return true;\n }\n }\n@@ -6517,7 +6517,7 @@ static bool cpu_has_work_POWER10(CPUState *cs)\n if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&\n (env->spr[SPR_LPCR] & LPCR_EEE)) {\n bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);\n- if (heic == 0 || !msr_hv || msr_pr) {\n+ if (!heic || !msr_hv || FIELD_EX64(env->msr, MSR, PR)) {\n return true;\n }\n }\ndiff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c\nindex d3e2cfcd71..7e8e34ef06 100644\n--- a/target/ppc/excp_helper.c\n+++ b/target/ppc/excp_helper.c\n@@ -1738,7 +1738,8 @@ static void ppc_hw_interrupt(CPUPPCState *env)\n bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);\n bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);\n /* HEIC blocks delivery to the hypervisor */\n- if ((async_deliver && !(heic && msr_hv && !msr_pr)) ||\n+ if ((async_deliver && !(heic && msr_hv &&\n+ !FIELD_EX64(env->msr, MSR, PR))) ||\n (env->has_hv_mode && msr_hv == 0 && !lpes0)) {\n if (books_vhyp_promotes_external_to_hvirt(cpu)) {\n powerpc_excp(cpu, POWERPC_EXCP_HVIRT);\n@@ -1818,7 +1819,8 @@ static void ppc_hw_interrupt(CPUPPCState *env)\n * EBB exception must be taken in problem state and\n * with BESCR_GE set.\n */\n- if (msr_pr == 1 && env->spr[SPR_BESCR] & BESCR_GE) {\n+ if (FIELD_EX64(env->msr, MSR, PR) &&\n+ (env->spr[SPR_BESCR] & BESCR_GE)) {\n env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EBB);\n \n if (env->spr[SPR_BESCR] & BESCR_PMEO) {\n@@ -2094,7 +2096,7 @@ static void do_ebb(CPUPPCState *env, int ebb_excp)\n env->spr[SPR_BESCR] |= BESCR_EEO;\n }\n \n- if (msr_pr == 1) {\n+ if (FIELD_EX64(env->msr, MSR, PR)) {\n powerpc_excp(cpu, ebb_excp);\n } else {\n env->pending_interrupts |= 1 << PPC_INTERRUPT_EBB;\ndiff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c\nindex c4ff8fd632..fba7f84b7a 100644\n--- a/target/ppc/mem_helper.c\n+++ b/target/ppc/mem_helper.c\n@@ -613,10 +613,11 @@ void helper_tbegin(CPUPPCState *env)\n (1ULL << TEXASR_FAILURE_PERSISTENT) |\n (1ULL << TEXASR_NESTING_OVERFLOW) |\n (msr_hv << TEXASR_PRIVILEGE_HV) |\n- (msr_pr << TEXASR_PRIVILEGE_PR) |\n+ (FIELD_EX64(env->msr, MSR, PR) << TEXASR_PRIVILEGE_PR) |\n (1ULL << TEXASR_FAILURE_SUMMARY) |\n (1ULL << TEXASR_TFIAR_EXACT);\n- env->spr[SPR_TFIAR] = env->nip | (msr_hv << 1) | msr_pr;\n+ env->spr[SPR_TFIAR] = env->nip | (msr_hv << 1) |\n+ FIELD_EX64(env->msr, MSR, PR);\n env->spr[SPR_TFHAR] = env->nip + 4;\n env->crf[0] = 0xB; /* 0b1010 = transaction failure */\n }\ndiff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c\nindex 5414fd63c1..e88f51fd34 100644\n--- a/target/ppc/mmu-radix64.c\n+++ b/target/ppc/mmu-radix64.c\n@@ -191,12 +191,13 @@ static bool ppc_radix64_check_prot(PowerPCCPU *cpu, MMUAccessType access_type,\n }\n \n /* Determine permissions allowed by Encoded Access Authority */\n- if (!partition_scoped && (pte & R_PTE_EAA_PRIV) && msr_pr) {\n+ if (!partition_scoped && (pte & R_PTE_EAA_PRIV) &&\n+ FIELD_EX64(env->msr, MSR, PR)) {\n *prot = 0;\n } else if (mmuidx_pr(mmu_idx) || (pte & R_PTE_EAA_PRIV) ||\n partition_scoped) {\n *prot = ppc_radix64_get_prot_eaa(pte);\n- } else { /* !msr_pr && !(pte & R_PTE_EAA_PRIV) && !partition_scoped */\n+ } else { /* !MSR_PR && !(pte & R_PTE_EAA_PRIV) && !partition_scoped */\n *prot = ppc_radix64_get_prot_eaa(pte);\n *prot &= ppc_radix64_get_prot_amr(cpu); /* Least combined permissions */\n }\ndiff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c\nindex e9c5b14c0f..6ef8b1c00d 100644\n--- a/target/ppc/mmu_common.c\n+++ b/target/ppc/mmu_common.c\n@@ -273,8 +273,8 @@ static inline void bat_size_prot(CPUPPCState *env, target_ulong *blp,\n bl = (*BATu & 0x00001FFC) << 15;\n valid = 0;\n prot = 0;\n- if (((msr_pr == 0) && (*BATu & 0x00000002)) ||\n- ((msr_pr != 0) && (*BATu & 0x00000001))) {\n+ if ((!FIELD_EX64(env->msr, MSR, PR) && (*BATu & 0x00000002)) ||\n+ (FIELD_EX64(env->msr, MSR, PR) && (*BATu & 0x00000001))) {\n valid = 1;\n pp = *BATl & 0x00000003;\n if (pp != 0) {\n@@ -368,16 +368,17 @@ static int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,\n PowerPCCPU *cpu = env_archcpu(env);\n hwaddr hash;\n target_ulong vsid;\n- int ds, pr, target_page_bits;\n+ int ds, target_page_bits;\n+ bool pr;\n int ret;\n target_ulong sr, pgidx;\n \n- pr = msr_pr;\n+ pr = FIELD_EX64(env->msr, MSR, PR);\n ctx->eaddr = eaddr;\n \n sr = env->sr[eaddr >> 28];\n- ctx->key = (((sr & 0x20000000) && (pr != 0)) ||\n- ((sr & 0x40000000) && (pr == 0))) ? 1 : 0;\n+ ctx->key = (((sr & 0x20000000) && pr) ||\n+ ((sr & 0x40000000) && !pr)) ? 1 : 0;\n ds = sr & 0x80000000 ? 1 : 0;\n ctx->nx = sr & 0x10000000 ? 1 : 0;\n vsid = sr & 0x00FFFFFF;\n@@ -386,8 +387,8 @@ static int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,\n \"Check segment v=\" TARGET_FMT_lx \" %d \" TARGET_FMT_lx\n \" nip=\" TARGET_FMT_lx \" lr=\" TARGET_FMT_lx\n \" ir=%d dr=%d pr=%d %d t=%d\\n\",\n- eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir,\n- (int)msr_dr, pr != 0 ? 1 : 0,\n+ eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr,\n+ (int)msr_ir, (int)msr_dr, pr ? 1 : 0,\n access_type == MMU_DATA_STORE, type);\n pgidx = (eaddr & ~SEGMENT_MASK_256M) >> target_page_bits;\n hash = vsid ^ pgidx;\n@@ -530,7 +531,7 @@ static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,\n \n ret = -1;\n raddr = (hwaddr)-1ULL;\n- pr = msr_pr;\n+ pr = FIELD_EX64(env->msr, MSR, PR);\n for (i = 0; i < env->nb_tlb; i++) {\n tlb = &env->tlb.tlbe[i];\n if (ppcemb_tlb_check(env, tlb, &raddr, address,\n@@ -618,7 +619,7 @@ static int mmubooke_check_tlb(CPUPPCState *env, ppcemb_tlb_t *tlb,\n \n found_tlb:\n \n- if (msr_pr != 0) {\n+ if (FIELD_EX64(env->msr, MSR, PR)) {\n prot2 = tlb->prot & 0xF;\n } else {\n prot2 = (tlb->prot >> 4) & 0xF;\n@@ -768,7 +769,7 @@ static bool mmubooke206_get_as(CPUPPCState *env,\n return true;\n } else {\n *as_out = msr_ds;\n- *pr_out = msr_pr;\n+ *pr_out = FIELD_EX64(env->msr, MSR, PR);\n return false;\n }\n }\n", "prefixes": [ "PULL", "11/30" ] }