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GET /api/patches/1627175/?format=api
{ "id": 1627175, "url": "http://patchwork.ozlabs.org/api/patches/1627175/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20220505184938.351866-10-danielhb413@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20220505184938.351866-10-danielhb413@gmail.com>", "list_archive_url": null, "date": "2022-05-05T18:49:17", "name": "[PULL,09/30] target/ppc: Remove fpscr_* macros from cpu.h", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c60fd35f9953d1b0304741482c4fc4ca081e7c8b", "submitter": { "id": 74265, "url": "http://patchwork.ozlabs.org/api/people/74265/?format=api", "name": "Daniel Henrique Barboza", "email": "danielhb413@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20220505184938.351866-10-danielhb413@gmail.com/mbox/", "series": [ { "id": 298671, "url": "http://patchwork.ozlabs.org/api/series/298671/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=298671", "date": "2022-05-05T18:49:09", "name": "[PULL,01/30] target/ppc: initialize 'val' union in kvm_get_one_spr()", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/298671/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1627175/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1627175/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "bilbo.ozlabs.org;\n\tdkim=pass (2048-bit key;\n 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by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <danielhb413@gmail.com>)\n id 1nmgYg-00036Q-AI; Thu, 05 May 2022 14:50:38 -0400", "from mail-oi1-x22d.google.com ([2607:f8b0:4864:20::22d]:45976)\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <danielhb413@gmail.com>)\n id 1nmgYd-0004TA-SN; Thu, 05 May 2022 14:50:38 -0400", "by mail-oi1-x22d.google.com with SMTP id n24so5238424oie.12;\n Thu, 05 May 2022 11:50:35 -0700 (PDT)", "from balboa.ibmuc.com (201-1-57-208.dsl.telesp.net.br.\n [201.1.57.208]) by smtp.gmail.com with ESMTPSA id\n n67-20020aca4046000000b00325cda1ff94sm917146oia.19.2022.05.05.11.50.32\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Thu, 05 May 2022 11:50:34 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112;\n h=from:to:cc:subject:date:message-id:in-reply-to:references\n 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L0mPxyGbOcD4ulb+Upwnqb3Jdw0ZNru8F0GFNuEEBvAzuSF/k7YnKnY9z3+bV9uIXMj/\n D0ocgW8dMO+B6YNq2z4Rwm6xncqAqUB7DoQ9rEWk0/WHw1+u/nwYQ9gli33sCCgELTtQ\n 8c9Q==", "X-Gm-Message-State": "AOAM531kf0n1ICMGmpTnUft1KSmAy470I/PUl8qFMltIldaI9ONSE7FK\n YdwLZcfHXCXKYPW72hv1UdlNQDsvKZg=", "X-Google-Smtp-Source": "\n ABdhPJx03bBqOa1laC/kF9ZIPRyYfBqFoF0Iik9bVvDMvuoEebTB6qG7glIvekmJo0hNXAhsShdLIw==", "X-Received": "by 2002:a05:6808:1392:b0:326:4e8:1672 with SMTP id\n c18-20020a056808139200b0032604e81672mr3200796oiw.177.1651776634593;\n Thu, 05 May 2022 11:50:34 -0700 (PDT)", "From": "Daniel Henrique Barboza <danielhb413@gmail.com>", "To": "qemu-devel@nongnu.org", "Cc": "qemu-ppc@nongnu.org, danielhb413@gmail.com, peter.maydell@linaro.org,\n richard.henderson@linaro.org,\n =?utf-8?q?V=C3=ADctor_Colombo?= <victor.colombo@eldorado.org.br>", "Subject": "[PULL 09/30] target/ppc: Remove fpscr_* macros from cpu.h", "Date": "Thu, 5 May 2022 15:49:17 -0300", "Message-Id": "<20220505184938.351866-10-danielhb413@gmail.com>", "X-Mailer": "git-send-email 2.32.0", "In-Reply-To": "<20220505184938.351866-1-danielhb413@gmail.com>", "References": "<20220505184938.351866-1-danielhb413@gmail.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::22d;\n envelope-from=danielhb413@gmail.com; helo=mail-oi1-x22d.google.com", "X-Spam_score_int": "-18", "X-Spam_score": "-1.9", "X-Spam_bar": "-", "X-Spam_report": "(-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001,\n T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Víctor Colombo <victor.colombo@eldorado.org.br>\n\nfpscr_* defined macros are hiding the usage of *env behind them.\nSubstitute the usage of these macros with `env->fpscr & FP_*` to make\nthe code cleaner.\n\nSuggested-by: Richard Henderson <richard.henderson@linaro.org>\nReviewed-by: Richard Henderson <richard.henderson@linaro.org>\nSigned-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>\nMessage-Id: <20220504210541.115256-2-victor.colombo@eldorado.org.br>\nSigned-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>\n---\n target/ppc/cpu.c | 2 +-\n target/ppc/cpu.h | 29 -----------------------------\n target/ppc/fpu_helper.c | 28 ++++++++++++++--------------\n 3 files changed, 15 insertions(+), 44 deletions(-)", "diff": "diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c\nindex d7b42bae52..401b6f9e63 100644\n--- a/target/ppc/cpu.c\n+++ b/target/ppc/cpu.c\n@@ -88,7 +88,7 @@ static inline void fpscr_set_rounding_mode(CPUPPCState *env)\n int rnd_type;\n \n /* Set rounding mode */\n- switch (fpscr_rn) {\n+ switch (env->fpscr & FP_RN) {\n case 0:\n /* Best approximation (round to nearest) */\n rnd_type = float_round_nearest_even;\ndiff --git a/target/ppc/cpu.h b/target/ppc/cpu.h\nindex c2b6c987c0..ad31e51d69 100644\n--- a/target/ppc/cpu.h\n+++ b/target/ppc/cpu.h\n@@ -713,41 +713,12 @@ enum {\n #define FPSCR_NI 2 /* Floating-point non-IEEE mode */\n #define FPSCR_RN1 1\n #define FPSCR_RN0 0 /* Floating-point rounding control */\n-#define fpscr_drn (((env->fpscr) & FP_DRN) >> FPSCR_DRN0)\n-#define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)\n-#define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)\n-#define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)\n-#define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)\n-#define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)\n-#define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)\n-#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)\n-#define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)\n-#define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)\n-#define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)\n-#define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)\n-#define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)\n-#define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)\n-#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)\n-#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)\n-#define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)\n-#define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)\n-#define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)\n-#define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)\n-#define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)\n-#define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)\n-#define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)\n-#define fpscr_rn (((env->fpscr) >> FPSCR_RN0) & 0x3)\n /* Invalid operation exception summary */\n #define FPSCR_IX ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \\\n (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \\\n (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \\\n (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \\\n (1 << FPSCR_VXCVI))\n-/* exception summary */\n-#define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)\n-/* enabled exception summary */\n-#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \\\n- 0x1F)\n \n #define FP_DRN2 (1ull << FPSCR_DRN2)\n #define FP_DRN1 (1ull << FPSCR_DRN1)\ndiff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c\nindex 99281cc37a..f6c8318a71 100644\n--- a/target/ppc/fpu_helper.c\n+++ b/target/ppc/fpu_helper.c\n@@ -202,7 +202,7 @@ static void finish_invalid_op_excp(CPUPPCState *env, int op, uintptr_t retaddr)\n env->fpscr |= FP_VX;\n /* Update the floating-point exception summary */\n env->fpscr |= FP_FX;\n- if (fpscr_ve != 0) {\n+ if (env->fpscr & FP_VE) {\n /* Update the floating-point enabled exception summary */\n env->fpscr |= FP_FEX;\n if (fp_exceptions_enabled(env)) {\n@@ -216,7 +216,7 @@ static void finish_invalid_op_arith(CPUPPCState *env, int op,\n bool set_fpcc, uintptr_t retaddr)\n {\n env->fpscr &= ~(FP_FR | FP_FI);\n- if (fpscr_ve == 0) {\n+ if (!(env->fpscr & FP_VE)) {\n if (set_fpcc) {\n env->fpscr &= ~FP_FPCC;\n env->fpscr |= (FP_C | FP_FU);\n@@ -286,7 +286,7 @@ static void float_invalid_op_vxvc(CPUPPCState *env, bool set_fpcc,\n /* Update the floating-point exception summary */\n env->fpscr |= FP_FX;\n /* We must update the target FPR before raising the exception */\n- if (fpscr_ve != 0) {\n+ if (env->fpscr & FP_VE) {\n CPUState *cs = env_cpu(env);\n \n cs->exception_index = POWERPC_EXCP_PROGRAM;\n@@ -303,7 +303,7 @@ static void float_invalid_op_vxcvi(CPUPPCState *env, bool set_fpcc,\n {\n env->fpscr |= FP_VXCVI;\n env->fpscr &= ~(FP_FR | FP_FI);\n- if (fpscr_ve == 0) {\n+ if (!(env->fpscr & FP_VE)) {\n if (set_fpcc) {\n env->fpscr &= ~FP_FPCC;\n env->fpscr |= (FP_C | FP_FU);\n@@ -318,7 +318,7 @@ static inline void float_zero_divide_excp(CPUPPCState *env, uintptr_t raddr)\n env->fpscr &= ~(FP_FR | FP_FI);\n /* Update the floating-point exception summary */\n env->fpscr |= FP_FX;\n- if (fpscr_ze != 0) {\n+ if (env->fpscr & FP_ZE) {\n /* Update the floating-point enabled exception summary */\n env->fpscr |= FP_FEX;\n if (fp_exceptions_enabled(env)) {\n@@ -336,7 +336,7 @@ static inline void float_overflow_excp(CPUPPCState *env)\n env->fpscr |= FP_OX;\n /* Update the floating-point exception summary */\n env->fpscr |= FP_FX;\n- if (fpscr_oe != 0) {\n+ if (env->fpscr & FP_OE) {\n /* XXX: should adjust the result */\n /* Update the floating-point enabled exception summary */\n env->fpscr |= FP_FEX;\n@@ -356,7 +356,7 @@ static inline void float_underflow_excp(CPUPPCState *env)\n env->fpscr |= FP_UX;\n /* Update the floating-point exception summary */\n env->fpscr |= FP_FX;\n- if (fpscr_ue != 0) {\n+ if (env->fpscr & FP_UE) {\n /* XXX: should adjust the result */\n /* Update the floating-point enabled exception summary */\n env->fpscr |= FP_FEX;\n@@ -374,7 +374,7 @@ static inline void float_inexact_excp(CPUPPCState *env)\n env->fpscr |= FP_XX;\n /* Update the floating-point exception summary */\n env->fpscr |= FP_FX;\n- if (fpscr_xe != 0) {\n+ if (env->fpscr & FP_XE) {\n /* Update the floating-point enabled exception summary */\n env->fpscr |= FP_FEX;\n /* We must update the target FPR before raising the exception */\n@@ -2274,7 +2274,7 @@ VSX_MADDQ(XSNMSUBQPO, NMSUB_FLGS, 0)\n vxvc = svxvc; \\\n if (flags & float_flag_invalid_snan) { \\\n float_invalid_op_vxsnan(env, GETPC()); \\\n- vxvc &= fpscr_ve == 0; \\\n+ vxvc &= !(env->fpscr & FP_VE); \\\n } \\\n if (vxvc) { \\\n float_invalid_op_vxvc(env, 0, GETPC()); \\\n@@ -2375,7 +2375,7 @@ static inline void do_scalar_cmp(CPUPPCState *env, ppc_vsr_t *xa, ppc_vsr_t *xb,\n if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) ||\n float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) {\n vxsnan_flag = true;\n- if (fpscr_ve == 0 && ordered) {\n+ if (!(env->fpscr & FP_VE) && ordered) {\n vxvc_flag = true;\n }\n } else if (float64_is_quiet_nan(xa->VsrD(0), &env->fp_status) ||\n@@ -2440,7 +2440,7 @@ static inline void do_scalar_cmpq(CPUPPCState *env, ppc_vsr_t *xa,\n if (float128_is_signaling_nan(xa->f128, &env->fp_status) ||\n float128_is_signaling_nan(xb->f128, &env->fp_status)) {\n vxsnan_flag = true;\n- if (fpscr_ve == 0 && ordered) {\n+ if (!(env->fpscr & FP_VE) && ordered) {\n vxvc_flag = true;\n }\n } else if (float128_is_quiet_nan(xa->f128, &env->fp_status) ||\n@@ -2590,7 +2590,7 @@ void helper_##name(CPUPPCState *env, \\\n t.VsrD(0) = xb->VsrD(0); \\\n } \\\n \\\n- vex_flag = fpscr_ve & vxsnan_flag; \\\n+ vex_flag = (env->fpscr & FP_VE) && vxsnan_flag; \\\n if (vxsnan_flag) { \\\n float_invalid_op_vxsnan(env, GETPC()); \\\n } \\\n@@ -3320,7 +3320,7 @@ void helper_xsrqpi(CPUPPCState *env, uint32_t opcode,\n if (r == 0 && rmc == 0) {\n rmode = float_round_ties_away;\n } else if (r == 0 && rmc == 0x3) {\n- rmode = fpscr_rn;\n+ rmode = env->fpscr & FP_RN;\n } else if (r == 1) {\n switch (rmc) {\n case 0:\n@@ -3374,7 +3374,7 @@ void helper_xsrqpxp(CPUPPCState *env, uint32_t opcode,\n if (r == 0 && rmc == 0) {\n rmode = float_round_ties_away;\n } else if (r == 0 && rmc == 0x3) {\n- rmode = fpscr_rn;\n+ rmode = env->fpscr & FP_RN;\n } else if (r == 1) {\n switch (rmc) {\n case 0:\n", "prefixes": [ "PULL", "09/30" ] }