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GET /api/patches/1624913/?format=api
{ "id": 1624913, "url": "http://patchwork.ozlabs.org/api/patches/1624913/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20220501142357.16778-7-pali@kernel.org/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20220501142357.16778-7-pali@kernel.org>", "list_archive_url": null, "date": "2022-05-01T14:23:57", "name": "[6/6] board: freescale: p1_p2_rdb_pc: Fix size of NAND mapping", "commit_ref": null, "pull_url": null, "state": "rejected", "archived": false, "hash": "91180501492851682f66706e6fb0515561157fb7", "submitter": { "id": 78810, "url": "http://patchwork.ozlabs.org/api/people/78810/?format=api", "name": "Pali Rohár", "email": "pali@kernel.org" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20220501142357.16778-7-pali@kernel.org/mbox/", "series": [ { "id": 297864, "url": "http://patchwork.ozlabs.org/api/series/297864/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=297864", "date": "2022-05-01T14:23:51", "name": "board: freescale: p1_p2_rdb_pc: Fix sizes of LBC peripherals", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/297864/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1624913/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1624913/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "bilbo.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=RPPj7xCT;\n\tdkim-atps=neutral", "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=kernel.org", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.b=\"RPPj7xCT\";\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=kernel.org", "phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (2048 bits))\n\t(No client certificate requested)\n\tby bilbo.ozlabs.org (Postfix) with ESMTPS id 4KrpTL40hVz9s2R\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 2 May 2022 00:27:18 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 2DC5A83F48;\n\tSun, 1 May 2022 16:26:21 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id 3406783F05; Sun, 1 May 2022 16:26:09 +0200 (CEST)", "from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n bits)) (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id B3DC383F21\n for <u-boot@lists.denx.de>; Sun, 1 May 2022 16:25:59 +0200 (CEST)", "from smtp.kernel.org (relay.kernel.org [52.25.139.140])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n (No client certificate requested)\n by dfw.source.kernel.org (Postfix) with ESMTPS id 5F0AA60ED9;\n Sun, 1 May 2022 14:25:58 +0000 (UTC)", "by smtp.kernel.org (Postfix) with ESMTPSA id 0E0D9C385AA;\n Sun, 1 May 2022 14:25:58 +0000 (UTC)", "by pali.im (Postfix)\n id BCD5C942; Sun, 1 May 2022 16:25:57 +0200 (CEST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,\n DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,\n SPF_PASS autolearn=ham autolearn_force=no version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n s=k20201202; t=1651415158;\n bh=MfjDR3mWtBvSMxf+YQhf3LISW6hFIvUHYo88Qr7RaTw=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=RPPj7xCTG92KR9miMZlUul7pAFSBg8MSYO+dWQYlHxKBDPaphALtsFGqKpzv6QKxZ\n 05JR28T3YlAtNLDWil0zBqPXnEq946DQer1ywjlmaGsFGoBd/pSJ6LCs+5tI6P4aQb\n dwJT1EbavexXTGkQi5tHviCU/XG61fgtIh/LXHmfuNen5zSkJ8ANl28+KGsiqvw2+v\n YkgY7GWCTjnSazAKmSFLTpLaT8cBBHRuAnShCt/ueKyiFwUtpTwVytciv5OuYkcdTh\n 6gJeFKndhJq9uSVBFvx0JhYCf09VGlMR6kIibNE9EffDuYVzWUvLZy38GEWjq89LLv\n bVV81LNMj6Slw==", "From": "=?utf-8?q?Pali_Roh=C3=A1r?= <pali@kernel.org>", "To": "Tom Rini <trini@konsulko.com>", "Cc": "u-boot@lists.denx.de", "Subject": "[PATCH 6/6] board: freescale: p1_p2_rdb_pc: Fix size of NAND mapping", "Date": "Sun, 1 May 2022 16:23:57 +0200", "Message-Id": "<20220501142357.16778-7-pali@kernel.org>", "X-Mailer": "git-send-email 2.20.1", "In-Reply-To": "<20220501142357.16778-1-pali@kernel.org>", "References": "<20220501142357.16778-1-pali@kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.5 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "P1020RDB-PD has NAND with large page. All other P1/P2 RDB boards have NAND\nwith small page. According to P1/P2 RM documentation, for NAND with large\npage it is needed to use 256 kB mapping and for small page just 32 kB.\n\nCurrenly in p1_p2_rdb_pc board code there is a mix of 32 kB and 1 MB\nsettings which effetively restrict to just 32 kB. Fix this issue and set\nTLB, LAW and LBC OR registers which correct mapping size based on the\nselected board.\n\nNote that E500 core does not support Book-E page of 32 kB, so choose 64 kB\nsettings for TLB.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\n---\n board/freescale/p1_p2_rdb_pc/law.c | 4 ++++\n board/freescale/p1_p2_rdb_pc/tlb.c | 11 +++++++++--\n include/configs/p1_p2_rdb_pc.h | 4 ++--\n 3 files changed, 15 insertions(+), 4 deletions(-)", "diff": "diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c\nindex 80adf21a1183..60672d34e11c 100644\n--- a/board/freescale/p1_p2_rdb_pc/law.c\n+++ b/board/freescale/p1_p2_rdb_pc/law.c\n@@ -19,8 +19,12 @@ struct law_entry law_table[] = {\n \tSET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_LBC),\n #endif\n #ifdef CONFIG_SYS_NAND_BASE_PHYS\n+#ifdef CONFIG_TARGET_P1020RDB_PD\n+\tSET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_256K, LAW_TRGT_IF_LBC),\n+#else\n \tSET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),\n #endif\n+#endif\n };\n \n int num_law_entries = ARRAY_SIZE(law_table);\ndiff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c\nindex 5bbeae302ad0..a5b80762f0fc 100644\n--- a/board/freescale/p1_p2_rdb_pc/tlb.c\n+++ b/board/freescale/p1_p2_rdb_pc/tlb.c\n@@ -78,10 +78,17 @@ struct fsl_e_tlb_entry tlb_table[] = {\n #endif /* not SPL */\n \n #ifdef CONFIG_SYS_NAND_BASE\n-\t/* *I*G - NAND */\n+#ifdef CONFIG_TARGET_P1020RDB_PD\n+\t/* *I*G - NAND large page 256K */\n \tSET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,\n \t\t\tMAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,\n-\t\t\t0, 7, BOOKE_PAGESZ_1M, 1),\n+\t\t\t0, 7, BOOKE_PAGESZ_256K, 1),\n+#else\n+\t/* *I*G - NAND small page 64K (effective only 32K; e500 does not support BOOKE_PAGESZ_32K) */\n+\tSET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,\n+\t\t\tMAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,\n+\t\t\t0, 7, BOOKE_PAGESZ_64K, 1),\n+#endif\n #endif\n \n #if defined(CONFIG_SYS_RAMBOOT) || \\\ndiff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h\nindex cf84f4045538..2ddf768f2c82 100644\n--- a/include/configs/p1_p2_rdb_pc.h\n+++ b/include/configs/p1_p2_rdb_pc.h\n@@ -214,7 +214,7 @@\n * 0xec00_0000 0xefff_ffff\tNOR flash\tUp to 64M non-cacheable\tCS0/1\n * 0xf8f8_0000 0xf8ff_ffff\tL2 SRAM\t\tUp to 512K cacheable\n * (early boot only)\n- * 0xff80_0000 0xff80_7fff\tNAND flash\t32K non-cacheable\tCS1/0\n+ * 0xff80_0000 0xff83_ffff\tNAND flash\t32K/256K non-cacheable\tCS1/0\n * 0xff98_0000 0xff98_ffff\tPMC\t\t64K non-cacheable\tCS2\n * 0xffa0_0000 0xffa1_ffff\tCPLD\t\t128K non-cacheable\tCS3\n * 0xffb0_0000 0xffbf_ffff\tVSC7385 switch 1M non-cacheable\tCS2\n@@ -283,7 +283,7 @@\n \t| BR_MS_FCM\t/* MSEL = FCM */ \\\n \t| BR_V)\t/* valid */\n #if defined(CONFIG_TARGET_P1020RDB_PD)\n-#define CONFIG_SYS_NAND_OR_PRELIM\t(OR_AM_32KB \\\n+#define CONFIG_SYS_NAND_OR_PRELIM\t(OR_AM_256KB \\\n \t| OR_FCM_PGS\t/* Large Page*/ \\\n \t| OR_FCM_CSCT \\\n \t| OR_FCM_CST \\\n", "prefixes": [ "6/6" ] }