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{
    "id": 1624912,
    "url": "http://patchwork.ozlabs.org/api/patches/1624912/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20220501142357.16778-2-pali@kernel.org/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20220501142357.16778-2-pali@kernel.org>",
    "list_archive_url": null,
    "date": "2022-05-01T14:23:52",
    "name": "[1/6] Revert \"Convert CONFIG_SYS_BR0_PRELIM et al to Kconfig\"",
    "commit_ref": null,
    "pull_url": null,
    "state": "rejected",
    "archived": false,
    "hash": "a8d0bbab1d859e580015c3fa8604669fe0825516",
    "submitter": {
        "id": 78810,
        "url": "http://patchwork.ozlabs.org/api/people/78810/?format=api",
        "name": "Pali Rohár",
        "email": "pali@kernel.org"
    },
    "delegate": {
        "id": 3651,
        "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api",
        "username": "trini",
        "first_name": "Tom",
        "last_name": "Rini",
        "email": "trini@ti.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20220501142357.16778-2-pali@kernel.org/mbox/",
    "series": [
        {
            "id": 297864,
            "url": "http://patchwork.ozlabs.org/api/series/297864/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=297864",
            "date": "2022-05-01T14:23:51",
            "name": "board: freescale: p1_p2_rdb_pc: Fix sizes of LBC peripherals",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/297864/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/1624912/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/1624912/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "=?utf-8?q?Pali_Roh=C3=A1r?= <pali@kernel.org>",
        "To": "Tom Rini <trini@konsulko.com>",
        "Cc": "u-boot@lists.denx.de",
        "Subject": "[PATCH 1/6] Revert \"Convert CONFIG_SYS_BR0_PRELIM et al to Kconfig\"",
        "Date": "Sun,  1 May 2022 16:23:52 +0200",
        "Message-Id": "<20220501142357.16778-2-pali@kernel.org>",
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    "content": "This reverts commit c7fad78ec0ee41b72a58bebb61959570eb937ab1.\n\nThis commit made configuration, understanding, maintenance, debugging and\nfuture development of the powerpc/mpc85xx Local Bus Controller on P1/P2\nboards impossible.\n\nAll preliminary Base and Option registers depends on other code and C\nmacros generated at C compile time and they comes from the other macros.\n\nFor example, NOR base address and NOR options are set via macros\nCONFIG_SYS_FLASH_BR_PRELIM and CONFIG_SYS_FLASH_OR_PRELIM. And then based\non other logic are filled correct values in to the correct macros\nCONFIG_SYS_BR*_PRELIM and CONFIG_SYS_OR*_PRELIM.\n\nThese config options are not user configurable options and therefore\nshould not appear in menuconfig. Moreover for P1/P2 boards they have\nnothing with DDR driver, so they should not appear in drivers/ddr.\n\nThis change was completely wrong direction, so revert it. It allows to\nstart fixing issues with FLASH, NOR, NAND and CPLD LBC configuration.\nIn current state it is impossible.\n\nSee also thread for more details:\nhttps://lore.kernel.org/u-boot/20220426181740.o2n7xfg46ytljcdx@pali/t/#u\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\n---\n README                                       |  11 ++\n arch/powerpc/cpu/mpc83xx/elbc/elbc.h         | 170 +++++++++++++++++++\n arch/powerpc/cpu/mpc8xx/Kconfig              |  85 ++++++++++\n configs/M5272C3_defconfig                    |  24 ---\n configs/MCR3000_defconfig                    |  47 +++--\n configs/MPC837XERDB_defconfig                |   9 -\n configs/MPC8548CDS_36BIT_defconfig           |  12 --\n configs/MPC8548CDS_defconfig                 |  12 --\n configs/MPC8548CDS_legacy_defconfig          |  12 --\n configs/P1020RDB-PC_36BIT_NAND_defconfig     |  12 --\n configs/P1020RDB-PC_36BIT_SDCARD_defconfig   |   9 -\n configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig |   9 -\n configs/P1020RDB-PC_36BIT_defconfig          |   9 -\n configs/P1020RDB-PC_NAND_defconfig           |  12 --\n configs/P1020RDB-PC_SDCARD_defconfig         |   9 -\n configs/P1020RDB-PC_SPIFLASH_defconfig       |   9 -\n configs/P1020RDB-PC_defconfig                |   9 -\n configs/P1020RDB-PD_NAND_defconfig           |  12 --\n configs/P1020RDB-PD_SDCARD_defconfig         |   9 -\n configs/P1020RDB-PD_SPIFLASH_defconfig       |   9 -\n configs/P1020RDB-PD_defconfig                |   9 -\n configs/P2020RDB-PC_36BIT_NAND_defconfig     |  12 --\n configs/P2020RDB-PC_36BIT_SDCARD_defconfig   |   9 -\n configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig |   9 -\n configs/P2020RDB-PC_36BIT_defconfig          |   9 -\n configs/P2020RDB-PC_NAND_defconfig           |  12 --\n configs/P2020RDB-PC_SDCARD_defconfig         |   9 -\n configs/P2020RDB-PC_SPIFLASH_defconfig       |   9 -\n configs/P2020RDB-PC_defconfig                |   9 -\n configs/P2041RDB_NAND_defconfig              |   9 -\n configs/P2041RDB_SDCARD_defconfig            |   6 -\n configs/P2041RDB_SPIFLASH_defconfig          |   6 -\n configs/P2041RDB_defconfig                   |   6 -\n configs/P3041DS_NAND_defconfig               |  12 --\n configs/P3041DS_SDCARD_defconfig             |   9 -\n configs/P3041DS_SPIFLASH_defconfig           |   9 -\n configs/P3041DS_defconfig                    |   9 -\n configs/P4080DS_SDCARD_defconfig             |   9 -\n configs/P4080DS_SPIFLASH_defconfig           |   9 -\n configs/P4080DS_defconfig                    |   9 -\n configs/P5040DS_NAND_defconfig               |  12 --\n configs/P5040DS_SDCARD_defconfig             |   9 -\n configs/P5040DS_SPIFLASH_defconfig           |   9 -\n configs/P5040DS_defconfig                    |   9 -\n configs/cobra5272_defconfig                  |  24 ---\n configs/gazerbeam_defconfig                  |   9 -\n configs/ids8313_defconfig                    |  12 --\n configs/kmcoge5ne_defconfig                  |  12 --\n configs/kmeter1_defconfig                    |   9 -\n configs/kmopti2_defconfig                    |  12 --\n configs/kmsupx5_defconfig                    |   9 -\n configs/kmtegr1_defconfig                    |   9 -\n configs/kmtepr2_defconfig                    |  12 --\n configs/socrates_defconfig                   |  12 --\n configs/tuge1_defconfig                      |   9 -\n configs/tuxx1_defconfig                      |  12 --\n drivers/ddr/fsl/Kconfig                      |  92 ----------\n include/configs/M5272C3.h                    |  20 +++\n include/configs/MPC8548CDS.h                 |  17 ++\n include/configs/P2041RDB.h                   |  18 ++\n include/configs/cobra5272.h                  |  30 ++++\n include/configs/corenet_ds.h                 |  22 +++\n include/configs/p1_p2_rdb_pc.h               |  19 +++\n include/configs/socrates.h                   |   9 +\n scripts/config_whitelist.txt                 |  18 ++\n 65 files changed, 442 insertions(+), 653 deletions(-)",
    "diff": "diff --git a/README b/README\nindex b7ab6e50708d..dbea360bbf70 100644\n--- a/README\n+++ b/README\n@@ -2233,6 +2233,17 @@ Low Level (hardware related) configuration options:\n - CONFIG_SYS_MAMR_PTA:\n \t\tperiodic timer for refresh\n \n+- FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CONFIG_SYS_REMAP_OR_AM,\n+  CONFIG_SYS_PRELIM_OR_AM, CONFIG_SYS_OR_TIMING_FLASH, CONFIG_SYS_OR0_REMAP,\n+  CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR1_REMAP, CONFIG_SYS_OR1_PRELIM,\n+  CONFIG_SYS_BR1_PRELIM:\n+\t\tMemory Controller Definitions: BR0/1 and OR0/1 (FLASH)\n+\n+- SDRAM_BASE2_PRELIM, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE,\n+  CONFIG_SYS_OR_TIMING_SDRAM, CONFIG_SYS_OR2_PRELIM, CONFIG_SYS_BR2_PRELIM,\n+  CONFIG_SYS_OR3_PRELIM, CONFIG_SYS_BR3_PRELIM:\n+\t\tMemory Controller Definitions: BR2/3 and OR2/3 (SDRAM)\n+\n - CONFIG_SYS_SRIO:\n \t\tChip has SRIO or not\n \ndiff --git a/arch/powerpc/cpu/mpc83xx/elbc/elbc.h b/arch/powerpc/cpu/mpc83xx/elbc/elbc.h\nindex e795cd10cb95..245fe7c6fb79 100644\n--- a/arch/powerpc/cpu/mpc83xx/elbc/elbc.h\n+++ b/arch/powerpc/cpu/mpc83xx/elbc/elbc.h\n@@ -1,3 +1,173 @@\n+#ifdef CONFIG_ELBC_BR0_OR0\n+#define CONFIG_SYS_BR0_PRELIM (\\\n+\tCONFIG_BR0_OR0_BASE |\\\n+\tCONFIG_BR0_PORTSIZE |\\\n+\tCONFIG_BR0_ERRORCHECKING |\\\n+\tCONFIG_BR0_WRITE_PROTECT_BIT |\\\n+\tCONFIG_BR0_MACHINE |\\\n+\tCONFIG_BR0_ATOMIC |\\\n+\tCONFIG_BR0_VALID_BIT \\\n+)\n+#define CONFIG_SYS_OR0_PRELIM (\\\n+\tCONFIG_OR0_AM |\\\n+\tCONFIG_OR0_XAM |\\\n+\tCONFIG_OR0_BCTLD |\\\n+\tCONFIG_OR0_BI |\\\n+\tCONFIG_OR0_COLS |\\\n+\tCONFIG_OR0_ROWS |\\\n+\tCONFIG_OR0_PMSEL |\\\n+\tCONFIG_OR0_SCY |\\\n+\tCONFIG_OR0_PGS |\\\n+\tCONFIG_OR0_CSCT |\\\n+\tCONFIG_OR0_CST |\\\n+\tCONFIG_OR0_CHT |\\\n+\tCONFIG_OR0_RST |\\\n+\tCONFIG_OR0_CSNT |\\\n+\tCONFIG_OR0_ACS |\\\n+\tCONFIG_OR0_XACS |\\\n+\tCONFIG_OR0_SETA |\\\n+\tCONFIG_OR0_TRLX |\\\n+\tCONFIG_OR0_EHTR |\\\n+\tCONFIG_OR0_EAD \\\n+)\n+#endif /* CONFIG_ELBC_BR0_OR0 */\n+\n+#ifdef CONFIG_ELBC_BR1_OR1\n+#define CONFIG_SYS_BR1_PRELIM (\\\n+\tCONFIG_BR1_OR1_BASE |\\\n+\tCONFIG_BR1_PORTSIZE |\\\n+\tCONFIG_BR1_ERRORCHECKING |\\\n+\tCONFIG_BR1_WRITE_PROTECT_BIT |\\\n+\tCONFIG_BR1_MACHINE |\\\n+\tCONFIG_BR1_ATOMIC |\\\n+\tCONFIG_BR1_VALID_BIT \\\n+)\n+#define CONFIG_SYS_OR1_PRELIM (\\\n+\tCONFIG_OR1_AM |\\\n+\tCONFIG_OR1_XAM |\\\n+\tCONFIG_OR1_BCTLD |\\\n+\tCONFIG_OR1_BI |\\\n+\tCONFIG_OR1_COLS |\\\n+\tCONFIG_OR1_ROWS |\\\n+\tCONFIG_OR1_PMSEL |\\\n+\tCONFIG_OR1_SCY |\\\n+\tCONFIG_OR1_PGS |\\\n+\tCONFIG_OR1_CSCT |\\\n+\tCONFIG_OR1_CST |\\\n+\tCONFIG_OR1_CHT |\\\n+\tCONFIG_OR1_RST |\\\n+\tCONFIG_OR1_CSNT |\\\n+\tCONFIG_OR1_ACS |\\\n+\tCONFIG_OR1_XACS |\\\n+\tCONFIG_OR1_SETA |\\\n+\tCONFIG_OR1_TRLX |\\\n+\tCONFIG_OR1_EHTR |\\\n+\tCONFIG_OR1_EAD \\\n+)\n+#endif /* CONFIG_ELBC_BR1_OR1 */\n+\n+#ifdef CONFIG_ELBC_BR2_OR2\n+#define CONFIG_SYS_BR2_PRELIM (\\\n+\tCONFIG_BR2_OR2_BASE |\\\n+\tCONFIG_BR2_PORTSIZE |\\\n+\tCONFIG_BR2_ERRORCHECKING |\\\n+\tCONFIG_BR2_WRITE_PROTECT_BIT |\\\n+\tCONFIG_BR2_MACHINE |\\\n+\tCONFIG_BR2_ATOMIC |\\\n+\tCONFIG_BR2_VALID_BIT \\\n+)\n+#define CONFIG_SYS_OR2_PRELIM (\\\n+\tCONFIG_OR2_AM |\\\n+\tCONFIG_OR2_XAM |\\\n+\tCONFIG_OR2_BCTLD |\\\n+\tCONFIG_OR2_BI |\\\n+\tCONFIG_OR2_COLS |\\\n+\tCONFIG_OR2_ROWS |\\\n+\tCONFIG_OR2_PMSEL |\\\n+\tCONFIG_OR2_SCY |\\\n+\tCONFIG_OR2_PGS |\\\n+\tCONFIG_OR2_CSCT |\\\n+\tCONFIG_OR2_CST |\\\n+\tCONFIG_OR2_CHT |\\\n+\tCONFIG_OR2_RST |\\\n+\tCONFIG_OR2_CSNT |\\\n+\tCONFIG_OR2_ACS |\\\n+\tCONFIG_OR2_XACS |\\\n+\tCONFIG_OR2_SETA |\\\n+\tCONFIG_OR2_TRLX |\\\n+\tCONFIG_OR2_EHTR |\\\n+\tCONFIG_OR2_EAD \\\n+)\n+#endif /* CONFIG_ELBC_BR2_OR2 */\n+\n+#ifdef CONFIG_ELBC_BR3_OR3\n+#define CONFIG_SYS_BR3_PRELIM (\\\n+\tCONFIG_BR3_OR3_BASE |\\\n+\tCONFIG_BR3_PORTSIZE |\\\n+\tCONFIG_BR3_ERRORCHECKING |\\\n+\tCONFIG_BR3_WRITE_PROTECT_BIT |\\\n+\tCONFIG_BR3_MACHINE |\\\n+\tCONFIG_BR3_ATOMIC |\\\n+\tCONFIG_BR3_VALID_BIT \\\n+)\n+#define CONFIG_SYS_OR3_PRELIM (\\\n+\tCONFIG_OR3_AM |\\\n+\tCONFIG_OR3_XAM |\\\n+\tCONFIG_OR3_BCTLD |\\\n+\tCONFIG_OR3_BI |\\\n+\tCONFIG_OR3_COLS |\\\n+\tCONFIG_OR3_ROWS |\\\n+\tCONFIG_OR3_PMSEL |\\\n+\tCONFIG_OR3_SCY |\\\n+\tCONFIG_OR3_PGS |\\\n+\tCONFIG_OR3_CSCT |\\\n+\tCONFIG_OR3_CST |\\\n+\tCONFIG_OR3_CHT |\\\n+\tCONFIG_OR3_RST |\\\n+\tCONFIG_OR3_CSNT |\\\n+\tCONFIG_OR3_ACS |\\\n+\tCONFIG_OR3_XACS |\\\n+\tCONFIG_OR3_SETA |\\\n+\tCONFIG_OR3_TRLX |\\\n+\tCONFIG_OR3_EHTR |\\\n+\tCONFIG_OR3_EAD \\\n+)\n+#endif /* CONFIG_ELBC_BR3_OR3 */\n+\n+#ifdef CONFIG_ELBC_BR4_OR4\n+#define CONFIG_SYS_BR4_PRELIM (\\\n+\tCONFIG_BR4_OR4_BASE |\\\n+\tCONFIG_BR4_PORTSIZE |\\\n+\tCONFIG_BR4_ERRORCHECKING |\\\n+\tCONFIG_BR4_WRITE_PROTECT_BIT |\\\n+\tCONFIG_BR4_MACHINE |\\\n+\tCONFIG_BR4_ATOMIC |\\\n+\tCONFIG_BR4_VALID_BIT \\\n+)\n+#define CONFIG_SYS_OR4_PRELIM (\\\n+\tCONFIG_OR4_AM |\\\n+\tCONFIG_OR4_XAM |\\\n+\tCONFIG_OR4_BCTLD |\\\n+\tCONFIG_OR4_BI |\\\n+\tCONFIG_OR4_COLS |\\\n+\tCONFIG_OR4_ROWS |\\\n+\tCONFIG_OR4_PMSEL |\\\n+\tCONFIG_OR4_SCY |\\\n+\tCONFIG_OR4_PGS |\\\n+\tCONFIG_OR4_CSCT |\\\n+\tCONFIG_OR4_CST |\\\n+\tCONFIG_OR4_CHT |\\\n+\tCONFIG_OR4_RST |\\\n+\tCONFIG_OR4_CSNT |\\\n+\tCONFIG_OR4_ACS |\\\n+\tCONFIG_OR4_XACS |\\\n+\tCONFIG_OR4_SETA |\\\n+\tCONFIG_OR4_TRLX |\\\n+\tCONFIG_OR4_EHTR |\\\n+\tCONFIG_OR4_EAD \\\n+)\n+#endif /* CONFIG_ELBC_BR4_OR4 */\n+\n #if defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_0)\n #define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM\n #define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM\ndiff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig\nindex d63071104c4d..2f844ea78677 100644\n--- a/arch/powerpc/cpu/mpc8xx/Kconfig\n+++ b/arch/powerpc/cpu/mpc8xx/Kconfig\n@@ -84,6 +84,91 @@ config SYS_DER\n \thelp\n \t  Debug Event Register (37-47)\n \n+comment \"Memory mapping\"\n+\n+config SYS_BR0_PRELIM\n+\thex \"Preliminary value for BR0\"\n+\n+config SYS_OR0_PRELIM\n+\thex \"Preliminary value for OR0\"\n+\n+config SYS_BR1_PRELIM_BOOL\n+\tbool \"Define Bank 1\"\n+\n+config SYS_BR1_PRELIM\n+\thex \"Preliminary value for BR1\"\n+\tdepends on SYS_BR1_PRELIM_BOOL\n+\n+config SYS_OR1_PRELIM\n+\thex \"Preliminary value for OR1\"\n+\tdepends on SYS_BR1_PRELIM_BOOL\n+\n+config SYS_BR2_PRELIM_BOOL\n+\tbool \"Define Bank 2\"\n+\n+config SYS_BR2_PRELIM\n+\thex \"Preliminary value for BR2\"\n+\tdepends on SYS_BR2_PRELIM_BOOL\n+\n+config SYS_OR2_PRELIM\n+\thex \"Preliminary value for OR2\"\n+\tdepends on SYS_BR2_PRELIM_BOOL\n+\n+config SYS_BR3_PRELIM_BOOL\n+\tbool \"Define Bank 3\"\n+\n+config SYS_BR3_PRELIM\n+\thex \"Preliminary value for BR3\"\n+\tdepends on SYS_BR3_PRELIM_BOOL\n+\n+config SYS_OR3_PRELIM\n+\thex \"Preliminary value for OR3\"\n+\tdepends on SYS_BR3_PRELIM_BOOL\n+\n+config SYS_BR4_PRELIM_BOOL\n+\tbool \"Define Bank 4\"\n+\n+config SYS_BR4_PRELIM\n+\thex \"Preliminary value for BR4\"\n+\tdepends on SYS_BR4_PRELIM_BOOL\n+\n+config SYS_OR4_PRELIM\n+\thex \"Preliminary value for OR4\"\n+\tdepends on SYS_BR4_PRELIM_BOOL\n+\n+config SYS_BR5_PRELIM_BOOL\n+\tbool \"Define Bank 5\"\n+\n+config SYS_BR5_PRELIM\n+\thex \"Preliminary value for BR5\"\n+\tdepends on SYS_BR5_PRELIM_BOOL\n+\n+config SYS_OR5_PRELIM\n+\thex \"Preliminary value for OR5\"\n+\tdepends on SYS_BR5_PRELIM_BOOL\n+\n+config SYS_BR6_PRELIM_BOOL\n+\tbool \"Define Bank 6\"\n+\n+config SYS_BR6_PRELIM\n+\thex \"Preliminary value for BR6\"\n+\tdepends on SYS_BR6_PRELIM_BOOL\n+\n+config SYS_OR6_PRELIM\n+\thex \"Preliminary value for OR6\"\n+\tdepends on SYS_BR6_PRELIM_BOOL\n+\n+config SYS_BR7_PRELIM_BOOL\n+\tbool \"Define Bank 7\"\n+\n+config SYS_BR7_PRELIM\n+\thex \"Preliminary value for BR7\"\n+\tdepends on SYS_BR7_PRELIM_BOOL\n+\n+config SYS_OR7_PRELIM\n+\thex \"Preliminary value for OR7\"\n+\tdepends on SYS_BR7_PRELIM_BOOL\n+\n source \"board/cssi/MCR3000/Kconfig\"\n \n endmenu\ndiff --git a/configs/M5272C3_defconfig b/configs/M5272C3_defconfig\nindex ed48264ed9ca..7ae4d3fab00d 100644\n--- a/configs/M5272C3_defconfig\n+++ b/configs/M5272C3_defconfig\n@@ -26,30 +26,6 @@ CONFIG_CMD_CACHE=y\n CONFIG_SYS_RELOC_GD_ENV_ADDR=y\n CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y\n CONFIG_SYS_RX_ETH_BUFFER=8\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xFFE00201\n-CONFIG_SYS_OR0_PRELIM=0xFFE00014\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0x0\n-CONFIG_SYS_OR1_PRELIM=0x0\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0x30000001\n-CONFIG_SYS_OR2_PRELIM=0xFFF80000\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0x0\n-CONFIG_SYS_OR3_PRELIM=0x0\n-CONFIG_SYS_BR4_PRELIM_BOOL=y\n-CONFIG_SYS_BR4_PRELIM=0x0\n-CONFIG_SYS_OR4_PRELIM=0x0\n-CONFIG_SYS_BR5_PRELIM_BOOL=y\n-CONFIG_SYS_BR5_PRELIM=0x0\n-CONFIG_SYS_OR5_PRELIM=0x0\n-CONFIG_SYS_BR6_PRELIM_BOOL=y\n-CONFIG_SYS_BR6_PRELIM=0x0\n-CONFIG_SYS_OR6_PRELIM=0x0\n-CONFIG_SYS_BR7_PRELIM_BOOL=y\n-CONFIG_SYS_BR7_PRELIM=0x701\n-CONFIG_SYS_OR7_PRELIM=0xFFC0007C\n CONFIG_MTD_NOR_FLASH=y\n CONFIG_FLASH_CFI_DRIVER=y\n CONFIG_SYS_FLASH_PROTECTION=y\ndiff --git a/configs/MCR3000_defconfig b/configs/MCR3000_defconfig\nindex f99a830b546a..ec7a27fb8692 100644\n--- a/configs/MCR3000_defconfig\n+++ b/configs/MCR3000_defconfig\n@@ -18,6 +18,29 @@ CONFIG_SYS_PLPRCR=0x00460004\n CONFIG_SYS_SCCR=0x00C20000\n CONFIG_SYS_SCCR_MASK=0x60000000\n CONFIG_SYS_DER=0x2002000F\n+CONFIG_SYS_BR0_PRELIM=0x04000801\n+CONFIG_SYS_OR0_PRELIM=0xFFC00926\n+CONFIG_SYS_BR1_PRELIM_BOOL=y\n+CONFIG_SYS_BR1_PRELIM=0x00000081\n+CONFIG_SYS_OR1_PRELIM=0xFE000E00\n+CONFIG_SYS_BR2_PRELIM_BOOL=y\n+CONFIG_SYS_BR2_PRELIM=0x08000801\n+CONFIG_SYS_OR2_PRELIM=0xFFFF8F2A\n+CONFIG_SYS_BR3_PRELIM_BOOL=y\n+CONFIG_SYS_BR3_PRELIM=0x0C000401\n+CONFIG_SYS_OR3_PRELIM=0xFFFF8142\n+CONFIG_SYS_BR4_PRELIM_BOOL=y\n+CONFIG_SYS_BR4_PRELIM=0x10000801\n+CONFIG_SYS_OR4_PRELIM=0xFFFF8D08\n+CONFIG_SYS_BR5_PRELIM_BOOL=y\n+CONFIG_SYS_BR5_PRELIM=0x14000801\n+CONFIG_SYS_OR5_PRELIM=0xFFFF8916\n+CONFIG_SYS_BR6_PRELIM_BOOL=y\n+CONFIG_SYS_BR6_PRELIM=0x18000801\n+CONFIG_SYS_OR6_PRELIM=0xFFFF0908\n+CONFIG_SYS_BR7_PRELIM_BOOL=y\n+CONFIG_SYS_BR7_PRELIM=0x1C000001\n+CONFIG_SYS_OR7_PRELIM=0xFFFF810A\n CONFIG_OF_BOARD_SETUP=y\n CONFIG_SYS_MONITOR_BASE=0x04000000\n CONFIG_BOOTDELAY=5\n@@ -52,30 +75,6 @@ CONFIG_ENV_OVERWRITE=y\n CONFIG_ENV_IS_IN_FLASH=y\n CONFIG_SYS_RELOC_GD_ENV_ADDR=y\n CONFIG_DM=y\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0x4000801\n-CONFIG_SYS_OR0_PRELIM=0xFFC00926\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0x81\n-CONFIG_SYS_OR1_PRELIM=0xFE000E00\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0x8000801\n-CONFIG_SYS_OR2_PRELIM=0xFFFF8F2A\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xC000401\n-CONFIG_SYS_OR3_PRELIM=0xFFFF8142\n-CONFIG_SYS_BR4_PRELIM_BOOL=y\n-CONFIG_SYS_BR4_PRELIM=0x10000801\n-CONFIG_SYS_OR4_PRELIM=0xFFFF8D08\n-CONFIG_SYS_BR5_PRELIM_BOOL=y\n-CONFIG_SYS_BR5_PRELIM=0x14000801\n-CONFIG_SYS_OR5_PRELIM=0xFFFF8916\n-CONFIG_SYS_BR6_PRELIM_BOOL=y\n-CONFIG_SYS_BR6_PRELIM=0x18000801\n-CONFIG_SYS_OR6_PRELIM=0xFFFF0908\n-CONFIG_SYS_BR7_PRELIM_BOOL=y\n-CONFIG_SYS_BR7_PRELIM=0x1C000001\n-CONFIG_SYS_OR7_PRELIM=0xFFFF810A\n # CONFIG_MMC is not set\n CONFIG_MTD=y\n CONFIG_MTD_NOR_FLASH=y\ndiff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig\nindex 4a9db732f92e..dc6d847d9437 100644\n--- a/configs/MPC837XERDB_defconfig\n+++ b/configs/MPC837XERDB_defconfig\n@@ -175,15 +175,6 @@ CONFIG_ETHPRIME=\"TSEC0\"\n CONFIG_DM=y\n CONFIG_FSL_SATA=y\n CONFIG_SYS_SATA_MAX_DEVICE=2\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xFE001001\n-CONFIG_SYS_OR0_PRELIM=0xFF800193\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0xE0600C21\n-CONFIG_SYS_OR1_PRELIM=0xFFFF8396\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xF0000801\n-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF\n CONFIG_SYS_I2C_LEGACY=y\n CONFIG_SYS_I2C_FSL=y\n CONFIG_SYS_FSL_I2C_OFFSET=0x3000\ndiff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig\nindex 6933699771fb..f63bf06ac6c9 100644\n--- a/configs/MPC8548CDS_36BIT_defconfig\n+++ b/configs/MPC8548CDS_36BIT_defconfig\n@@ -39,18 +39,6 @@ CONFIG_DM=y\n CONFIG_CHIP_SELECTS_PER_CTRL=2\n CONFIG_DDR_ECC=y\n CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xFF807001\n-CONFIG_SYS_OR0_PRELIM=0xFF806E65\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0xFF007001\n-CONFIG_SYS_OR1_PRELIM=0xFF806E65\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xF0007861\n-CONFIG_SYS_OR2_PRELIM=0xFC006901\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xF8006801\n-CONFIG_SYS_OR3_PRELIM=0xFFF00FF7\n CONFIG_DM_I2C=y\n CONFIG_I2C_SET_DEFAULT_BUS_NUM=y\n CONFIG_SYS_I2C_FSL=y\ndiff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig\nindex ee9c14880c6e..63ef36fad625 100644\n--- a/configs/MPC8548CDS_defconfig\n+++ b/configs/MPC8548CDS_defconfig\n@@ -38,18 +38,6 @@ CONFIG_DM=y\n CONFIG_CHIP_SELECTS_PER_CTRL=2\n CONFIG_DDR_ECC=y\n CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xFF801001\n-CONFIG_SYS_OR0_PRELIM=0xFF806E65\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0xFF001001\n-CONFIG_SYS_OR1_PRELIM=0xFF806E65\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xF0001861\n-CONFIG_SYS_OR2_PRELIM=0xFC006901\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xF8000801\n-CONFIG_SYS_OR3_PRELIM=0xFFF00FF7\n CONFIG_DM_I2C=y\n CONFIG_I2C_SET_DEFAULT_BUS_NUM=y\n CONFIG_SYS_I2C_FSL=y\ndiff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig\nindex 97f641d71cdf..25d347bd7855 100644\n--- a/configs/MPC8548CDS_legacy_defconfig\n+++ b/configs/MPC8548CDS_legacy_defconfig\n@@ -38,18 +38,6 @@ CONFIG_DM=y\n CONFIG_CHIP_SELECTS_PER_CTRL=2\n CONFIG_DDR_ECC=y\n CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xFF801001\n-CONFIG_SYS_OR0_PRELIM=0xFF806E65\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0xFF001001\n-CONFIG_SYS_OR1_PRELIM=0xFF806E65\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xF0001861\n-CONFIG_SYS_OR2_PRELIM=0xFC006901\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xF8000801\n-CONFIG_SYS_OR3_PRELIM=0xFFF00FF7\n CONFIG_DM_I2C=y\n CONFIG_I2C_SET_DEFAULT_BUS_NUM=y\n CONFIG_SYS_I2C_FSL=y\ndiff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig\nindex 56b984e5ae68..015ce7257f3a 100644\n--- a/configs/P1020RDB-PC_36BIT_NAND_defconfig\n+++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig\n@@ -60,18 +60,6 @@ CONFIG_ETHPRIME=\"eTSEC1\"\n CONFIG_DM=y\n CONFIG_DDR_CLK_FREQ=66666666\n CONFIG_CHIP_SELECTS_PER_CTRL=1\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xFF800C21\n-CONFIG_SYS_OR0_PRELIM=0xFFFF8396\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0xEF001001\n-CONFIG_SYS_OR1_PRELIM=0xFC000FF7\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xFFB00801\n-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFA00801\n-CONFIG_SYS_OR3_PRELIM=0xFFF009F7\n CONFIG_DM_I2C=y\n CONFIG_SPL_SYS_I2C_LEGACY=y\n CONFIG_TPL_SYS_I2C_LEGACY=y\ndiff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig\nindex 4407a02a7d97..f6efdf1c9967 100644\n--- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig\n+++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig\n@@ -56,15 +56,6 @@ CONFIG_ETHPRIME=\"eTSEC1\"\n CONFIG_DM=y\n CONFIG_DDR_CLK_FREQ=66666666\n CONFIG_CHIP_SELECTS_PER_CTRL=1\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xEF001001\n-CONFIG_SYS_OR0_PRELIM=0xFC000FF7\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xFFB00801\n-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFA00801\n-CONFIG_SYS_OR3_PRELIM=0xFFF009F7\n CONFIG_DM_I2C=y\n CONFIG_SPL_SYS_I2C_LEGACY=y\n CONFIG_I2C_SET_DEFAULT_BUS_NUM=y\ndiff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig\nindex ee0fdd6657d1..926b5ac928c9 100644\n--- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig\n+++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig\n@@ -59,15 +59,6 @@ CONFIG_ETHPRIME=\"eTSEC1\"\n CONFIG_DM=y\n CONFIG_DDR_CLK_FREQ=66666666\n CONFIG_CHIP_SELECTS_PER_CTRL=1\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xEF001001\n-CONFIG_SYS_OR0_PRELIM=0xFC000FF7\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xFFB00801\n-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFA00801\n-CONFIG_SYS_OR3_PRELIM=0xFFF009F7\n CONFIG_DM_I2C=y\n CONFIG_SPL_SYS_I2C_LEGACY=y\n CONFIG_I2C_SET_DEFAULT_BUS_NUM=y\ndiff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig\nindex bbfc4a5bcff9..a807e272e046 100644\n--- a/configs/P1020RDB-PC_36BIT_defconfig\n+++ b/configs/P1020RDB-PC_36BIT_defconfig\n@@ -45,15 +45,6 @@ CONFIG_ETHPRIME=\"eTSEC1\"\n CONFIG_DM=y\n CONFIG_DDR_CLK_FREQ=66666666\n CONFIG_CHIP_SELECTS_PER_CTRL=1\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xEF001001\n-CONFIG_SYS_OR0_PRELIM=0xFC000FF7\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xFFB00801\n-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFA00801\n-CONFIG_SYS_OR3_PRELIM=0xFFF009F7\n CONFIG_DM_I2C=y\n CONFIG_SPL_SYS_I2C_LEGACY=y\n CONFIG_I2C_SET_DEFAULT_BUS_NUM=y\ndiff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig\nindex 00d847d50af2..cf46268981e5 100644\n--- a/configs/P1020RDB-PC_NAND_defconfig\n+++ b/configs/P1020RDB-PC_NAND_defconfig\n@@ -59,18 +59,6 @@ CONFIG_ETHPRIME=\"eTSEC1\"\n CONFIG_DM=y\n CONFIG_DDR_CLK_FREQ=66666666\n CONFIG_CHIP_SELECTS_PER_CTRL=1\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xFF800C21\n-CONFIG_SYS_OR0_PRELIM=0xFFFF8396\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0xEF001001\n-CONFIG_SYS_OR1_PRELIM=0xFC000FF7\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xFFB00801\n-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFA00801\n-CONFIG_SYS_OR3_PRELIM=0xFFF009F7\n CONFIG_DM_I2C=y\n CONFIG_SPL_SYS_I2C_LEGACY=y\n CONFIG_TPL_SYS_I2C_LEGACY=y\ndiff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig\nindex feb00ea91615..e640e48e6fbd 100644\n--- a/configs/P1020RDB-PC_SDCARD_defconfig\n+++ b/configs/P1020RDB-PC_SDCARD_defconfig\n@@ -55,15 +55,6 @@ CONFIG_ETHPRIME=\"eTSEC1\"\n CONFIG_DM=y\n CONFIG_DDR_CLK_FREQ=66666666\n CONFIG_CHIP_SELECTS_PER_CTRL=1\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xEF001001\n-CONFIG_SYS_OR0_PRELIM=0xFC000FF7\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xFFB00801\n-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFA00801\n-CONFIG_SYS_OR3_PRELIM=0xFFF009F7\n CONFIG_DM_I2C=y\n CONFIG_SPL_SYS_I2C_LEGACY=y\n CONFIG_I2C_SET_DEFAULT_BUS_NUM=y\ndiff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig\nindex f18f4b2ce150..6e11abebca56 100644\n--- a/configs/P1020RDB-PC_SPIFLASH_defconfig\n+++ b/configs/P1020RDB-PC_SPIFLASH_defconfig\n@@ -58,15 +58,6 @@ CONFIG_ETHPRIME=\"eTSEC1\"\n CONFIG_DM=y\n CONFIG_DDR_CLK_FREQ=66666666\n CONFIG_CHIP_SELECTS_PER_CTRL=1\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xEF001001\n-CONFIG_SYS_OR0_PRELIM=0xFC000FF7\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xFFB00801\n-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFA00801\n-CONFIG_SYS_OR3_PRELIM=0xFFF009F7\n CONFIG_DM_I2C=y\n CONFIG_SPL_SYS_I2C_LEGACY=y\n CONFIG_I2C_SET_DEFAULT_BUS_NUM=y\ndiff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig\nindex aec0d47acb7c..069b21885fa4 100644\n--- a/configs/P1020RDB-PC_defconfig\n+++ b/configs/P1020RDB-PC_defconfig\n@@ -44,15 +44,6 @@ CONFIG_ETHPRIME=\"eTSEC1\"\n CONFIG_DM=y\n CONFIG_DDR_CLK_FREQ=66666666\n CONFIG_CHIP_SELECTS_PER_CTRL=1\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xEF001001\n-CONFIG_SYS_OR0_PRELIM=0xFC000FF7\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xFFB00801\n-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFA00801\n-CONFIG_SYS_OR3_PRELIM=0xFFF009F7\n CONFIG_DM_I2C=y\n CONFIG_SPL_SYS_I2C_LEGACY=y\n CONFIG_I2C_SET_DEFAULT_BUS_NUM=y\ndiff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig\nindex 0d713624d488..867e6328564b 100644\n--- a/configs/P1020RDB-PD_NAND_defconfig\n+++ b/configs/P1020RDB-PD_NAND_defconfig\n@@ -62,18 +62,6 @@ CONFIG_ETHPRIME=\"eTSEC1\"\n CONFIG_DM=y\n CONFIG_DDR_CLK_FREQ=66666666\n CONFIG_CHIP_SELECTS_PER_CTRL=2\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xFF800C21\n-CONFIG_SYS_OR0_PRELIM=0xFFFF8796\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0xEC001001\n-CONFIG_SYS_OR1_PRELIM=0xFC000FF7\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xFFB00801\n-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFA00801\n-CONFIG_SYS_OR3_PRELIM=0xFFF009F7\n CONFIG_DM_I2C=y\n CONFIG_SPL_SYS_I2C_LEGACY=y\n CONFIG_TPL_SYS_I2C_LEGACY=y\ndiff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig\nindex b50dfcbc392c..799e2442644e 100644\n--- a/configs/P1020RDB-PD_SDCARD_defconfig\n+++ b/configs/P1020RDB-PD_SDCARD_defconfig\n@@ -58,15 +58,6 @@ CONFIG_ETHPRIME=\"eTSEC1\"\n CONFIG_DM=y\n CONFIG_DDR_CLK_FREQ=66666666\n CONFIG_CHIP_SELECTS_PER_CTRL=2\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xEC001001\n-CONFIG_SYS_OR0_PRELIM=0xFC000FF7\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xFFB00801\n-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFA00801\n-CONFIG_SYS_OR3_PRELIM=0xFFF009F7\n CONFIG_DM_I2C=y\n CONFIG_SPL_SYS_I2C_LEGACY=y\n CONFIG_I2C_SET_DEFAULT_BUS_NUM=y\ndiff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig\nindex 6649f5b2feaf..907ad57ef5df 100644\n--- a/configs/P1020RDB-PD_SPIFLASH_defconfig\n+++ b/configs/P1020RDB-PD_SPIFLASH_defconfig\n@@ -61,15 +61,6 @@ CONFIG_ETHPRIME=\"eTSEC1\"\n CONFIG_DM=y\n CONFIG_DDR_CLK_FREQ=66666666\n CONFIG_CHIP_SELECTS_PER_CTRL=2\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xEC001001\n-CONFIG_SYS_OR0_PRELIM=0xFC000FF7\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xFFB00801\n-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFA00801\n-CONFIG_SYS_OR3_PRELIM=0xFFF009F7\n CONFIG_DM_I2C=y\n CONFIG_SPL_SYS_I2C_LEGACY=y\n CONFIG_I2C_SET_DEFAULT_BUS_NUM=y\ndiff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig\nindex cbbdb0fb113a..b9f48a45fd19 100644\n--- a/configs/P1020RDB-PD_defconfig\n+++ b/configs/P1020RDB-PD_defconfig\n@@ -47,15 +47,6 @@ CONFIG_ETHPRIME=\"eTSEC1\"\n CONFIG_DM=y\n CONFIG_DDR_CLK_FREQ=66666666\n CONFIG_CHIP_SELECTS_PER_CTRL=2\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xEC001001\n-CONFIG_SYS_OR0_PRELIM=0xFC000FF7\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xFFB00801\n-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFA00801\n-CONFIG_SYS_OR3_PRELIM=0xFFF009F7\n CONFIG_DM_I2C=y\n CONFIG_SPL_SYS_I2C_LEGACY=y\n CONFIG_I2C_SET_DEFAULT_BUS_NUM=y\ndiff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig\nindex e167468ed385..f256d5303a94 100644\n--- a/configs/P2020RDB-PC_36BIT_NAND_defconfig\n+++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig\n@@ -64,18 +64,6 @@ CONFIG_ETHPRIME=\"eTSEC1\"\n CONFIG_DM=y\n CONFIG_DDR_CLK_FREQ=66666666\n CONFIG_CHIP_SELECTS_PER_CTRL=1\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xFF800C21\n-CONFIG_SYS_OR0_PRELIM=0xFFFF8396\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0xEF001001\n-CONFIG_SYS_OR1_PRELIM=0xFC000FF7\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xFFB00801\n-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFA00801\n-CONFIG_SYS_OR3_PRELIM=0xFFF009F7\n CONFIG_DM_I2C=y\n CONFIG_SPL_SYS_I2C_LEGACY=y\n CONFIG_TPL_SYS_I2C_LEGACY=y\ndiff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig\nindex 1e15552edc70..5ea88e071c8a 100644\n--- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig\n+++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig\n@@ -60,15 +60,6 @@ CONFIG_ETHPRIME=\"eTSEC1\"\n CONFIG_DM=y\n CONFIG_DDR_CLK_FREQ=66666666\n CONFIG_CHIP_SELECTS_PER_CTRL=1\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xEF001001\n-CONFIG_SYS_OR0_PRELIM=0xFC000FF7\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xFFB00801\n-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFA00801\n-CONFIG_SYS_OR3_PRELIM=0xFFF009F7\n CONFIG_DM_I2C=y\n CONFIG_SPL_SYS_I2C_LEGACY=y\n CONFIG_I2C_SET_DEFAULT_BUS_NUM=y\ndiff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig\nindex cf0ae5da3cfa..99fe986e0969 100644\n--- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig\n+++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig\n@@ -63,15 +63,6 @@ CONFIG_ETHPRIME=\"eTSEC1\"\n CONFIG_DM=y\n CONFIG_DDR_CLK_FREQ=66666666\n CONFIG_CHIP_SELECTS_PER_CTRL=1\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xEF001001\n-CONFIG_SYS_OR0_PRELIM=0xFC000FF7\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xFFB00801\n-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFA00801\n-CONFIG_SYS_OR3_PRELIM=0xFFF009F7\n CONFIG_DM_I2C=y\n CONFIG_SPL_SYS_I2C_LEGACY=y\n CONFIG_I2C_SET_DEFAULT_BUS_NUM=y\ndiff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig\nindex bd189b965b00..d9dec63ad13a 100644\n--- a/configs/P2020RDB-PC_36BIT_defconfig\n+++ b/configs/P2020RDB-PC_36BIT_defconfig\n@@ -49,15 +49,6 @@ CONFIG_ETHPRIME=\"eTSEC1\"\n CONFIG_DM=y\n CONFIG_DDR_CLK_FREQ=66666666\n CONFIG_CHIP_SELECTS_PER_CTRL=1\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xEF001001\n-CONFIG_SYS_OR0_PRELIM=0xFC000FF7\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xFFB00801\n-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFA00801\n-CONFIG_SYS_OR3_PRELIM=0xFFF009F7\n CONFIG_DM_I2C=y\n CONFIG_SPL_SYS_I2C_LEGACY=y\n CONFIG_I2C_SET_DEFAULT_BUS_NUM=y\ndiff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig\nindex 29d90c91400e..5e055ebc4e25 100644\n--- a/configs/P2020RDB-PC_NAND_defconfig\n+++ b/configs/P2020RDB-PC_NAND_defconfig\n@@ -63,18 +63,6 @@ CONFIG_ETHPRIME=\"eTSEC1\"\n CONFIG_DM=y\n CONFIG_DDR_CLK_FREQ=66666666\n CONFIG_CHIP_SELECTS_PER_CTRL=1\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xFF800C21\n-CONFIG_SYS_OR0_PRELIM=0xFFFF8396\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0xEF001001\n-CONFIG_SYS_OR1_PRELIM=0xFC000FF7\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xFFB00801\n-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFA00801\n-CONFIG_SYS_OR3_PRELIM=0xFFF009F7\n CONFIG_DM_I2C=y\n CONFIG_SPL_SYS_I2C_LEGACY=y\n CONFIG_TPL_SYS_I2C_LEGACY=y\ndiff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig\nindex 540999bef21d..73651a6b4d89 100644\n--- a/configs/P2020RDB-PC_SDCARD_defconfig\n+++ b/configs/P2020RDB-PC_SDCARD_defconfig\n@@ -59,15 +59,6 @@ CONFIG_ETHPRIME=\"eTSEC1\"\n CONFIG_DM=y\n CONFIG_DDR_CLK_FREQ=66666666\n CONFIG_CHIP_SELECTS_PER_CTRL=1\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xEF001001\n-CONFIG_SYS_OR0_PRELIM=0xFC000FF7\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xFFB00801\n-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFA00801\n-CONFIG_SYS_OR3_PRELIM=0xFFF009F7\n CONFIG_DM_I2C=y\n CONFIG_SPL_SYS_I2C_LEGACY=y\n CONFIG_I2C_SET_DEFAULT_BUS_NUM=y\ndiff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig\nindex 0881e35476ac..8a5b7c9f115d 100644\n--- a/configs/P2020RDB-PC_SPIFLASH_defconfig\n+++ b/configs/P2020RDB-PC_SPIFLASH_defconfig\n@@ -62,15 +62,6 @@ CONFIG_ETHPRIME=\"eTSEC1\"\n CONFIG_DM=y\n CONFIG_DDR_CLK_FREQ=66666666\n CONFIG_CHIP_SELECTS_PER_CTRL=1\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xEF001001\n-CONFIG_SYS_OR0_PRELIM=0xFC000FF7\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xFFB00801\n-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFA00801\n-CONFIG_SYS_OR3_PRELIM=0xFFF009F7\n CONFIG_DM_I2C=y\n CONFIG_SPL_SYS_I2C_LEGACY=y\n CONFIG_I2C_SET_DEFAULT_BUS_NUM=y\ndiff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig\nindex eba11d340acb..30897e11d02b 100644\n--- a/configs/P2020RDB-PC_defconfig\n+++ b/configs/P2020RDB-PC_defconfig\n@@ -48,15 +48,6 @@ CONFIG_ETHPRIME=\"eTSEC1\"\n CONFIG_DM=y\n CONFIG_DDR_CLK_FREQ=66666666\n CONFIG_CHIP_SELECTS_PER_CTRL=1\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xEF001001\n-CONFIG_SYS_OR0_PRELIM=0xFC000FF7\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xFFB00801\n-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFA00801\n-CONFIG_SYS_OR3_PRELIM=0xFFF009F7\n CONFIG_DM_I2C=y\n CONFIG_SPL_SYS_I2C_LEGACY=y\n CONFIG_I2C_SET_DEFAULT_BUS_NUM=y\ndiff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig\nindex 9717f50834ad..97e67db39ef4 100644\n--- a/configs/P2041RDB_NAND_defconfig\n+++ b/configs/P2041RDB_NAND_defconfig\n@@ -47,15 +47,6 @@ CONFIG_ETHPRIME=\"FM1@DTSEC1\"\n CONFIG_DM=y\n CONFIG_SYS_SATA_MAX_DEVICE=2\n CONFIG_FSL_CAAM=y\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xFFA00C21\n-CONFIG_SYS_OR0_PRELIM=0xFFFC0796\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0xE8001001\n-CONFIG_SYS_OR1_PRELIM=0xF8000F85\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFDF0801\n-CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7\n CONFIG_DM_I2C=y\n CONFIG_I2C_SET_DEFAULT_BUS_NUM=y\n CONFIG_SYS_I2C_FSL=y\ndiff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig\nindex 50065c4a9672..1142d563c56e 100644\n--- a/configs/P2041RDB_SDCARD_defconfig\n+++ b/configs/P2041RDB_SDCARD_defconfig\n@@ -47,12 +47,6 @@ CONFIG_ETHPRIME=\"FM1@DTSEC1\"\n CONFIG_DM=y\n CONFIG_SYS_SATA_MAX_DEVICE=2\n CONFIG_FSL_CAAM=y\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xE8001001\n-CONFIG_SYS_OR0_PRELIM=0xF8000F85\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFDF0801\n-CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7\n CONFIG_DM_I2C=y\n CONFIG_I2C_SET_DEFAULT_BUS_NUM=y\n CONFIG_SYS_I2C_FSL=y\ndiff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig\nindex 25f32c03c149..c74c1c60e8f4 100644\n--- a/configs/P2041RDB_SPIFLASH_defconfig\n+++ b/configs/P2041RDB_SPIFLASH_defconfig\n@@ -49,12 +49,6 @@ CONFIG_ETHPRIME=\"FM1@DTSEC1\"\n CONFIG_DM=y\n CONFIG_SYS_SATA_MAX_DEVICE=2\n CONFIG_FSL_CAAM=y\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xE8001001\n-CONFIG_SYS_OR0_PRELIM=0xF8000F85\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFDF0801\n-CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7\n CONFIG_DM_I2C=y\n CONFIG_I2C_SET_DEFAULT_BUS_NUM=y\n CONFIG_SYS_I2C_FSL=y\ndiff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig\nindex 29e94fcd094c..421eefc7df28 100644\n--- a/configs/P2041RDB_defconfig\n+++ b/configs/P2041RDB_defconfig\n@@ -44,12 +44,6 @@ CONFIG_ETHPRIME=\"FM1@DTSEC1\"\n CONFIG_DM=y\n CONFIG_SYS_SATA_MAX_DEVICE=2\n CONFIG_FSL_CAAM=y\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xE8001001\n-CONFIG_SYS_OR0_PRELIM=0xF8000F85\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFDF0801\n-CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7\n CONFIG_DM_I2C=y\n CONFIG_I2C_SET_DEFAULT_BUS_NUM=y\n CONFIG_SYS_I2C_FSL=y\ndiff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig\nindex 638b409b9635..66dbffc2d198 100644\n--- a/configs/P3041DS_NAND_defconfig\n+++ b/configs/P3041DS_NAND_defconfig\n@@ -47,18 +47,6 @@ CONFIG_SYS_SATA_MAX_DEVICE=2\n CONFIG_FSL_CAAM=y\n CONFIG_DDR_ECC=y\n CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xFFA00C21\n-CONFIG_SYS_OR0_PRELIM=0xFFFC0796\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0xE0001001\n-CONFIG_SYS_OR1_PRELIM=0xF8000FF7\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xE8001001\n-CONFIG_SYS_OR2_PRELIM=0xF8000F85\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFDF0801\n-CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7\n CONFIG_DM_I2C=y\n CONFIG_I2C_SET_DEFAULT_BUS_NUM=y\n CONFIG_SYS_I2C_FSL=y\ndiff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig\nindex e05ea44d2c2a..aec5e6019191 100644\n--- a/configs/P3041DS_SDCARD_defconfig\n+++ b/configs/P3041DS_SDCARD_defconfig\n@@ -47,15 +47,6 @@ CONFIG_SYS_SATA_MAX_DEVICE=2\n CONFIG_FSL_CAAM=y\n CONFIG_DDR_ECC=y\n CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xE8001001\n-CONFIG_SYS_OR0_PRELIM=0xF8000F85\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0xE0001001\n-CONFIG_SYS_OR1_PRELIM=0xF8000FF7\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFDF0801\n-CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7\n CONFIG_DM_I2C=y\n CONFIG_I2C_SET_DEFAULT_BUS_NUM=y\n CONFIG_SYS_I2C_FSL=y\ndiff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig\nindex 9bfde175420f..53612ce2be63 100644\n--- a/configs/P3041DS_SPIFLASH_defconfig\n+++ b/configs/P3041DS_SPIFLASH_defconfig\n@@ -49,15 +49,6 @@ CONFIG_SYS_SATA_MAX_DEVICE=2\n CONFIG_FSL_CAAM=y\n CONFIG_DDR_ECC=y\n CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xE8001001\n-CONFIG_SYS_OR0_PRELIM=0xF8000F85\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0xE0001001\n-CONFIG_SYS_OR1_PRELIM=0xF8000FF7\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFDF0801\n-CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7\n CONFIG_DM_I2C=y\n CONFIG_I2C_SET_DEFAULT_BUS_NUM=y\n CONFIG_SYS_I2C_FSL=y\ndiff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig\nindex d62a200871ab..1b4a85344a69 100644\n--- a/configs/P3041DS_defconfig\n+++ b/configs/P3041DS_defconfig\n@@ -44,15 +44,6 @@ CONFIG_SYS_SATA_MAX_DEVICE=2\n CONFIG_FSL_CAAM=y\n CONFIG_DDR_ECC=y\n CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xE8001001\n-CONFIG_SYS_OR0_PRELIM=0xF8000F85\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0xE0001001\n-CONFIG_SYS_OR1_PRELIM=0xF8000FF7\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFDF0801\n-CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7\n CONFIG_DM_I2C=y\n CONFIG_I2C_SET_DEFAULT_BUS_NUM=y\n CONFIG_SYS_I2C_FSL=y\ndiff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig\nindex 63f8e6aa9d49..715a049f679c 100644\n--- a/configs/P4080DS_SDCARD_defconfig\n+++ b/configs/P4080DS_SDCARD_defconfig\n@@ -46,15 +46,6 @@ CONFIG_DM=y\n CONFIG_FSL_CAAM=y\n CONFIG_DDR_ECC=y\n CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xE8001001\n-CONFIG_SYS_OR0_PRELIM=0xF8000F85\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0xE0001001\n-CONFIG_SYS_OR1_PRELIM=0xF8000FF7\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFDF0801\n-CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7\n CONFIG_DM_I2C=y\n CONFIG_I2C_SET_DEFAULT_BUS_NUM=y\n CONFIG_SYS_I2C_FSL=y\ndiff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig\nindex 56da9d80b73f..b06cf949f1d2 100644\n--- a/configs/P4080DS_SPIFLASH_defconfig\n+++ b/configs/P4080DS_SPIFLASH_defconfig\n@@ -48,15 +48,6 @@ CONFIG_DM=y\n CONFIG_FSL_CAAM=y\n CONFIG_DDR_ECC=y\n CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xE8001001\n-CONFIG_SYS_OR0_PRELIM=0xF8000F85\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0xE0001001\n-CONFIG_SYS_OR1_PRELIM=0xF8000FF7\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFDF0801\n-CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7\n CONFIG_DM_I2C=y\n CONFIG_I2C_SET_DEFAULT_BUS_NUM=y\n CONFIG_SYS_I2C_FSL=y\ndiff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig\nindex ec5d2f9ac6c3..0c4251369059 100644\n--- a/configs/P4080DS_defconfig\n+++ b/configs/P4080DS_defconfig\n@@ -43,15 +43,6 @@ CONFIG_DM=y\n CONFIG_FSL_CAAM=y\n CONFIG_DDR_ECC=y\n CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xE8001001\n-CONFIG_SYS_OR0_PRELIM=0xF8000F85\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0xE0001001\n-CONFIG_SYS_OR1_PRELIM=0xF8000FF7\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFDF0801\n-CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7\n CONFIG_DM_I2C=y\n CONFIG_I2C_SET_DEFAULT_BUS_NUM=y\n CONFIG_SYS_I2C_FSL=y\ndiff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig\nindex 2ac298a43141..f4234723bc67 100644\n--- a/configs/P5040DS_NAND_defconfig\n+++ b/configs/P5040DS_NAND_defconfig\n@@ -48,18 +48,6 @@ CONFIG_SYS_SATA_MAX_DEVICE=2\n CONFIG_FSL_CAAM=y\n CONFIG_DDR_ECC=y\n CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xFFA00C21\n-CONFIG_SYS_OR0_PRELIM=0xFFFC0796\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0xE0001001\n-CONFIG_SYS_OR1_PRELIM=0xF8000FF7\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xE8001001\n-CONFIG_SYS_OR2_PRELIM=0xF8000F85\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFDF0801\n-CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7\n CONFIG_DM_I2C=y\n CONFIG_I2C_SET_DEFAULT_BUS_NUM=y\n CONFIG_SYS_I2C_FSL=y\ndiff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig\nindex a1ddca57750c..a7bef5db0dcc 100644\n--- a/configs/P5040DS_SDCARD_defconfig\n+++ b/configs/P5040DS_SDCARD_defconfig\n@@ -47,15 +47,6 @@ CONFIG_SYS_SATA_MAX_DEVICE=2\n CONFIG_FSL_CAAM=y\n CONFIG_DDR_ECC=y\n CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xE8001001\n-CONFIG_SYS_OR0_PRELIM=0xF8000F85\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0xE0001001\n-CONFIG_SYS_OR1_PRELIM=0xF8000FF7\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFDF0801\n-CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7\n CONFIG_DM_I2C=y\n CONFIG_I2C_SET_DEFAULT_BUS_NUM=y\n CONFIG_SYS_I2C_FSL=y\ndiff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig\nindex 32fec67e949e..0e18933e6ab5 100644\n--- a/configs/P5040DS_SPIFLASH_defconfig\n+++ b/configs/P5040DS_SPIFLASH_defconfig\n@@ -49,15 +49,6 @@ CONFIG_SYS_SATA_MAX_DEVICE=2\n CONFIG_FSL_CAAM=y\n CONFIG_DDR_ECC=y\n CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xE8001001\n-CONFIG_SYS_OR0_PRELIM=0xF8000F85\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0xE0001001\n-CONFIG_SYS_OR1_PRELIM=0xF8000FF7\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFDF0801\n-CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7\n CONFIG_DM_I2C=y\n CONFIG_I2C_SET_DEFAULT_BUS_NUM=y\n CONFIG_SYS_I2C_FSL=y\ndiff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig\nindex 48bd2b6f1bf1..927eb12b5a41 100644\n--- a/configs/P5040DS_defconfig\n+++ b/configs/P5040DS_defconfig\n@@ -44,15 +44,6 @@ CONFIG_SYS_SATA_MAX_DEVICE=2\n CONFIG_FSL_CAAM=y\n CONFIG_DDR_ECC=y\n CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xE8001001\n-CONFIG_SYS_OR0_PRELIM=0xF8000F85\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0xE0001001\n-CONFIG_SYS_OR1_PRELIM=0xF8000FF7\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xFFDF0801\n-CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7\n CONFIG_DM_I2C=y\n CONFIG_I2C_SET_DEFAULT_BUS_NUM=y\n CONFIG_SYS_I2C_FSL=y\ndiff --git a/configs/cobra5272_defconfig b/configs/cobra5272_defconfig\nindex eacfc6614339..da3a009ead59 100644\n--- a/configs/cobra5272_defconfig\n+++ b/configs/cobra5272_defconfig\n@@ -23,30 +23,6 @@ CONFIG_CMD_PING=y\n CONFIG_SYS_RELOC_GD_ENV_ADDR=y\n CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y\n CONFIG_SYS_RX_ETH_BUFFER=8\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xFFE00201\n-CONFIG_SYS_OR0_PRELIM=0xFFE00014\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0x0\n-CONFIG_SYS_OR1_PRELIM=0x0\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0x0\n-CONFIG_SYS_OR2_PRELIM=0x0\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0x0\n-CONFIG_SYS_OR3_PRELIM=0x0\n-CONFIG_SYS_BR4_PRELIM_BOOL=y\n-CONFIG_SYS_BR4_PRELIM=0x0\n-CONFIG_SYS_OR4_PRELIM=0x0\n-CONFIG_SYS_BR5_PRELIM_BOOL=y\n-CONFIG_SYS_BR5_PRELIM=0x0\n-CONFIG_SYS_OR5_PRELIM=0x0\n-CONFIG_SYS_BR6_PRELIM_BOOL=y\n-CONFIG_SYS_BR6_PRELIM=0x0\n-CONFIG_SYS_OR6_PRELIM=0x0\n-CONFIG_SYS_BR7_PRELIM_BOOL=y\n-CONFIG_SYS_BR7_PRELIM=0x701\n-CONFIG_SYS_OR7_PRELIM=0xFF00007C\n CONFIG_MTD_NOR_FLASH=y\n CONFIG_USE_SYS_MAX_FLASH_BANKS=y\n CONFIG_DM_ETH=y\ndiff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig\nindex f2f0257071c2..9d585fb4c34f 100644\n--- a/configs/gazerbeam_defconfig\n+++ b/configs/gazerbeam_defconfig\n@@ -162,15 +162,6 @@ CONFIG_CLK=y\n CONFIG_CLK_ICS8N3QV01=y\n CONFIG_CPU=y\n CONFIG_CPU_MPC83XX=y\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xFE001001\n-CONFIG_SYS_OR0_PRELIM=0xFF800FF6\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0xE0601001\n-CONFIG_SYS_OR1_PRELIM=0xFFF00850\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xE0701001\n-CONFIG_SYS_OR2_PRELIM=0xFFF00850\n CONFIG_DM_PCA953X=y\n CONFIG_MPC8XXX_GPIO=y\n CONFIG_DM_I2C=y\ndiff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig\nindex 7415b1158c6a..0740ba972a93 100644\n--- a/configs/ids8313_defconfig\n+++ b/configs/ids8313_defconfig\n@@ -166,18 +166,6 @@ CONFIG_ETHPRIME=\"TSEC1\"\n CONFIG_VERSION_VARIABLE=y\n CONFIG_BOOTCOUNT_LIMIT=y\n CONFIG_BOOTCOUNT_I2C=y\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xFF800801\n-CONFIG_SYS_OR0_PRELIM=0xFF8008A7\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0xE1000C21\n-CONFIG_SYS_OR1_PRELIM=0xFFFF87CE\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xE2000801\n-CONFIG_SYS_OR2_PRELIM=0xFFFE0C74\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xE3000801\n-CONFIG_SYS_OR3_PRELIM=0xFFFF8814\n CONFIG_SYS_I2C_LEGACY=y\n CONFIG_SYS_I2C_FSL=y\n CONFIG_SYS_FSL_I2C_OFFSET=0x3100\ndiff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig\nindex 00c98483b303..c3b7770e0a3b 100644\n--- a/configs/kmcoge5ne_defconfig\n+++ b/configs/kmcoge5ne_defconfig\n@@ -197,18 +197,6 @@ CONFIG_VERSION_VARIABLE=y\n CONFIG_BOOTCOUNT_LIMIT=y\n CONFIG_DM_BOOTCOUNT=y\n CONFIG_BOOTCOUNT_MEM=y\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xF0001001\n-CONFIG_SYS_OR0_PRELIM=0xF0000E55\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0xE8000801\n-CONFIG_SYS_OR1_PRELIM=0xFC000E25\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xA0000801\n-CONFIG_SYS_OR3_PRELIM=0xF0000E25\n-CONFIG_SYS_BR4_PRELIM_BOOL=y\n-CONFIG_SYS_BR4_PRELIM=0xB0000801\n-CONFIG_SYS_OR4_PRELIM=0xF0000E25\n CONFIG_SYS_I2C_LEGACY=y\n CONFIG_SYS_I2C_FSL=y\n CONFIG_SYS_FSL_I2C_OFFSET=0x3000\ndiff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig\nindex ae29991c492d..a869597bf464 100644\n--- a/configs/kmeter1_defconfig\n+++ b/configs/kmeter1_defconfig\n@@ -166,15 +166,6 @@ CONFIG_VERSION_VARIABLE=y\n CONFIG_BOOTCOUNT_LIMIT=y\n CONFIG_DM_BOOTCOUNT=y\n CONFIG_BOOTCOUNT_MEM=y\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xF0001001\n-CONFIG_SYS_OR0_PRELIM=0xF0000E55\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0xE8000801\n-CONFIG_SYS_OR1_PRELIM=0xFC000E25\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xA0000801\n-CONFIG_SYS_OR3_PRELIM=0xF0000E25\n CONFIG_SYS_I2C_LEGACY=y\n CONFIG_SYS_I2C_FSL=y\n CONFIG_SYS_FSL_I2C_OFFSET=0x3000\ndiff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig\nindex 45bc3eb3b4d5..d06ccce0c612 100644\n--- a/configs/kmopti2_defconfig\n+++ b/configs/kmopti2_defconfig\n@@ -178,18 +178,6 @@ CONFIG_VERSION_VARIABLE=y\n CONFIG_BOOTCOUNT_LIMIT=y\n CONFIG_DM_BOOTCOUNT=y\n CONFIG_BOOTCOUNT_MEM=y\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xF0001001\n-CONFIG_SYS_OR0_PRELIM=0xF0000E55\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0xE8000801\n-CONFIG_SYS_OR1_PRELIM=0xF8000E25\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xA0000801\n-CONFIG_SYS_OR2_PRELIM=0xF0000C25\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xB0001001\n-CONFIG_SYS_OR3_PRELIM=0xF0000040\n CONFIG_SYS_I2C_LEGACY=y\n CONFIG_SYS_I2C_FSL=y\n CONFIG_SYS_FSL_I2C_OFFSET=0x3000\ndiff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig\nindex 08d217986d74..03a86275482c 100644\n--- a/configs/kmsupx5_defconfig\n+++ b/configs/kmsupx5_defconfig\n@@ -157,15 +157,6 @@ CONFIG_VERSION_VARIABLE=y\n CONFIG_BOOTCOUNT_LIMIT=y\n CONFIG_DM_BOOTCOUNT=y\n CONFIG_BOOTCOUNT_MEM=y\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xF0001001\n-CONFIG_SYS_OR0_PRELIM=0xF0000E55\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0xE8000801\n-CONFIG_SYS_OR1_PRELIM=0xF8000E25\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xA0000801\n-CONFIG_SYS_OR2_PRELIM=0xF0000C25\n CONFIG_SYS_I2C_LEGACY=y\n CONFIG_SYS_I2C_FSL=y\n CONFIG_SYS_FSL_I2C_OFFSET=0x3000\ndiff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig\nindex a752672ead19..dbf20a1757c2 100644\n--- a/configs/kmtegr1_defconfig\n+++ b/configs/kmtegr1_defconfig\n@@ -158,15 +158,6 @@ CONFIG_VERSION_VARIABLE=y\n CONFIG_BOOTCOUNT_LIMIT=y\n CONFIG_DM_BOOTCOUNT=y\n CONFIG_BOOTCOUNT_MEM=y\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xF0001001\n-CONFIG_SYS_OR0_PRELIM=0xF0000E55\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0xE8000801\n-CONFIG_SYS_OR1_PRELIM=0xF8000E25\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xB0001001\n-CONFIG_SYS_OR3_PRELIM=0xF0000050\n CONFIG_SYS_I2C_LEGACY=y\n CONFIG_SYS_I2C_FSL=y\n CONFIG_SYS_FSL_I2C_OFFSET=0x3000\ndiff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig\nindex a0cca5b9f280..942161bcce26 100644\n--- a/configs/kmtepr2_defconfig\n+++ b/configs/kmtepr2_defconfig\n@@ -177,18 +177,6 @@ CONFIG_VERSION_VARIABLE=y\n CONFIG_BOOTCOUNT_LIMIT=y\n CONFIG_DM_BOOTCOUNT=y\n CONFIG_BOOTCOUNT_MEM=y\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xF0001001\n-CONFIG_SYS_OR0_PRELIM=0xF0000E55\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0xE8000801\n-CONFIG_SYS_OR1_PRELIM=0xF8000E25\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xA0000801\n-CONFIG_SYS_OR2_PRELIM=0xF0000C25\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xB0001001\n-CONFIG_SYS_OR3_PRELIM=0xF0000040\n CONFIG_SYS_I2C_LEGACY=y\n CONFIG_SYS_I2C_FSL=y\n CONFIG_SYS_FSL_I2C_OFFSET=0x3000\ndiff --git a/configs/socrates_defconfig b/configs/socrates_defconfig\nindex 2abb81c53b49..d0001045c4dd 100644\n--- a/configs/socrates_defconfig\n+++ b/configs/socrates_defconfig\n@@ -51,18 +51,6 @@ CONFIG_USE_ETHPRIME=y\n CONFIG_ETHPRIME=\"TSEC0\"\n CONFIG_DM=y\n CONFIG_CHIP_SELECTS_PER_CTRL=2\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xFE001001\n-CONFIG_SYS_OR0_PRELIM=0xFE000030\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0xFC001001\n-CONFIG_SYS_OR1_PRELIM=0xFE000030\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xC80018A1\n-CONFIG_SYS_OR2_PRELIM=0xFC000000\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xC0001881\n-CONFIG_SYS_OR3_PRELIM=0xFFF00000\n CONFIG_DM_I2C=y\n CONFIG_SYS_I2C_FSL=y\n # CONFIG_MMC is not set\ndiff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig\nindex 11f8b5b10516..ec9b3108f9c9 100644\n--- a/configs/tuge1_defconfig\n+++ b/configs/tuge1_defconfig\n@@ -157,15 +157,6 @@ CONFIG_VERSION_VARIABLE=y\n CONFIG_BOOTCOUNT_LIMIT=y\n CONFIG_DM_BOOTCOUNT=y\n CONFIG_BOOTCOUNT_MEM=y\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xF0001001\n-CONFIG_SYS_OR0_PRELIM=0xF0000E55\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0xE8000801\n-CONFIG_SYS_OR1_PRELIM=0xF8000E25\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xA0000801\n-CONFIG_SYS_OR2_PRELIM=0xF0000C25\n CONFIG_SYS_I2C_LEGACY=y\n CONFIG_SYS_I2C_FSL=y\n CONFIG_SYS_FSL_I2C_OFFSET=0x3000\ndiff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig\nindex c25366406219..b16936b43ae7 100644\n--- a/configs/tuxx1_defconfig\n+++ b/configs/tuxx1_defconfig\n@@ -179,18 +179,6 @@ CONFIG_VERSION_VARIABLE=y\n CONFIG_BOOTCOUNT_LIMIT=y\n CONFIG_DM_BOOTCOUNT=y\n CONFIG_BOOTCOUNT_MEM=y\n-CONFIG_SYS_BR0_PRELIM_BOOL=y\n-CONFIG_SYS_BR0_PRELIM=0xF0001001\n-CONFIG_SYS_OR0_PRELIM=0xF0000E55\n-CONFIG_SYS_BR1_PRELIM_BOOL=y\n-CONFIG_SYS_BR1_PRELIM=0xE8000801\n-CONFIG_SYS_OR1_PRELIM=0xF8000E25\n-CONFIG_SYS_BR2_PRELIM_BOOL=y\n-CONFIG_SYS_BR2_PRELIM=0xA0000801\n-CONFIG_SYS_OR2_PRELIM=0xF0000C25\n-CONFIG_SYS_BR3_PRELIM_BOOL=y\n-CONFIG_SYS_BR3_PRELIM=0xB0000801\n-CONFIG_SYS_OR3_PRELIM=0xF0000E24\n CONFIG_SYS_I2C_LEGACY=y\n CONFIG_SYS_I2C_FSL=y\n CONFIG_SYS_FSL_I2C_OFFSET=0x3000\ndiff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig\nindex 5925fe9e287c..4c6d2929967e 100644\n--- a/drivers/ddr/fsl/Kconfig\n+++ b/drivers/ddr/fsl/Kconfig\n@@ -171,98 +171,6 @@ config ECC_INIT_VIA_DDRCONTROLLER\n \n endif\n \n-menu \"PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)\"\n-\tdepends on MCF52x2 || MPC8xx || MPC83xx || MPC85xx\n-\n-config SYS_BR0_PRELIM_BOOL\n-\tbool \"Define Bank 0\"\n-\n-config SYS_BR0_PRELIM\n-\thex \"Preliminary value for BR0\"\n-\tdepends on SYS_BR0_PRELIM_BOOL\n-\n-config SYS_OR0_PRELIM\n-\thex \"Preliminary value for OR0\"\n-\tdepends on SYS_BR0_PRELIM_BOOL\n-\n-config SYS_BR1_PRELIM_BOOL\n-\tbool \"Define Bank 1\"\n-\n-config SYS_BR1_PRELIM\n-\thex \"Preliminary value for BR1\"\n-\tdepends on SYS_BR1_PRELIM_BOOL\n-\n-config SYS_OR1_PRELIM\n-\thex \"Preliminary value for OR1\"\n-\tdepends on SYS_BR1_PRELIM_BOOL\n-\n-config SYS_BR2_PRELIM_BOOL\n-\tbool \"Define Bank 2\"\n-\n-config SYS_BR2_PRELIM\n-\thex \"Preliminary value for BR2\"\n-\tdepends on SYS_BR2_PRELIM_BOOL\n-\n-config SYS_OR2_PRELIM\n-\thex \"Preliminary value for OR2\"\n-\tdepends on SYS_BR2_PRELIM_BOOL\n-\n-config SYS_BR3_PRELIM_BOOL\n-\tbool \"Define Bank 3\"\n-\n-config SYS_BR3_PRELIM\n-\thex \"Preliminary value for BR3\"\n-\tdepends on SYS_BR3_PRELIM_BOOL\n-\n-config SYS_OR3_PRELIM\n-\thex \"Preliminary value for OR3\"\n-\tdepends on SYS_BR3_PRELIM_BOOL\n-\n-config SYS_BR4_PRELIM_BOOL\n-\tbool \"Define Bank 4\"\n-\n-config SYS_BR4_PRELIM\n-\thex \"Preliminary value for BR4\"\n-\tdepends on SYS_BR4_PRELIM_BOOL\n-\n-config SYS_OR4_PRELIM\n-\thex \"Preliminary value for OR4\"\n-\tdepends on SYS_BR4_PRELIM_BOOL\n-\n-config SYS_BR5_PRELIM_BOOL\n-\tbool \"Define Bank 5\"\n-\n-config SYS_BR5_PRELIM\n-\thex \"Preliminary value for BR5\"\n-\tdepends on SYS_BR5_PRELIM_BOOL\n-\n-config SYS_OR5_PRELIM\n-\thex \"Preliminary value for OR5\"\n-\tdepends on SYS_BR5_PRELIM_BOOL\n-\n-config SYS_BR6_PRELIM_BOOL\n-\tbool \"Define Bank 6\"\n-\n-config SYS_BR6_PRELIM\n-\thex \"Preliminary value for BR6\"\n-\tdepends on SYS_BR6_PRELIM_BOOL\n-\n-config SYS_OR6_PRELIM\n-\thex \"Preliminary value for OR6\"\n-\tdepends on SYS_BR6_PRELIM_BOOL\n-\n-config SYS_BR7_PRELIM_BOOL\n-\tbool \"Define Bank 7\"\n-\n-config SYS_BR7_PRELIM\n-\thex \"Preliminary value for BR7\"\n-\tdepends on SYS_BR7_PRELIM_BOOL\n-\n-config SYS_OR7_PRELIM\n-\thex \"Preliminary value for OR7\"\n-\tdepends on SYS_BR7_PRELIM_BOOL\n-endmenu\n-\n config SYS_FSL_ERRATUM_A008378\n \tbool\n \ndiff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h\nindex b8918680c14a..6c271e1b3358 100644\n--- a/include/configs/M5272C3.h\n+++ b/include/configs/M5272C3.h\n@@ -124,6 +124,26 @@\n \t\t\t\t\t CF_CACR_CEIB | CF_CACR_DCM | \\\n \t\t\t\t\t CF_CACR_EUSP)\n \n+/*-----------------------------------------------------------------------\n+ * Memory bank definitions\n+ */\n+#define CONFIG_SYS_BR0_PRELIM\t\t0xFFE00201\n+#define CONFIG_SYS_OR0_PRELIM\t\t0xFFE00014\n+#define CONFIG_SYS_BR1_PRELIM\t\t0\n+#define CONFIG_SYS_OR1_PRELIM\t\t0\n+#define CONFIG_SYS_BR2_PRELIM\t\t0x30000001\n+#define CONFIG_SYS_OR2_PRELIM\t\t0xFFF80000\n+#define CONFIG_SYS_BR3_PRELIM\t\t0\n+#define CONFIG_SYS_OR3_PRELIM\t\t0\n+#define CONFIG_SYS_BR4_PRELIM\t\t0\n+#define CONFIG_SYS_OR4_PRELIM\t\t0\n+#define CONFIG_SYS_BR5_PRELIM\t\t0\n+#define CONFIG_SYS_OR5_PRELIM\t\t0\n+#define CONFIG_SYS_BR6_PRELIM\t\t0\n+#define CONFIG_SYS_OR6_PRELIM\t\t0\n+#define CONFIG_SYS_BR7_PRELIM\t\t0x00000701\n+#define CONFIG_SYS_OR7_PRELIM\t\t0xFFC0007C\n+\n /*-----------------------------------------------------------------------\n  * Port configuration\n  */\ndiff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h\nindex 244f811ff65b..46b651c7f54e 100644\n--- a/include/configs/MPC8548CDS.h\n+++ b/include/configs/MPC8548CDS.h\n@@ -127,6 +127,14 @@\n #define CONFIG_SYS_FLASH_BASE_PHYS\tCONFIG_SYS_FLASH_BASE\n #endif\n \n+#define CONFIG_SYS_BR0_PRELIM \\\n+\t(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V)\n+#define CONFIG_SYS_BR1_PRELIM \\\n+\t(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)\n+\n+#define\tCONFIG_SYS_OR0_PRELIM\t\t0xff806e65\n+#define\tCONFIG_SYS_OR1_PRELIM\t\t0xff806e65\n+\n #define CONFIG_SYS_FLASH_BANKS_LIST \\\n \t{CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}\n #define CONFIG_SYS_MAX_FLASH_SECT\t128\t\t/* sectors per device */\n@@ -167,6 +175,10 @@\n  * FIXME: the top 17 bits of BR2.\n  */\n \n+#define CONFIG_SYS_BR2_PRELIM \\\n+\t(BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \\\n+\t| BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V)\n+\n /*\n  * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.\n  *\n@@ -181,6 +193,8 @@\n  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901\n  */\n \n+#define CONFIG_SYS_OR2_PRELIM\t\t0xfc006901\n+\n #define CONFIG_SYS_LBC_LCRR\t\t0x00030004\t/* LB clock ratio reg */\n #define CONFIG_SYS_LBC_LBCR\t\t0x00000000\t/* LB config reg */\n #define CONFIG_SYS_LBC_LSRT\t\t0x20000000\t/* LB sdram refresh timer */\n@@ -239,6 +253,9 @@\n #else\n #define CADMUS_BASE_ADDR_PHYS\tCADMUS_BASE_ADDR\n #endif\n+#define CONFIG_SYS_BR3_PRELIM \\\n+\t(BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V)\n+#define CONFIG_SYS_OR3_PRELIM\t 0xfff00ff7\n \n #define CONFIG_SYS_INIT_RAM_LOCK\t1\n #define CONFIG_SYS_INIT_RAM_ADDR\t0xe4010000\t/* Initial RAM address */\ndiff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h\nindex 3d9e3e1c78b7..687b88bd2abd 100644\n--- a/include/configs/P2041RDB.h\n+++ b/include/configs/P2041RDB.h\n@@ -129,6 +129,9 @@\n #define CPLD_BASE_PHYS\t\tCPLD_BASE\n #endif\n \n+#define CONFIG_SYS_BR3_PRELIM\t(BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)\n+#define CONFIG_SYS_OR3_PRELIM\t0xffffeff7\t/* 32KB but only 4k mapped */\n+\n #define PIXIS_LBMAP_SWITCH\t7\n #define PIXIS_LBMAP_MASK\t0xf0\n #define PIXIS_LBMAP_SHIFT\t4\n@@ -171,6 +174,21 @@\n \t\t\t       | OR_FCM_SCY_1 \\\n \t\t\t       | OR_FCM_TRLX \\\n \t\t\t       | OR_FCM_EHTR)\n+\n+#ifdef CONFIG_MTD_RAW_NAND\n+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */\n+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */\n+#define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */\n+#define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */\n+#else\n+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */\n+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */\n+#define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */\n+#define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */\n+#endif\n+#else\n+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */\n+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */\n #endif /* CONFIG_NAND_FSL_ELBC */\n \n #define CONFIG_SYS_FLASH_EMPTY_INFO\ndiff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h\nindex 1822ce5120ac..3d49a15232b5 100644\n--- a/include/configs/cobra5272.h\n+++ b/include/configs/cobra5272.h\n@@ -222,6 +222,36 @@ enter a valid image address in flash */\n \t\t\t\t\t CF_CACR_CEIB | CF_CACR_DCM | \\\n \t\t\t\t\t CF_CACR_EUSP)\n \n+/*-----------------------------------------------------------------------\n+ * Memory bank definitions\n+ *\n+ * Please refer also to Motorola Coldfire user manual - Chapter XXX\n+ * <http://e-www.motorola.com/files/dsp/doc/ref_manual/MCF5272UM.pdf>\n+ */\n+#define CONFIG_SYS_BR0_PRELIM\t\t0xFFE00201\n+#define CONFIG_SYS_OR0_PRELIM\t\t0xFFE00014\n+\n+#define CONFIG_SYS_BR1_PRELIM\t\t0\n+#define CONFIG_SYS_OR1_PRELIM\t\t0\n+\n+#define CONFIG_SYS_BR2_PRELIM\t\t0\n+#define CONFIG_SYS_OR2_PRELIM\t\t0\n+\n+#define CONFIG_SYS_BR3_PRELIM\t\t0\n+#define CONFIG_SYS_OR3_PRELIM\t\t0\n+\n+#define CONFIG_SYS_BR4_PRELIM\t\t0\n+#define CONFIG_SYS_OR4_PRELIM\t\t0\n+\n+#define CONFIG_SYS_BR5_PRELIM\t\t0\n+#define CONFIG_SYS_OR5_PRELIM\t\t0\n+\n+#define CONFIG_SYS_BR6_PRELIM\t\t0\n+#define CONFIG_SYS_OR6_PRELIM\t\t0\n+\n+#define CONFIG_SYS_BR7_PRELIM\t\t0x00000701\n+#define CONFIG_SYS_OR7_PRELIM\t\t0xFF00007C\n+\n /*-----------------------------------------------------------------------\n  * LED config\n  */\ndiff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h\nindex 121963fe5ce5..9108f206b696 100644\n--- a/include/configs/corenet_ds.h\n+++ b/include/configs/corenet_ds.h\n@@ -120,6 +120,10 @@\n #define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \\\n \t\t\t\t\t| OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)\n \n+#define CONFIG_SYS_BR1_PRELIM \\\n+\t(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)\n+#define CONFIG_SYS_OR1_PRELIM\t0xf8000ff7\n+\n #define PIXIS_BASE\t\t0xffdf0000\t/* PIXIS registers */\n #ifdef CONFIG_PHYS_64BIT\n #define PIXIS_BASE_PHYS\t\t0xfffdf0000ull\n@@ -127,6 +131,9 @@\n #define PIXIS_BASE_PHYS\t\tPIXIS_BASE\n #endif\n \n+#define CONFIG_SYS_BR3_PRELIM\t(BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)\n+#define CONFIG_SYS_OR3_PRELIM\t0xffffeff7\t/* 32KB but only 4k mapped */\n+\n #define PIXIS_LBMAP_SWITCH\t7\n #define PIXIS_LBMAP_MASK\t0xf0\n #define PIXIS_LBMAP_SHIFT\t4\n@@ -169,6 +176,21 @@\n \t\t\t       | OR_FCM_SCY_1 \\\n \t\t\t       | OR_FCM_TRLX \\\n \t\t\t       | OR_FCM_EHTR)\n+\n+#ifdef CONFIG_MTD_RAW_NAND\n+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */\n+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */\n+#define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */\n+#define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */\n+#else\n+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */\n+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */\n+#define CONFIG_SYS_BR2_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */\n+#define CONFIG_SYS_OR2_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */\n+#endif\n+#else\n+#define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */\n+#define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */\n #endif /* CONFIG_NAND_FSL_ELBC */\n \n #define CONFIG_SYS_FLASH_EMPTY_INFO\ndiff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h\nindex f6ecf2a7a8b8..648d941c59b2 100644\n--- a/include/configs/p1_p2_rdb_pc.h\n+++ b/include/configs/p1_p2_rdb_pc.h\n@@ -332,6 +332,22 @@\n \t\t\t\t OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \\\n \t\t\t\t OR_GPCM_EAD)\n \n+#ifdef CONFIG_MTD_RAW_NAND\n+#define CONFIG_SYS_BR0_PRELIM\tCONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */\n+#define CONFIG_SYS_OR0_PRELIM\tCONFIG_SYS_NAND_OR_PRELIM /* NAND Options */\n+#define CONFIG_SYS_BR1_PRELIM\tCONFIG_FLASH_BR_PRELIM\t/* NOR Base Address */\n+#define CONFIG_SYS_OR1_PRELIM\tCONFIG_FLASH_OR_PRELIM\t/* NOR Options */\n+#else\n+#define CONFIG_SYS_BR0_PRELIM\tCONFIG_FLASH_BR_PRELIM\t/* NOR Base Address */\n+#define CONFIG_SYS_OR0_PRELIM\tCONFIG_FLASH_OR_PRELIM\t/* NOR Options */\n+#ifdef CONFIG_NAND_FSL_ELBC\n+#define CONFIG_SYS_BR1_PRELIM\tCONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */\n+#define CONFIG_SYS_OR1_PRELIM\tCONFIG_SYS_NAND_OR_PRELIM /* NAND Options */\n+#endif\n+#endif\n+#define CONFIG_SYS_BR3_PRELIM\tCONFIG_CPLD_BR_PRELIM\t/* CPLD Base Address */\n+#define CONFIG_SYS_OR3_PRELIM\tCONFIG_CPLD_OR_PRELIM\t/* CPLD Options */\n+\n /* Vsc7385 switch */\n #ifdef CONFIG_VSC7385_ENET\n #define __VSCFW_ADDR\t\t\t\"vscfw_addr=ef000000\\0\"\n@@ -349,6 +365,9 @@\n \t\t\tOR_GPCM_XACS |  OR_GPCM_SCY_15 | OR_GPCM_SETA | \\\n \t\t\tOR_GPCM_TRLX |  OR_GPCM_EHTR | OR_GPCM_EAD)\n \n+#define CONFIG_SYS_BR2_PRELIM\tCONFIG_SYS_VSC7385_BR_PRELIM\n+#define CONFIG_SYS_OR2_PRELIM\tCONFIG_SYS_VSC7385_OR_PRELIM\n+\n /* The size of the VSC7385 firmware image */\n #define CONFIG_VSC7385_IMAGE_SIZE\t8192\n #endif\ndiff --git a/include/configs/socrates.h b/include/configs/socrates.h\nindex daba8278c6a3..2644fca25573 100644\n--- a/include/configs/socrates.h\n+++ b/include/configs/socrates.h\n@@ -89,6 +89,11 @@\n #define CONFIG_SYS_LBC_FLASH_BASE\tCONFIG_SYS_FLASH1\t/* Localbus flash start\t*/\n #define CONFIG_SYS_FLASH_BASE\t\tCONFIG_SYS_LBC_FLASH_BASE /* start of FLASH\t*/\n \n+#define CONFIG_SYS_BR0_PRELIM\t\t0xfe001001\t/* port size 16bit\t*/\n+#define CONFIG_SYS_OR0_PRELIM\t\t0xfe000030\t/* 32MB Flash\t\t*/\n+#define CONFIG_SYS_BR1_PRELIM\t\t0xfc001001\t/* port size 16bit\t*/\n+#define CONFIG_SYS_OR1_PRELIM\t\t0xfe000030\t/* 32MB Flash\t\t*/\n+\n #define CONFIG_SYS_MAX_FLASH_SECT\t256\t\t/* sectors per device\t*/\n #undef\tCONFIG_SYS_FLASH_CHECKSUM\n #define CONFIG_SYS_FLASH_ERASE_TOUT\t60000\t/* Flash Erase Timeout (ms)\t*/\n@@ -112,6 +117,8 @@\n #define CONFIG_SYS_FPGA_BASE\t\t0xc0000000\n #define CONFIG_SYS_FPGA_SIZE\t\t0x00100000\t/* 1 MB\t\t*/\n #define CONFIG_SYS_HMI_BASE\t\t0xc0010000\n+#define CONFIG_SYS_BR3_PRELIM\t\t0xc0001881\t/* UPMA, 32-bit */\n+#define CONFIG_SYS_OR3_PRELIM\t\t0xfff00000\t/* 1 MB\t\t*/\n \n #define CONFIG_SYS_NAND_BASE\t\t(CONFIG_SYS_FPGA_BASE + 0x70)\n #define CONFIG_SYS_MAX_NAND_DEVICE\t1\n@@ -119,6 +126,8 @@\n /* LIME GDC */\n #define CONFIG_SYS_LIME_BASE\t\t0xc8000000\n #define CONFIG_SYS_LIME_SIZE\t\t0x04000000\t/* 64 MB\t*/\n+#define CONFIG_SYS_BR2_PRELIM\t\t0xc80018a1\t/* UPMB, 32-bit\t*/\n+#define CONFIG_SYS_OR2_PRELIM\t\t0xfc000000\t/* 64 MB\t*/\n \n #define CONFIG_SYS_SPD_BUS_NUM 0\n \ndiff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt\nindex 5b882b2670ca..f11b764d8b11 100644\n--- a/scripts/config_whitelist.txt\n+++ b/scripts/config_whitelist.txt\n@@ -13,6 +13,8 @@ CONFIG_BS_HDR_ADDR_RAM\n CONFIG_BS_HDR_SIZE\n CONFIG_BS_SIZE\n CONFIG_CHAIN_BOOT_CMD\n+CONFIG_CPLD_BR_PRELIM\n+CONFIG_CPLD_OR_PRELIM\n CONFIG_DEFAULT\n CONFIG_DFU_ALT\n CONFIG_DFU_ALT_BOOT_EMMC\n@@ -659,6 +661,14 @@ CONFIG_SYS_BOOTM_LEN\n CONFIG_SYS_BOOTPARAMS_LEN\n CONFIG_SYS_BOOT_BLOCK\n CONFIG_SYS_BOOT_RAMDISK_HIGH\n+CONFIG_SYS_BR0_PRELIM\n+CONFIG_SYS_BR1_PRELIM\n+CONFIG_SYS_BR2_PRELIM\n+CONFIG_SYS_BR3_PRELIM\n+CONFIG_SYS_BR4_PRELIM\n+CONFIG_SYS_BR5_PRELIM\n+CONFIG_SYS_BR6_PRELIM\n+CONFIG_SYS_BR7_PRELIM\n CONFIG_SYS_CACHE_ACR0\n CONFIG_SYS_CACHE_ACR1\n CONFIG_SYS_CACHE_ACR2\n@@ -1413,6 +1423,14 @@ CONFIG_SYS_OHCI_SWAP_REG_ACCESS\n CONFIG_SYS_OMAP_ABE_SYSCK\n CONFIG_SYS_ONENAND_BASE\n CONFIG_SYS_ONENAND_BLOCK_SIZE\n+CONFIG_SYS_OR0_PRELIM\n+CONFIG_SYS_OR1_PRELIM\n+CONFIG_SYS_OR2_PRELIM\n+CONFIG_SYS_OR3_PRELIM\n+CONFIG_SYS_OR4_PRELIM\n+CONFIG_SYS_OR5_PRELIM\n+CONFIG_SYS_OR6_PRELIM\n+CONFIG_SYS_OR7_PRELIM\n CONFIG_SYS_OR_TIMING_MRAM\n CONFIG_SYS_OSCIN_FREQ\n CONFIG_SYS_OSPR_OFFSET\n",
    "prefixes": [
        "1/6"
    ]
}