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GET /api/patches/1624911/?format=api
{ "id": 1624911, "url": "http://patchwork.ozlabs.org/api/patches/1624911/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20220501142357.16778-4-pali@kernel.org/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20220501142357.16778-4-pali@kernel.org>", "list_archive_url": null, "date": "2022-05-01T14:23:54", "name": "[3/6] mpc85xx: Replace magic values in BR/OR PRELIM config options by proper C macros", "commit_ref": null, "pull_url": null, "state": "rejected", "archived": false, "hash": "024048c042cc3753ebfa0874d25df3859fe14d51", "submitter": { "id": 78810, "url": "http://patchwork.ozlabs.org/api/people/78810/?format=api", "name": "Pali Rohár", "email": "pali@kernel.org" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20220501142357.16778-4-pali@kernel.org/mbox/", "series": [ { "id": 297864, "url": "http://patchwork.ozlabs.org/api/series/297864/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=297864", "date": "2022-05-01T14:23:51", "name": "board: freescale: p1_p2_rdb_pc: Fix sizes of LBC peripherals", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/297864/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1624911/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1624911/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "bilbo.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=IzXjJcNu;\n\tdkim-atps=neutral", "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=kernel.org", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.b=\"IzXjJcNu\";\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=kernel.org", "phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (2048 bits))\n\t(No client certificate requested)\n\tby bilbo.ozlabs.org (Postfix) with ESMTPS id 4KrpSt6Nstz9s2R\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 2 May 2022 00:26:54 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id EC15583F40;\n\tSun, 1 May 2022 16:26:15 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id E456883F1F; Sun, 1 May 2022 16:26:06 +0200 (CEST)", "from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n bits)) (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 6B2D683F1C\n for <u-boot@lists.denx.de>; Sun, 1 May 2022 16:25:59 +0200 (CEST)", "from smtp.kernel.org (relay.kernel.org [52.25.139.140])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n (No client certificate requested)\n by dfw.source.kernel.org (Postfix) with ESMTPS id 1F26C60EDC;\n Sun, 1 May 2022 14:25:58 +0000 (UTC)", "by smtp.kernel.org (Postfix) with ESMTPSA id 2F635C385B2;\n Sun, 1 May 2022 14:25:57 +0000 (UTC)", "by pali.im (Postfix)\n id D8DC39E6; Sun, 1 May 2022 16:25:54 +0200 (CEST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,\n DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,\n SPF_PASS,UPPERCASE_50_75 autolearn=ham autolearn_force=no version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n s=k20201202; t=1651415157;\n bh=cskR7EjwS4sKt1CuLgJa1oRCqtwYlRRLvSBLq7l/5FA=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=IzXjJcNuSyC6IyGKcxeaAjnXUwXW92ak4KEe9pJFFN32hPTAEjcvoVNpxzeP5zem+\n ZdiB+7zEhfTe3GW4emYw22Y1cuW1apAKs9HTojPh9Z7Fm1HSoqpYjXm6lt2uS64DnH\n Ksp+F+DCUbv1SN+1/yu1fHbh81ctzY2cZUfN2pI2Q+E7q+sZ8LtJJJEMJISmltYmQM\n tOr5MHrZUzVQWsgJFwzLxzOpNg66LlqGybhlEWIzrc8ssd+WwVAtgn/1DTSxNd73i+\n qf3XmUGiVF9RI0QYgt3MXE1Fhify8Errzjkmdn+aE73e3/vJu0EabKQI2qv2046KHg\n N46h2Q60ShNuQ==", "From": "=?utf-8?q?Pali_Roh=C3=A1r?= <pali@kernel.org>", "To": "Tom Rini <trini@konsulko.com>", "Cc": "u-boot@lists.denx.de", "Subject": "[PATCH 3/6] mpc85xx: Replace magic values in BR/OR PRELIM config\n options by proper C macros", "Date": "Sun, 1 May 2022 16:23:54 +0200", "Message-Id": "<20220501142357.16778-4-pali@kernel.org>", "X-Mailer": "git-send-email 2.20.1", "In-Reply-To": "<20220501142357.16778-1-pali@kernel.org>", "References": "<20220501142357.16778-1-pali@kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.5 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "This change allows to understand how are Preliminary Base and Option\nregisters configured and later fix improper configuration.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\n---\n include/configs/P2041RDB.h | 7 ++++---\n include/configs/corenet_ds.h | 8 +++++---\n include/configs/p1_p2_rdb_pc.h | 11 ++++++++---\n 3 files changed, 17 insertions(+), 9 deletions(-)", "diff": "diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h\nindex 687b88bd2abd..c2d7c76f6063 100644\n--- a/include/configs/P2041RDB.h\n+++ b/include/configs/P2041RDB.h\n@@ -118,7 +118,8 @@\n \t\t(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \\\n \t\tBR_PS_16 | BR_V)\n #define CONFIG_SYS_FLASH_OR_PRELIM \\\n-\t\t((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \\\n+\t\t(OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 \\\n+\t\t | OR_GPCM_XACS | OR_GPCM_TRLX | OR_GPCM_EAD \\\n \t\t | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)\n \n #define CONFIG_FSL_CPLD\n@@ -162,11 +163,11 @@\n \n /* NAND flash config */\n #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \\\n-\t\t\t | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \\\n+\t\t\t | BR_DECC_CHK_GEN /* Use HW ECC */ \\\n \t\t\t | BR_PS_8\t /* Port Size = 8 bit */ \\\n \t\t\t | BR_MS_FCM\t /* MSEL = FCM */ \\\n \t\t\t | BR_V)\t\t /* valid */\n-#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000\t /* length 256K */ \\\n+#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB\t /* length 256K */ \\\n \t\t\t | OR_FCM_PGS\t /* Large Page*/ \\\n \t\t\t | OR_FCM_CSCT \\\n \t\t\t | OR_FCM_CST \\\ndiff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h\nindex 9108f206b696..c908269b24c7 100644\n--- a/include/configs/corenet_ds.h\n+++ b/include/configs/corenet_ds.h\n@@ -117,7 +117,9 @@\n #define CONFIG_SYS_FLASH_BR_PRELIM \\\n \t\t(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \\\n \t\t | BR_PS_16 | BR_V)\n-#define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \\\n+#define CONFIG_SYS_FLASH_OR_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | \\\n+\t\t\t\t\t| OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \\\n+\t\t\t\t\t| OR_GPCM_TRLX | OR_GPCM_EAD \\\n \t\t\t\t\t| OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)\n \n #define CONFIG_SYS_BR1_PRELIM \\\n@@ -164,11 +166,11 @@\n \n /* NAND flash config */\n #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \\\n-\t\t\t | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \\\n+\t\t\t | BR_DECC_CHK_GEN /* Use HW ECC */ \\\n \t\t\t | BR_PS_8\t /* Port Size = 8 bit */ \\\n \t\t\t | BR_MS_FCM\t /* MSEL = FCM */ \\\n \t\t\t | BR_V)\t\t /* valid */\n-#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000\t /* length 256K */ \\\n+#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB\t /* length 256K */ \\\n \t\t\t | OR_FCM_PGS\t /* Large Page*/ \\\n \t\t\t | OR_FCM_CSCT \\\n \t\t\t | OR_FCM_CST \\\ndiff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h\nindex 9726ef3077f7..b567eb1a03cc 100644\n--- a/include/configs/p1_p2_rdb_pc.h\n+++ b/include/configs/p1_p2_rdb_pc.h\n@@ -243,7 +243,10 @@\n #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \\\n \t| BR_PS_16 | BR_V)\n \n-#define CONFIG_FLASH_OR_PRELIM\t0xfc000ff7\n+#define CONFIG_FLASH_OR_PRELIM\t\t(OR_AM_64MB | OR_GPCM_CSNT | \\\n+\t\t\t\t\t OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | \\\n+\t\t\t\t\t OR_GPCM_SCY_15 | OR_GPCM_TRLX | \\\n+\t\t\t\t\t OR_GPCM_EHTR | OR_GPCM_EAD)\n \n #define CONFIG_SYS_FLASH_BANKS_LIST\t{CONFIG_SYS_FLASH_BASE_PHYS}\n #define CONFIG_SYS_FLASH_QUIET_TEST\n@@ -268,7 +271,7 @@\n #define CONFIG_SYS_MAX_NAND_DEVICE\t1\n \n #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \\\n-\t| (2<<BR_DECC_SHIFT)\t/* Use HW ECC */ \\\n+\t| BR_DECC_CHK_GEN\t/* Use HW ECC */ \\\n \t| BR_PS_8\t/* Port Size = 8 bit */ \\\n \t| BR_MS_FCM\t/* MSEL = FCM */ \\\n \t| BR_V)\t/* valid */\n@@ -325,7 +328,9 @@\n /* CPLD config size: 1Mb */\n #define CONFIG_CPLD_BR_PRELIM\t(BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \\\n \t\t\t\t\tBR_PS_8 | BR_V)\n-#define CONFIG_CPLD_OR_PRELIM\t(0xfff009f7)\n+#define CONFIG_CPLD_OR_PRELIM\t(OR_AM_1MB | OR_GPCM_CSNT | OR_GPCM_XACS | \\\n+\t\t\t\t\tOR_GPCM_SCY_15 | OR_GPCM_TRLX | \\\n+\t\t\t\t\tOR_GPCM_EHTR | OR_GPCM_EAD)\n \n #define CONFIG_SYS_PMC_BASE\t0xff980000\n #define CONFIG_SYS_PMC_BASE_PHYS\tCONFIG_SYS_PMC_BASE\n", "prefixes": [ "3/6" ] }