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GET /api/patches/1624908/?format=api
{ "id": 1624908, "url": "http://patchwork.ozlabs.org/api/patches/1624908/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20220501142357.16778-5-pali@kernel.org/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20220501142357.16778-5-pali@kernel.org>", "list_archive_url": null, "date": "2022-05-01T14:23:55", "name": "[4/6] board: freescale: p1_p2_rdb_pc: Fix size of CPLD mapping", "commit_ref": null, "pull_url": null, "state": "rejected", "archived": false, "hash": "8857b4aad13b9dcec0329838f9d172ae535e0eb3", "submitter": { "id": 78810, "url": "http://patchwork.ozlabs.org/api/people/78810/?format=api", "name": "Pali Rohár", "email": "pali@kernel.org" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20220501142357.16778-5-pali@kernel.org/mbox/", "series": [ { "id": 297864, "url": "http://patchwork.ozlabs.org/api/series/297864/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=297864", "date": "2022-05-01T14:23:51", "name": "board: freescale: p1_p2_rdb_pc: Fix sizes of LBC peripherals", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/297864/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1624908/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1624908/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "bilbo.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=NDSBqNY6;\n\tdkim-atps=neutral", "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=kernel.org", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.b=\"NDSBqNY6\";\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=kernel.org", "phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (2048 bits))\n\t(No client certificate requested)\n\tby bilbo.ozlabs.org (Postfix) with ESMTPS id 4KrpSJ1g7xz9s2R\n\tfor <incoming@patchwork.ozlabs.org>; Mon, 2 May 2022 00:26:24 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 0FC2E83F0E;\n\tSun, 1 May 2022 16:26:09 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id 8263383DDA; Sun, 1 May 2022 16:26:05 +0200 (CEST)", "from dfw.source.kernel.org (dfw.source.kernel.org\n [IPv6:2604:1380:4641:c500::1])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 5EE7383DDA\n for <u-boot@lists.denx.de>; Sun, 1 May 2022 16:25:58 +0200 (CEST)", "from smtp.kernel.org (relay.kernel.org [52.25.139.140])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n (No client certificate requested)\n by dfw.source.kernel.org (Postfix) with ESMTPS id D805060DDC;\n Sun, 1 May 2022 14:25:56 +0000 (UTC)", "by smtp.kernel.org (Postfix) with ESMTPSA id 236E6C385B1;\n Sun, 1 May 2022 14:25:56 +0000 (UTC)", "by pali.im (Postfix)\n id D1DB5942; Sun, 1 May 2022 16:25:55 +0200 (CEST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.7 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,\n DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,\n SPF_PASS autolearn=ham autolearn_force=no version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n s=k20201202; t=1651415156;\n bh=uDPKnPFPp7fJ4IDkAZEKVPNGExYRlZHX0Wra/JKAqas=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=NDSBqNY6dJu4kB8ToBh0GpaIiMmjSMYXnuMyMflLkV6/iF2D1+bzANZjDa9qd4GCD\n wfB+ekOpye+d9Fq1F/HpwybIM8n51k6CyBqyXJBraHBitplXOmw4Pvgf0FYUAB33IZ\n 6uwswmjWgDmG8ESfHq+1ocNwaxRXNgUumJV2fGBobY+E45yZUPD8fU4MrRwfVhAYkk\n ajIQMkaf+xrsXHGrq4DCiS7JRi5h+z6IjnaqKb9d9CIKCwHc7iKwA0Z/HasilYkMfN\n TCj6dOjPSVaWCBc5D3FGiGLT6x+iV90wyP1bifkmF+QwzzUtcHCulSZBLn8LnpoEM7\n 04wDWIcr3A8og==", "From": "=?utf-8?q?Pali_Roh=C3=A1r?= <pali@kernel.org>", "To": "Tom Rini <trini@konsulko.com>", "Cc": "u-boot@lists.denx.de", "Subject": "[PATCH 4/6] board: freescale: p1_p2_rdb_pc: Fix size of CPLD mapping", "Date": "Sun, 1 May 2022 16:23:55 +0200", "Message-Id": "<20220501142357.16778-5-pali@kernel.org>", "X-Mailer": "git-send-email 2.20.1", "In-Reply-To": "<20220501142357.16778-1-pali@kernel.org>", "References": "<20220501142357.16778-1-pali@kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.5 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Per Freescale P1021RDB Combo board CPLD Specification V4.2, CPLD memory\nspace on all these P1/P2 RDB-PC boards, which use Lattice FPGA for CPLD\nimplementation, is only 128 kB long.\n\nSo decrease mapping size from 1 MB to 128 kB.\n\nNote that E500 core, which is on P1/P2 boards does not support Book-E page\nsize of 128 kB. It ignores lowest bit in size definition, so macro\nBOOKE_PAGESZ_128K has same effect as BOOKE_PAGESZ_64K. Therefore for TLB\nentry use BOOKE_PAGESZ_256K to cover whole 128 kB of CPLD memory space.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\n---\n board/freescale/p1_p2_rdb_pc/law.c | 2 +-\n board/freescale/p1_p2_rdb_pc/tlb.c | 3 ++-\n include/configs/p1_p2_rdb_pc.h | 6 +++---\n 3 files changed, 6 insertions(+), 5 deletions(-)", "diff": "diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c\nindex 5f4d713ca569..901145ded3b0 100644\n--- a/board/freescale/p1_p2_rdb_pc/law.c\n+++ b/board/freescale/p1_p2_rdb_pc/law.c\n@@ -8,7 +8,7 @@\n #include <asm/mmu.h>\n \n struct law_entry law_table[] = {\n-\tSET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),\n+\tSET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_LBC),\n \tSET_LAW(CONFIG_SYS_PMC_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),\n #ifdef CONFIG_VSC7385_ENET\n \tSET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),\ndiff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c\nindex 5931ec650bd8..ca47e15067a4 100644\n--- a/board/freescale/p1_p2_rdb_pc/tlb.c\n+++ b/board/freescale/p1_p2_rdb_pc/tlb.c\n@@ -62,9 +62,10 @@ struct fsl_e_tlb_entry tlb_table[] = {\n \t\t\t0, 5, BOOKE_PAGESZ_1M, 1),\n #endif\n \n+\t/* *I*G - CPLD 256K (effective only 128K; e500 does not support BOOKE_PAGESZ_128K) */\n \tSET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,\n \t\t\tMAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,\n-\t\t\t0, 6, BOOKE_PAGESZ_1M, 1),\n+\t\t\t0, 6, BOOKE_PAGESZ_256K, 1),\n \tSET_TLB_ENTRY(1, CONFIG_SYS_PMC_BASE, CONFIG_SYS_PMC_BASE_PHYS,\n \t\t\tMAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,\n \t\t\t0, 10, BOOKE_PAGESZ_64K, 1),\ndiff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h\nindex b567eb1a03cc..69fbb4ad8fe4 100644\n--- a/include/configs/p1_p2_rdb_pc.h\n+++ b/include/configs/p1_p2_rdb_pc.h\n@@ -216,7 +216,7 @@\n * (early boot only)\n * 0xff80_0000 0xff80_7fff\tNAND flash\t32K non-cacheable\tCS1/0\n * 0xff98_0000 0xff98_ffff\tPMC\t\t64K non-cacheable\tCS2\n- * 0xffa0_0000 0xffaf_ffff\tCPLD\t\t1M non-cacheable\tCS3\n+ * 0xffa0_0000 0xffa1_ffff\tCPLD\t\t128K non-cacheable\tCS3\n * 0xffb0_0000 0xffbf_ffff\tVSC7385 switch 1M non-cacheable\tCS2\n * 0xffc0_0000 0xffc3_ffff\tPCI IO range\t256k non-cacheable\n * 0xffd0_0000 0xffd0_3fff\tL1 for stack\t16K cacheable\n@@ -325,10 +325,10 @@\n #else\n #define CONFIG_SYS_CPLD_BASE_PHYS\tCONFIG_SYS_CPLD_BASE\n #endif\n-/* CPLD config size: 1Mb */\n+/* CPLD config size: 128 kB */\n #define CONFIG_CPLD_BR_PRELIM\t(BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \\\n \t\t\t\t\tBR_PS_8 | BR_V)\n-#define CONFIG_CPLD_OR_PRELIM\t(OR_AM_1MB | OR_GPCM_CSNT | OR_GPCM_XACS | \\\n+#define CONFIG_CPLD_OR_PRELIM\t(OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \\\n \t\t\t\t\tOR_GPCM_SCY_15 | OR_GPCM_TRLX | \\\n \t\t\t\t\tOR_GPCM_EHTR | OR_GPCM_EAD)\n \n", "prefixes": [ "4/6" ] }