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GET /api/patches/1614407/?format=api
{ "id": 1614407, "url": "http://patchwork.ozlabs.org/api/patches/1614407/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20220407101624.15850-6-pali@kernel.org/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20220407101624.15850-6-pali@kernel.org>", "list_archive_url": null, "date": "2022-04-07T10:16:18", "name": "[05/11] board: freescale: p1_p2_rdb_pc: Fix page attributes for second 1G SDRAM map", "commit_ref": "0b30cb3de70fbaa4525d169a6fc09f732b290d97", "pull_url": null, "state": "accepted", "archived": false, "hash": "5f477d14ae37f4385345f8e3071baa6f070b8c77", "submitter": { "id": 78810, "url": "http://patchwork.ozlabs.org/api/people/78810/?format=api", "name": "Pali Rohár", "email": "pali@kernel.org" }, "delegate": { "id": 87636, "url": "http://patchwork.ozlabs.org/api/users/87636/?format=api", "username": "priyankajain", "first_name": "Priyanka", "last_name": "Jain", "email": "priyanka.jain@nxp.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20220407101624.15850-6-pali@kernel.org/mbox/", "series": [ { "id": 293984, "url": "http://patchwork.ozlabs.org/api/series/293984/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=293984", "date": "2022-04-07T10:16:13", "name": "board: freescale: p1_p2_rdb_pc: Various cleanups and fixes", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/293984/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1614407/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1614407/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "bilbo.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=ZKmwSgt4;\n\tdkim-atps=neutral", "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=kernel.org", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.b=\"ZKmwSgt4\";\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=kernel.org", "phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby bilbo.ozlabs.org (Postfix) with ESMTPS id 4KYy6Q19Htz9sGj\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 7 Apr 2022 20:19:26 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id C011983D96;\n\tThu, 7 Apr 2022 12:18:59 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id D0AFA83CD8; Thu, 7 Apr 2022 12:17:52 +0200 (CEST)", "from dfw.source.kernel.org (dfw.source.kernel.org\n [IPv6:2604:1380:4641:c500::1])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 7EDC783C67\n for <u-boot@lists.denx.de>; Thu, 7 Apr 2022 12:17:43 +0200 (CEST)", "from smtp.kernel.org (relay.kernel.org [52.25.139.140])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n (No client certificate requested)\n by dfw.source.kernel.org (Postfix) with ESMTPS id 8AB6861D47;\n Thu, 7 Apr 2022 10:17:41 +0000 (UTC)", "by smtp.kernel.org (Postfix) with ESMTPSA id A99A3C385A6;\n Thu, 7 Apr 2022 10:17:40 +0000 (UTC)", "by pali.im (Postfix)\n id 63AFFC77; Thu, 7 Apr 2022 12:17:39 +0200 (CEST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,\n DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,\n SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no\n version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n s=k20201202; t=1649326660;\n bh=HXg9J0qii8bIiR0gUTN8qDtKdk6lDFrom6xaGkrkQY4=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=ZKmwSgt4KYf99SMMhFHnf3CkDU49vEHJ8Zhy0lpLkMgRUy/Hl2HPAcOSu5Bs5XIPE\n J27y7Qkn04mfdhIfru/s55SP05WWgCuDAV+Kn2Rqsqw1KcAFHfpI/4reoOlUt20vga\n uNYt7IuHG4p3dWS/tKzlrnWgSTP/WxkbPj8wq6xuvanSMlMKnmf3pSMyfrR57JCnbN\n bCIdELZ4hE2n3g6gRJP7F+32ho4amfm8xU+XVt1uBgD8zyq53wKKmlFk3qhG+gHr/1\n GqUTi+9V0O0hstDFfi97t+j7Ws4ObPrQ5loLcbUQzlSAUhGLgz6kybfBhE+VHnlfNj\n TgLKUeLgygLcw==", "From": "=?utf-8?q?Pali_Roh=C3=A1r?= <pali@kernel.org>", "To": "Priyanka Jain <priyanka.jain@nxp.com>, Qiang Zhao <qiang.zhao@nxp.com>,\n Shengzhou Liu <Shengzhou.Liu@nxp.com>, Sinan Akman <sinan@writeme.com>", "Cc": "u-boot@lists.denx.de", "Subject": "[PATCH 05/11] board: freescale: p1_p2_rdb_pc: Fix page attributes for\n second 1G SDRAM map", "Date": "Thu, 7 Apr 2022 12:16:18 +0200", "Message-Id": "<20220407101624.15850-6-pali@kernel.org>", "X-Mailer": "git-send-email 2.20.1", "In-Reply-To": "<20220407101624.15850-1-pali@kernel.org>", "References": "<20220407101624.15850-1-pali@kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.5 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Like for first 1G SDRAM map, do not enable Caching-inhibited nor Guarded\nattribute for second 1G SDRAM mapping. Whole 2G SDRAM should use caches and\nalso allow speculative loading (by not setting Guarded attribute).\n\nAlso enable Memory Coherency attribute for second 1G SDRAM map. In commit\n316f0d0f8f3c (\"powerpc: mpc85xx: Fix static TLB table for SDRAM\") it was\nenabled for all SDRAM maps on all other boards, just missed this one case.\n\nAs a last thing, first 1G SDRAM map has wrong comment, so adjust it.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\n---\n board/freescale/p1_p2_rdb_pc/tlb.c | 6 +++---\n 1 file changed, 3 insertions(+), 3 deletions(-)", "diff": "diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c\nindex fcd7a55199f0..5931ec650bd8 100644\n--- a/board/freescale/p1_p2_rdb_pc/tlb.c\n+++ b/board/freescale/p1_p2_rdb_pc/tlb.c\n@@ -79,16 +79,16 @@ struct fsl_e_tlb_entry tlb_table[] = {\n \n #if defined(CONFIG_SYS_RAMBOOT) || \\\n \t(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))\n-\t/* *I*G - eSDHC/eSPI/NAND boot */\n+\t/* **M** - 1G DDR for eSDHC/eSPI/NAND boot */\n \tSET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,\n \t\t\tMAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,\n \t\t\t0, 8, BOOKE_PAGESZ_1G, 1),\n \n #if defined(CONFIG_TARGET_P1020RDB_PD)\n-\t/* 2G DDR on P1020MBG, map the second 1G */\n+\t/* **M** - 2G DDR on P1020MBG, map the second 1G */\n \tSET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,\n \t\t\tCONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,\n-\t\t\tMAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,\n+\t\t\tMAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,\n \t\t\t0, 9, BOOKE_PAGESZ_1G, 1),\n #endif\n #endif /* RAMBOOT/SPL */\n", "prefixes": [ "05/11" ] }