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GET /api/patches/1614405/?format=api
{ "id": 1614405, "url": "http://patchwork.ozlabs.org/api/patches/1614405/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20220407101624.15850-11-pali@kernel.org/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20220407101624.15850-11-pali@kernel.org>", "list_archive_url": null, "date": "2022-04-07T10:16:23", "name": "[10/11] board: freescale: p1_p2_rdb_pc: Move BootROM change source macros to p1_p2_bootrom.h", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "e9fe89eece4833978e2bb806b0e323f43dfd5b3f", "submitter": { "id": 78810, "url": "http://patchwork.ozlabs.org/api/people/78810/?format=api", "name": "Pali Rohár", "email": "pali@kernel.org" }, "delegate": { "id": 87636, "url": "http://patchwork.ozlabs.org/api/users/87636/?format=api", "username": "priyankajain", "first_name": "Priyanka", "last_name": "Jain", "email": "priyanka.jain@nxp.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20220407101624.15850-11-pali@kernel.org/mbox/", "series": [ { "id": 293984, "url": "http://patchwork.ozlabs.org/api/series/293984/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=293984", "date": "2022-04-07T10:16:13", "name": "board: freescale: p1_p2_rdb_pc: Various cleanups and fixes", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/293984/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1614405/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1614405/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "bilbo.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=uvQlOM9j;\n\tdkim-atps=neutral", "ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=<UNKNOWN>)", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=kernel.org", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.b=\"uvQlOM9j\";\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=kernel.org", "phobos.denx.de; spf=pass smtp.mailfrom=pali@kernel.org" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby bilbo.ozlabs.org (Postfix) with ESMTPS id 4KYy5y4wX1z9sGj\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 7 Apr 2022 20:19:02 +1000 (AEST)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 24ED283CD8;\n\tThu, 7 Apr 2022 12:18:44 +0200 (CEST)", "by phobos.denx.de (Postfix, from userid 109)\n id B8CA1803C8; Thu, 7 Apr 2022 12:17:52 +0200 (CEST)", "from ams.source.kernel.org (ams.source.kernel.org\n [IPv6:2604:1380:4601:e00::1])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id C694E83C8F\n for <u-boot@lists.denx.de>; Thu, 7 Apr 2022 12:17:43 +0200 (CEST)", "from smtp.kernel.org (relay.kernel.org [52.25.139.140])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n (No client certificate requested)\n by ams.source.kernel.org (Postfix) with ESMTPS id 7B449B82718;\n Thu, 7 Apr 2022 10:17:43 +0000 (UTC)", "by smtp.kernel.org (Postfix) with ESMTPSA id F1F58C385A0;\n Thu, 7 Apr 2022 10:17:41 +0000 (UTC)", "by pali.im (Postfix)\n id AC19DB91; Thu, 7 Apr 2022 12:17:41 +0200 (CEST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH,\n DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,\n SPF_PASS,T_SCC_BODY_TEXT_LINE,UPPERCASE_50_75 autolearn=no\n autolearn_force=no version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n s=k20201202; t=1649326662;\n bh=w7vGwJSL8szfJBtVsZ+XPyh2BjylUyF2BBuI4D+D/dU=;\n h=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n b=uvQlOM9jz00Zmz+gaQxsXDRvnhtlC1QbtDNaHOY6Hc/XNTf2TDM+HN3rGLxFThTWX\n zRmi41uFlviQ20LGKOgh4oLKO8eK0eUg8koBuE6lUYMaToWgPAlReYl/cL04regeTN\n 9ggMDNPstBosxNjwkm63U6kJJAq75DHeSnupa3eKczs+lUk//KSqaPe4iEWGUmb060\n D5nlmZ7fgXJ4RVY6EwRwmlQWJlP3o26aNSRp4GwuIxx02aHABZa0BIhVKwDqbmVvX2\n LaW6tPCq9QqSYlGxsjcYS0vkO5s9nLNa0SVrhcZO7gfLW4ArT432nVbund3o4HItH9\n CmV3CW0TAM5ug==", "From": "=?utf-8?q?Pali_Roh=C3=A1r?= <pali@kernel.org>", "To": "Priyanka Jain <priyanka.jain@nxp.com>, Qiang Zhao <qiang.zhao@nxp.com>,\n Shengzhou Liu <Shengzhou.Liu@nxp.com>, Sinan Akman <sinan@writeme.com>", "Cc": "u-boot@lists.denx.de", "Subject": "[PATCH 10/11] board: freescale: p1_p2_rdb_pc: Move BootROM change\n source macros to p1_p2_bootrom.h", "Date": "Thu, 7 Apr 2022 12:16:23 +0200", "Message-Id": "<20220407101624.15850-11-pali@kernel.org>", "X-Mailer": "git-send-email 2.20.1", "In-Reply-To": "<20220407101624.15850-1-pali@kernel.org>", "References": "<20220407101624.15850-1-pali@kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.5 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Code for changing BootROM source is platform generic and can be used by any\nP1* and P2* compatible board. Not only by RDB boards which use config\nheader file p1_p2_rdb_pc.h.\n\nSo move this code from p1_p2_rdb_pc.h to p1_p2_bootrom.h and cleanup macros\nfor generating boot source env variables in CONFIG_EXTRA_ENV_SETTINGS.\n\nThis allows to use code for changing BootROM source also by other boards in\nfuture.\n\nSigned-off-by: Pali Rohár <pali@kernel.org>\n---\n include/configs/p1_p2_bootrom.h | 32 +++++++++++++++\n include/configs/p1_p2_rdb_pc.h | 73 +++++++++++++++++++++------------\n 2 files changed, 78 insertions(+), 27 deletions(-)\n create mode 100644 include/configs/p1_p2_bootrom.h", "diff": "diff --git a/include/configs/p1_p2_bootrom.h b/include/configs/p1_p2_bootrom.h\nnew file mode 100644\nindex 000000000000..a1f61b788cf7\n--- /dev/null\n+++ b/include/configs/p1_p2_bootrom.h\n@@ -0,0 +1,32 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+// (C) 2022 Pali Rohár <pali@kernel.org>\n+\n+#define CHANGE_BOOTROM_SOURCE_CMD(SOURCE, MASK) i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 SOURCE 1; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 MASK 1\n+\n+#ifdef __SW_NOR_BANK_LO\n+#define CHANGE_BOOTROM_LOWER_NOR_BANK_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_NOR_BANK_LO, __SW_NOR_BANK_MASK)\n+#endif\n+\n+#ifdef __SW_NOR_BANK_UP\n+#define CHANGE_BOOTROM_UPPER_NOR_BANK_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_NOR_BANK_UP, __SW_NOR_BANK_MASK)\n+#endif\n+\n+#ifdef __SW_BOOT_NOR\n+#define CHANGE_BOOTROM_SOURCE_DEF_NOR_BANK_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_NOR, __SW_BOOT_MASK)\n+#endif\n+\n+#ifdef __SW_BOOT_SPI\n+#define CHANGE_BOOTROM_SOURCE_SPI_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_SPI, __SW_BOOT_MASK)\n+#endif\n+\n+#ifdef __SW_BOOT_SD\n+#define CHANGE_BOOTROM_SOURCE_SD_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_SD, __SW_BOOT_MASK)\n+#endif\n+\n+#ifdef __SW_BOOT_NAND\n+#define CHANGE_BOOTROM_SOURCE_NAND_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_NAND, __SW_BOOT_MASK)\n+#endif\n+\n+#ifdef __SW_BOOT_PCIE\n+#define CHANGE_BOOTROM_SOURCE_PCIE_CMD CHANGE_BOOTROM_SOURCE_CMD(__SW_BOOT_PCIE, __SW_BOOT_MASK)\n+#endif\ndiff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h\nindex 995bd983cef1..d41b31081017 100644\n--- a/include/configs/p1_p2_rdb_pc.h\n+++ b/include/configs/p1_p2_rdb_pc.h\n@@ -79,6 +79,8 @@\n */\n #endif\n \n+#include \"p1_p2_bootrom.h\"\n+\n #ifdef CONFIG_SDCARD\n #define CONFIG_SPL_FLUSH_IMAGE\n #define CONFIG_SPL_TARGET\t\t\"u-boot-with-spl.bin\"\n@@ -575,30 +577,46 @@\n #define CONFIG_BOOTFILE\t\t\"uImage\"\n #define CONFIG_UBOOTPATH\tu-boot.bin /* U-Boot image on TFTP server */\n \n-#ifdef __SW_BOOT_NOR\n-#define __NOR_RST_CMD\t\\\n-norboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NOR 1; \\\n-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset\n+#ifdef CHANGE_BOOTROM_LOWER_NOR_BANK_CMD\n+#define __MAP_NOR_LOWER_CMD \"map_lowernorbank=\"__stringify(CHANGE_BOOTROM_LOWER_NOR_BANK_CMD)\"\\0\"\n+#else\n+#define __MAP_NOR_LOWER_CMD \"\"\n+#endif\n+\n+#ifdef CHANGE_BOOTROM_UPPER_NOR_BANK_CMD\n+#define __MAP_NOR_UPPER_CMD \"map_uppernorbank=\"__stringify(CHANGE_BOOTROM_UPPER_NOR_BANK_CMD)\"\\0\"\n+#else\n+#define __MAP_NOR_UPPER_CMD \"\"\n+#endif\n+\n+#ifdef CHANGE_BOOTROM_SOURCE_DEF_NOR_BANK_CMD\n+#define __NOR_RST_CMD \"norboot=\"__stringify(CHANGE_BOOTROM_SOURCE_DEF_NOR_BANK_CMD)\"; reset\\0\"\n+#else\n+#define __NOR_RST_CMD \"\"\n #endif\n-#ifdef __SW_BOOT_SPI\n-#define __SPI_RST_CMD\t\\\n-spiboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SPI 1; \\\n-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset\n+\n+#ifdef CHANGE_BOOTROM_SOURCE_SPI_CMD\n+#define __SPI_RST_CMD \"spiboot=\"__stringify(CHANGE_BOOTROM_SOURCE_SPI_CMD)\"; reset\\0\"\n+#else\n+#define __SPI_RST_CMD \"\"\n #endif\n-#ifdef __SW_BOOT_SD\n-#define __SD_RST_CMD\t\\\n-sdboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_SD 1; \\\n-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset\n+\n+#ifdef CHANGE_BOOTROM_SOURCE_SD_CMD\n+#define __SD_RST_CMD \"sdboot=\"__stringify(CHANGE_BOOTROM_SOURCE_SD_CMD)\"; reset\\0\"\n+#else\n+#define __SD_RST_CMD \"\"\n #endif\n-#ifdef __SW_BOOT_NAND\n-#define __NAND_RST_CMD\t\\\n-nandboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_NAND 1; \\\n-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset\n+\n+#ifdef CHANGE_BOOTROM_SOURCE_NAND_CMD\n+#define __NAND_RST_CMD \"nandboot=\"__stringify(CHANGE_BOOTROM_SOURCE_NAND_CMD)\"; reset\\0\"\n+#else\n+#define __NAND_RST_CMD \"\"\n #endif\n-#ifdef __SW_BOOT_PCIE\n-#define __PCIE_RST_CMD\t\\\n-pciboot=i2c dev CONFIG_SYS_SPD_BUS_NUM; i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 1 __SW_BOOT_PCIE 1; \\\n-i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset\n+\n+#ifdef CHANGE_BOOTROM_SOURCE_PCIE_CMD\n+#define __PCIE_RST_CMD \"pciboot=\"__stringify(CHANGE_BOOTROM_SOURCE_PCIE_CMD)\"; reset\\0\"\n+#else\n+#define __PCIE_RST_CMD \"\"\n #endif\n \n #define\tCONFIG_EXTRA_ENV_SETTINGS\t\\\n@@ -626,13 +644,14 @@ i2c mw CONFIG_SYS_I2C_PCA9557_ADDR 3 __SW_BOOT_MASK 1; reset\n \"nandfdtaddr=80000\\0\"\t\t\\\n \"ramdisk_size=120000\\0\"\t\\\n __VSCFW_ADDR\t\\\n-\"map_lowernorbank=i2c dev \"__stringify(CONFIG_SYS_SPD_BUS_NUM)\"; i2c mw \"__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)\" 1 \"__stringify(__SW_NOR_BANK_LO)\" 1; i2c mw \"__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)\" 3 \"__stringify(__SW_NOR_BANK_MASK)\" 1\\0\" \\\n-\"map_uppernorbank=i2c dev \"__stringify(CONFIG_SYS_SPD_BUS_NUM)\"; i2c mw \"__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)\" 1 \"__stringify(__SW_NOR_BANK_UP)\" 1; i2c mw \"__stringify(CONFIG_SYS_I2C_PCA9557_ADDR)\" 3 \"__stringify(__SW_NOR_BANK_MASK)\" 1\\0\" \\\n-__stringify(__NOR_RST_CMD)\"\\0\" \\\n-__stringify(__SPI_RST_CMD)\"\\0\" \\\n-__stringify(__SD_RST_CMD)\"\\0\" \\\n-__stringify(__NAND_RST_CMD)\"\\0\" \\\n-__stringify(__PCIE_RST_CMD)\"\\0\"\n+__MAP_NOR_LOWER_CMD\t\\\n+__MAP_NOR_UPPER_CMD\t\\\n+__NOR_RST_CMD\t\\\n+__SPI_RST_CMD\t\\\n+__SD_RST_CMD\t\\\n+__NAND_RST_CMD\t\\\n+__PCIE_RST_CMD\t\\\n+\"\"\n \n #define CONFIG_USB_FAT_BOOT\t\\\n \"setenv bootargs root=/dev/ram rw \"\t\\\n", "prefixes": [ "10/11" ] }